intel_extreme: skylake/DDI. all displays can set resolution now, no refresh on digital panels yet (DPLL still missing)
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@ -1163,6 +1163,7 @@ struct intel_free_graphics_memory {
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#define PCH_PANEL_FITTER_H_SCALE 0x90
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#define PCH_PANEL_FITTER_H_SCALE 0x90
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#define PANEL_FITTER_ENABLED (1 << 31)
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#define PANEL_FITTER_ENABLED (1 << 31)
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//pipes are hardcoded according to offset on SkyLake and later
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#define PANEL_FITTER_PIPE_MASK (3 << 29)
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#define PANEL_FITTER_PIPE_MASK (3 << 29)
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#define PANEL_FITTER_PIPE_A (0 << 29)
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#define PANEL_FITTER_PIPE_A (0 << 29)
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#define PANEL_FITTER_PIPE_B (1 << 29)
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#define PANEL_FITTER_PIPE_B (1 << 29)
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@ -36,6 +36,10 @@ PanelFitter::PanelFitter(pipe_index pipeIndex)
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:
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:
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fRegisterBase(PCH_PANEL_FITTER_BASE_REGISTER)
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fRegisterBase(PCH_PANEL_FITTER_BASE_REGISTER)
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{
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{
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// SkyLake has a newer type of panelfitter, called panelscaler (PS) there
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if (gInfo->shared_info->device_type.Generation() >= 9) {
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fRegisterBase += 0x100;
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}
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if (pipeIndex == INTEL_PIPE_B) {
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if (pipeIndex == INTEL_PIPE_B) {
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fRegisterBase += PCH_PANEL_FITTER_PIPE_OFFSET;
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fRegisterBase += PCH_PANEL_FITTER_PIPE_OFFSET;
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}
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}
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@ -46,8 +50,12 @@ PanelFitter::PanelFitter(pipe_index pipeIndex)
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uint32 fitCtl = read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL);
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uint32 fitCtl = read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL);
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if (fitCtl & PANEL_FITTER_ENABLED) {
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if (fitCtl & PANEL_FITTER_ENABLED) {
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TRACE("%s: this fitter is connected to pipe #%" B_PRIx32 "\n", __func__,
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if (gInfo->shared_info->device_type.Generation() <= 8) {
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((fitCtl & PANEL_FITTER_PIPE_MASK) >> 29) + 1);
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TRACE("%s: this fitter is connected to pipe #%" B_PRIx32 "\n", __func__,
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((fitCtl & PANEL_FITTER_PIPE_MASK) >> 29) + 1);
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} else {
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TRACE("%s: this fitter is enabled by the BIOS\n", __func__);
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}
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} else {
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} else {
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TRACE("%s: this fitter is not setup by the BIOS\n", __func__);
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TRACE("%s: this fitter is not setup by the BIOS\n", __func__);
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}
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}
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