Temporarily disabled interrupt handling: this fixes a strange symptom that happen
on stippi's and my laptop when connected to a power outlet (no interrupts arrive anymore but timer interrupts). Need to investigate this a bit more... git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16553 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
3a14d2275f
commit
adbba9cd76
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@ -1,101 +1,107 @@
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/*
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Copyright (c) 2002-2004, Thomas Kurschel
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* Copyright 2006, Haiku, Inc. All Rights Reserved.
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* Copyright 2002-2004, Thomas Kurschel
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*
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* Distributed under the terms of the MIT License.
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*/
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Part of Radeon kernel driver
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Interrupt handling. Currently, none of this is used
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as I haven't got the HW spec.
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*/
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#include "radeon_driver.h"
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#include <stdio.h>
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/** Interrupt handling. Currently, none of this is used
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* as I haven't got the HW spec.
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*/
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#include "mmio.h"
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#include "radeon_driver.h"
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#include "rbbm_regs.h"
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#include <stdio.h>
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// disable all interrupts
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static void
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Radeon_DisableIRQ( device_info *di )
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/** Disable all interrupts */
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static void
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Radeon_DisableIRQ(device_info *di)
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{
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OUTREG( di->regs, RADEON_GEN_INT_CNTL, 0 );
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OUTREG(di->regs, RADEON_GEN_INT_CNTL, 0);
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}
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// interrupt worker routine
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// handles standard interrupts, i.e. VBI and DMA
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static uint32
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Radeon_ThreadInterruptWork( vuint8 *regs, device_info *di, uint32 int_status )
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/** Interrupt worker routine
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* handles standard interrupts, i.e. VBI and DMA
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*/
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static uint32
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Radeon_ThreadInterruptWork(vuint8 *regs, device_info *di, uint32 int_status)
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{
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shared_info *si = di->si;
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uint32 handled = B_HANDLED_INTERRUPT;
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if( (int_status & RADEON_CRTC_VBLANK_STAT) != 0 &&
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si->crtc[0].vblank >= 0 )
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{
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if ((int_status & RADEON_CRTC_VBLANK_STAT) != 0
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&& si->crtc[0].vblank >= 0) {
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int32 blocked;
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++di->vbi_count[0];
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if( (get_sem_count( si->crtc[0].vblank, &blocked ) == B_OK) && (blocked < 0) ) {
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release_sem_etc( si->crtc[0].vblank, -blocked, B_DO_NOT_RESCHEDULE );
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if (get_sem_count(si->crtc[0].vblank, &blocked ) == B_OK && blocked < 0) {
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release_sem_etc(si->crtc[0].vblank, -blocked, B_DO_NOT_RESCHEDULE);
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handled = B_INVOKE_SCHEDULER;
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}
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}
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if( (int_status & RADEON_CRTC2_VBLANK_STAT) != 0 &&
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si->crtc[1].vblank >= 0 )
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{
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if ((int_status & RADEON_CRTC2_VBLANK_STAT) != 0
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&& si->crtc[1].vblank >= 0) {
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int32 blocked;
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++di->vbi_count[1];
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++di->vbi_count[1];
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if( (get_sem_count( si->crtc[1].vblank, &blocked ) == B_OK) && (blocked < 0) ) {
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release_sem_etc( si->crtc[1].vblank, -blocked, B_DO_NOT_RESCHEDULE );
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if (get_sem_count(si->crtc[1].vblank, &blocked) == B_OK && blocked < 0) {
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release_sem_etc(si->crtc[1].vblank, -blocked, B_DO_NOT_RESCHEDULE);
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handled = B_INVOKE_SCHEDULER;
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}
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}
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if( (int_status & RADEON_VIDDMA_STAT ) != 0 ) {
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release_sem_etc( di->dma_sem, 1, B_DO_NOT_RESCHEDULE );
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if ((int_status & RADEON_VIDDMA_STAT) != 0) {
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release_sem_etc(di->dma_sem, 1, B_DO_NOT_RESCHEDULE);
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handled = B_INVOKE_SCHEDULER;
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}
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return handled;
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}
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// Capture interrupt handler
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#if 0
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/** Capture interrupt handler */
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static int32
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Radeon_HandleCaptureInterrupt( vuint8 *regs, device_info *di, uint32 cap_status )
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Radeon_HandleCaptureInterrupt(vuint8 *regs, device_info *di, uint32 cap_status)
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{
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int32 blocked;
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uint32 handled = B_HANDLED_INTERRUPT;
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cpu_status prev_irq_state = disable_interrupts();
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acquire_spinlock( &di->cap_spinlock );
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acquire_spinlock(&di->cap_spinlock);
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++di->cap_counter;
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di->cap_int_status = cap_status;
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di->cap_timestamp = system_time();
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release_spinlock( &di->cap_spinlock );
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restore_interrupts( prev_irq_state );
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release_spinlock(&di->cap_spinlock);
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restore_interrupts(prev_irq_state);
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// don't release if semaphore count is positive, i.e. notifications are piling up
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if( (get_sem_count( di->cap_sem, &blocked ) == B_OK) && (blocked <= 0) ) {
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release_sem_etc( di->cap_sem, 1, B_DO_NOT_RESCHEDULE );
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if (get_sem_count(di->cap_sem, &blocked) == B_OK && blocked <= 0) {
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release_sem_etc(di->cap_sem, 1, B_DO_NOT_RESCHEDULE);
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handled = B_INVOKE_SCHEDULER;
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}
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// acknowledge IRQ
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OUTREG( regs, RADEON_CAP_INT_STATUS, cap_status );
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OUTREG(regs, RADEON_CAP_INT_STATUS, cap_status);
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return handled;
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}
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// Main interrupt handler
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/** Main interrupt handler */
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static int32
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Radeon_Interrupt(void *data)
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{
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@ -105,43 +111,46 @@ Radeon_Interrupt(void *data)
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int32 full_int_status, int_status;
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// read possible IRQ reasons, ignoring any masked IRQs
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full_int_status = INREG( regs, RADEON_GEN_INT_STATUS );
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int_status = full_int_status & INREG( regs, RADEON_GEN_INT_CNTL );
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full_int_status = INREG(regs, RADEON_GEN_INT_STATUS);
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int_status = full_int_status & INREG(regs, RADEON_GEN_INT_CNTL);
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if( int_status != 0 ) {
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if (int_status != 0) {
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++di->interrupt_count;
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handled = Radeon_ThreadInterruptWork( regs, di, int_status );
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handled = Radeon_ThreadInterruptWork(regs, di, int_status);
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// acknowledge IRQ
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OUTREG( regs, RADEON_GEN_INT_STATUS, int_status );
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OUTREG(regs, RADEON_GEN_INT_STATUS, int_status);
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}
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// capture interrupt have no mask in GEN_INT_CNTL register;
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// probably, ATI wanted to make capture interrupt control independant of main control
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if( (full_int_status & RADEON_CAP0_INT_ACTIVE) != 0 ) {
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if ((full_int_status & RADEON_CAP0_INT_ACTIVE) != 0) {
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int32 cap_status;
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// same as before: only regard enabled IRQ reasons
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cap_status = INREG( regs, RADEON_CAP_INT_STATUS );
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cap_status &= INREG( regs, RADEON_CAP_INT_CNTL );
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if( cap_status != 0 ) {
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// same as before: only regard enabled IRQ reasons
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cap_status = INREG(regs, RADEON_CAP_INT_STATUS);
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cap_status &= INREG(regs, RADEON_CAP_INT_CNTL);
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if (cap_status != 0) {
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int32 cap_handled;
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cap_handled = Radeon_HandleCaptureInterrupt( regs, di, cap_status );
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if( cap_handled == B_INVOKE_SCHEDULER || handled == B_INVOKE_SCHEDULER )
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cap_handled = Radeon_HandleCaptureInterrupt(regs, di, cap_status);
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if (cap_handled == B_INVOKE_SCHEDULER || handled == B_INVOKE_SCHEDULER)
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handled = B_INVOKE_SCHEDULER;
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else if( cap_handled == B_HANDLED_INTERRUPT )
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else if (cap_handled == B_HANDLED_INTERRUPT)
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handled = B_HANDLED_INTERRUPT;
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}
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}
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return handled;
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return handled;
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}
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#endif
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static int32 timer_interrupt_func( timer *te )
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static int32
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timer_interrupt_func(timer *te)
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{
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bigtime_t now = system_time();
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/* get the pointer to the device we're handling this time */
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@ -152,30 +161,35 @@ static int32 timer_interrupt_func( timer *te )
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int32 result = B_HANDLED_INTERRUPT;
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/* are we suppoesed to handle interrupts still? */
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if( !di->shutdown_virtual_irq ) {
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if (!di->shutdown_virtual_irq) {
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/* reschedule with same period by default */
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bigtime_t when = si->refresh_period;
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timer *to;
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/* if interrupts are "enabled", do our thing */
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if( si->enable_virtual_irq ) {
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if (si->enable_virtual_irq) {
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/* insert code to sync to interrupts here */
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if (!vbl_status) {
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when -= si->blank_period - 4;
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}
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/* do the things we do when we notice a vertical retrace */
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result = Radeon_ThreadInterruptWork( regs, di,
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RADEON_CRTC_VBLANK_STAT |
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(di->num_crtc > 1 ? RADEON_CRTC2_VBLANK_STAT : 0 ));
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result = Radeon_ThreadInterruptWork(regs, di,
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RADEON_CRTC_VBLANK_STAT
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| (di->num_crtc > 1 ? RADEON_CRTC2_VBLANK_STAT : 0));
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}
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/* pick the "other" timer */
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to = (timer *)&(di->ti_a);
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if (to == te) to = (timer *)&(di->ti_b);
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to = (timer *)&di->ti_a;
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if (to == te)
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to = (timer *)&di->ti_b;
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/* our guess as to when we should be back */
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((timer_info *)to)->when_target = now + when;
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/* reschedule the interrupt */
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add_timer(to, timer_interrupt_func, ((timer_info *)to)->when_target, B_ONE_SHOT_ABSOLUTE_TIMER);
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add_timer(to, timer_interrupt_func, ((timer_info *)to)->when_target,
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B_ONE_SHOT_ABSOLUTE_TIMER);
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/* remember the currently active timer */
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di->current_timer = (timer_info *)to;
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}
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@ -184,142 +198,150 @@ static int32 timer_interrupt_func( timer *te )
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}
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// setup IRQ handlers.
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// includes an VBI emulator via a timer (according to sample code),
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// though this makes sense for one CRTC only
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/** Setup IRQ handlers.
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* Includes an VBI emulator via a timer (according to sample code),
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* though this makes sense for one CRTC only.
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*/
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status_t
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Radeon_SetupIRQ( device_info *di, char *buffer )
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Radeon_SetupIRQ(device_info *di, char *buffer)
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{
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shared_info *si = di->si;
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status_t result;
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thread_id thid;
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thread_info thinfo;
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sprintf( buffer, "%04X_%04X_%02X%02X%02X VBI 1",
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sprintf(buffer, "%04X_%04X_%02X%02X%02X VBI 1",
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di->pcii.vendor_id, di->pcii.device_id,
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di->pcii.bus, di->pcii.device, di->pcii.function );
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si->crtc[0].vblank = create_sem( 0, buffer );
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if( si->crtc[0].vblank < 0 ) {
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di->pcii.bus, di->pcii.device, di->pcii.function);
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si->crtc[0].vblank = create_sem(0, buffer);
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if (si->crtc[0].vblank < 0) {
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result = si->crtc[0].vblank;
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goto err1;
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}
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si->crtc[1].vblank = 0;
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if( di->num_crtc > 1 ) {
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sprintf( buffer, "%04X_%04X_%02X%02X%02X VBI 2",
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if (di->num_crtc > 1) {
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sprintf(buffer, "%04X_%04X_%02X%02X%02X VBI 2",
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di->pcii.vendor_id, di->pcii.device_id,
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di->pcii.bus, di->pcii.device, di->pcii.function );
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si->crtc[1].vblank = create_sem( 0, buffer );
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if( si->crtc[1].vblank < 0 ) {
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di->pcii.bus, di->pcii.device, di->pcii.function);
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si->crtc[1].vblank = create_sem(0, buffer);
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if (si->crtc[1].vblank < 0) {
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result = si->crtc[1].vblank;
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goto err2;
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}
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}
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sprintf( buffer, "%04X_%04X_%02X%02X%02X Cap I",
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sprintf(buffer, "%04X_%04X_%02X%02X%02X Cap I",
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di->pcii.vendor_id, di->pcii.device_id,
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di->pcii.bus, di->pcii.device, di->pcii.function );
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di->cap_sem = create_sem( 0, buffer );
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if( di->cap_sem < 0 ) {
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di->pcii.bus, di->pcii.device, di->pcii.function);
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di->cap_sem = create_sem(0, buffer);
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if (di->cap_sem < 0) {
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result = di->cap_sem;
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goto err3;
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}
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di->cap_spinlock = 0;
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sprintf( buffer, "%04X_%04X_%02X%02X%02X DMA I",
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sprintf(buffer, "%04X_%04X_%02X%02X%02X DMA I",
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di->pcii.vendor_id, di->pcii.device_id,
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di->pcii.bus, di->pcii.device, di->pcii.function );
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di->dma_sem = create_sem( 0, buffer );
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if( di->dma_sem < 0 ) {
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di->pcii.bus, di->pcii.device, di->pcii.function);
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di->dma_sem = create_sem(0, buffer);
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if (di->dma_sem < 0) {
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result = di->dma_sem;
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goto err4;
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}
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/* change the owner of the semaphores to the opener's team */
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/* this is required because apps can't aquire kernel semaphores */
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thid = find_thread(NULL);
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/* change the owner of the semaphores to the opener's team */
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/* this is required because apps can't aquire kernel semaphores */
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thid = find_thread(NULL);
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get_thread_info(thid, &thinfo);
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set_sem_owner(si->crtc[0].vblank, thinfo.team);
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if( di->num_crtc > 1 )
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if (di->num_crtc > 1)
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set_sem_owner(si->crtc[1].vblank, thinfo.team);
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//set_sem_owner(di->cap_sem, thinfo.team);
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/* disable all interrupts */
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Radeon_DisableIRQ( di );
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/* disable all interrupts */
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Radeon_DisableIRQ(di);
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|
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/* if we're faking interrupts */
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if ((di->pcii.u.h0.interrupt_pin == 0x00) || (di->pcii.u.h0.interrupt_line == 0xff)){
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/* if we're faking interrupts */
|
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if (di->pcii.u.h0.interrupt_pin == 0x00 || di->pcii.u.h0.interrupt_line == 0xff) {
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SHOW_INFO0( 3, "We like to fake IRQ" );
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/* fake some kind of interrupt with a timer */
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di->shutdown_virtual_irq = false;
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si->refresh_period = 16666; /* fake 60Hz to start */
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si->blank_period = si->refresh_period / 20;
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/* fake some kind of interrupt with a timer */
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di->shutdown_virtual_irq = false;
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si->refresh_period = 16666; /* fake 60Hz to start */
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si->blank_period = si->refresh_period / 20;
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di->ti_a.di = di; /* refer to ourself */
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di->ti_b.di = di;
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di->current_timer = &(di->ti_a);
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di->ti_a.di = di; /* refer to ourself */
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di->ti_b.di = di;
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di->current_timer = &di->ti_a;
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|
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/* program the first timer interrupt, and it will handle the rest */
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result = add_timer((timer *)(di->current_timer), timer_interrupt_func,
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si->refresh_period, B_ONE_SHOT_RELATIVE_TIMER);
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if( result != B_OK )
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goto err5;
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} else {
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/* otherwise install our interrupt handler */
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result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line,
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Radeon_Interrupt, (void *)di, 0);
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if( result != B_OK )
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goto err5;
|
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/* program the first timer interrupt, and it will handle the rest */
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result = add_timer((timer *)(di->current_timer), timer_interrupt_func,
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si->refresh_period, B_ONE_SHOT_RELATIVE_TIMER);
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if (result != B_OK)
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goto err5;
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} else {
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/* otherwise install our interrupt handler */
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dprintf("radeon: real interrupt handling disabled\n");
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#if 0
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result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line,
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Radeon_Interrupt, (void *)di, 0);
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if (result != B_OK)
|
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goto err5;
|
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|
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SHOW_INFO( 3, "installed IRQ @ %d", di->pcii.u.h0.interrupt_line );
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}
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return B_OK;
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SHOW_INFO(3, "installed IRQ @ %d", di->pcii.u.h0.interrupt_line);
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#endif
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}
|
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return B_OK;
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err5:
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delete_sem( di->dma_sem );
|
||||
delete_sem(di->dma_sem);
|
||||
err4:
|
||||
delete_sem( di->cap_sem );
|
||||
delete_sem(di->cap_sem);
|
||||
err3:
|
||||
if( di->num_crtc > 1 )
|
||||
delete_sem( si->crtc[1].vblank );
|
||||
if (di->num_crtc > 1)
|
||||
delete_sem(si->crtc[1].vblank);
|
||||
err2:
|
||||
delete_sem( si->crtc[0].vblank );
|
||||
delete_sem(si->crtc[0].vblank);
|
||||
err1:
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
// clean-up interrupt handling
|
||||
/** Clean-up interrupt handling */
|
||||
|
||||
void
|
||||
Radeon_CleanupIRQ( device_info *di )
|
||||
Radeon_CleanupIRQ(device_info *di)
|
||||
{
|
||||
shared_info *si = di->si;
|
||||
|
||||
Radeon_DisableIRQ( di );
|
||||
|
||||
/* if we were faking the interrupts */
|
||||
if ((di->pcii.u.h0.interrupt_pin == 0x00) || (di->pcii.u.h0.interrupt_line == 0xff)){
|
||||
/* stop our interrupt faking thread */
|
||||
di->shutdown_virtual_irq = true;
|
||||
/* cancel the timer */
|
||||
/* we don't know which one is current, so cancel them both and ignore any error */
|
||||
cancel_timer((timer *)&(di->ti_a));
|
||||
cancel_timer((timer *)&(di->ti_b));
|
||||
} else {
|
||||
/* remove interrupt handler */
|
||||
remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, Radeon_Interrupt, di);
|
||||
}
|
||||
|
||||
delete_sem( si->crtc[0].vblank );
|
||||
|
||||
if( di->num_crtc > 1 )
|
||||
delete_sem( si->crtc[1].vblank );
|
||||
|
||||
delete_sem( di->cap_sem );
|
||||
delete_sem( di->dma_sem );
|
||||
Radeon_DisableIRQ(di);
|
||||
|
||||
#if 0
|
||||
/* if we were faking the interrupts */
|
||||
if ((di->pcii.u.h0.interrupt_pin == 0x00) || (di->pcii.u.h0.interrupt_line == 0xff)){
|
||||
/* stop our interrupt faking thread */
|
||||
di->shutdown_virtual_irq = true;
|
||||
/* cancel the timer */
|
||||
/* we don't know which one is current, so cancel them both and ignore any error */
|
||||
cancel_timer((timer *)&(di->ti_a));
|
||||
cancel_timer((timer *)&(di->ti_b));
|
||||
} else {
|
||||
/* remove interrupt handler */
|
||||
remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, Radeon_Interrupt, di);
|
||||
}
|
||||
#endif
|
||||
|
||||
delete_sem(si->crtc[0].vblank);
|
||||
|
||||
if (di->num_crtc > 1)
|
||||
delete_sem(si->crtc[1].vblank);
|
||||
|
||||
delete_sem(di->cap_sem);
|
||||
delete_sem(di->dma_sem);
|
||||
|
||||
di->cap_sem = si->crtc[1].vblank = si->crtc[0].vblank = 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue