* Shuffled the functions a bit around to separate private from public functions.
* Renamed some functions, added comments. * Minor cleanup. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@24182 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
c607395208
commit
abf12dd83f
@ -58,7 +58,254 @@ next_corb(hda_controller *controller)
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}
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// #pragma mark -
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//! Called with interrupts off
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static void
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stream_handle_interrupt(hda_controller* controller, hda_stream* stream)
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{
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uint8 status;
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if (!stream->running)
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return;
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status = OREG8(controller, stream->off, STS);
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if (status == 0)
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return;
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OREG8(controller, stream->off, STS) = status;
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if ((status & STS_BCIS) != 0) {
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// Buffer Completed Interrupt
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acquire_spinlock(&stream->lock);
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stream->real_time = system_time();
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stream->frames_count += stream->buffer_length;
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stream->buffer_cycle = (stream->buffer_cycle + 1)
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% stream->num_buffers;
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release_spinlock(&stream->lock);
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release_sem_etc(stream->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE);
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} else
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dprintf("HDA: stream status %x\n", status);
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}
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static int32
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hda_interrupt_handler(hda_controller* controller)
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{
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int32 rc = B_HANDLED_INTERRUPT;
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/* Check if this interrupt is ours */
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uint32 intsts = REG32(controller, INTSTS);
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if ((intsts & INTSTS_GIS) == 0)
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return B_UNHANDLED_INTERRUPT;
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/* Controller or stream related? */
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if (intsts & INTSTS_CIS) {
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uint32 stateStatus = REG16(controller, STATESTS);
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uint8 rirbStatus = REG8(controller, RIRBSTS);
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uint8 corbStatus = REG8(controller, CORBSTS);
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if (stateStatus) {
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/* Detected Codec state change */
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REG16(controller, STATESTS) = stateStatus;
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controller->codec_status = stateStatus;
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}
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/* Check for incoming responses */
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if (rirbStatus) {
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REG8(controller, RIRBSTS) = rirbStatus;
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if (rirbStatus & RIRBSTS_RINTFL) {
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uint16 writePos = (REG16(controller, RIRBWP) + 1)
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% controller->rirb_length;
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for (; controller->rirb_read_pos != writePos;
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controller->rirb_read_pos = next_rirb(controller)) {
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uint32 response = current_rirb(controller).response;
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uint32 responseFlags = current_rirb(controller).flags;
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uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK;
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hda_codec* codec = controller->codecs[cad];
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if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) {
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dprintf("hda: Unsolicited response: %08lx/%08lx\n",
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response, responseFlags);
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continue;
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}
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if (codec == NULL) {
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dprintf("hda: Response for unknown codec %ld: "
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"%08lx/%08lx\n", cad, response, responseFlags);
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continue;
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}
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if (codec->response_count >= MAX_CODEC_RESPONSES) {
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dprintf("hda: too many responses received for codec %ld"
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": %08lx/%08lx!\n", cad, response, responseFlags);
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continue;
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}
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/* Store response in codec */
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codec->responses[codec->response_count++] = response;
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release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE);
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rc = B_INVOKE_SCHEDULER;
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}
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}
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if (rirbStatus & RIRBSTS_OIS)
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dprintf("hda: RIRB Overflow\n");
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}
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/* Check for sending errors */
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if (corbStatus) {
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REG8(controller, CORBSTS) = corbStatus;
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if (corbStatus & CORBSTS_MEI)
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dprintf("hda: CORB Memory Error!\n");
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}
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}
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if (intsts & ~(INTSTS_CIS | INTSTS_GIS)) {
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for (uint32 index = 0; index < HDA_MAX_STREAMS; index++) {
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if ((intsts & (1 << index)) != 0) {
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if (controller->streams[index]) {
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stream_handle_interrupt(controller,
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controller->streams[index]);
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} else {
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dprintf("hda: Stream interrupt for unconfigured stream "
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"%d!\n", index);
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}
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}
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}
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}
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/* NOTE: See HDA001 => CIS/GIS cannot be cleared! */
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return rc;
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}
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static status_t
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hda_hw_start(hda_controller* controller)
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{
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int timeout = 10;
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// TODO: reset controller first? (we currently reset on uninit only)
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/* Put controller out of reset mode */
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REG32(controller, GCTL) |= GCTL_CRST;
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do {
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snooze(100);
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} while (--timeout && !(REG32(controller, GCTL) & GCTL_CRST));
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return timeout ? B_OK : B_TIMED_OUT;
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}
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/*! Allocates and initializes the Command Output Ring Buffer (CORB), and
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Response Input Ring Buffer (RIRB) to the maximum supported size, and also
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the DMA position buffer.
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Programs the controller hardware to make use of these buffers (the DMA
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positioning is actually enabled in hda_stream_setup_buffers()).
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*/
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static status_t
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init_corb_rirb_pos(hda_controller* controller)
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{
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uint32 memSize, rirbOffset, posOffset;
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uint8 corbSize, rirbSize, posSize;
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status_t rc = B_OK;
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physical_entry pe;
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/* Determine and set size of CORB */
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corbSize = REG8(controller, CORBSIZE);
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if (corbSize & CORBSIZE_CAP_256E) {
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controller->corb_length = 256;
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REG8(controller, CORBSIZE) = CORBSIZE_SZ_256E;
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} else if (corbSize & CORBSIZE_CAP_16E) {
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controller->corb_length = 16;
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REG8(controller, CORBSIZE) = CORBSIZE_SZ_16E;
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} else if (corbSize & CORBSIZE_CAP_2E) {
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controller->corb_length = 2;
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REG8(controller, CORBSIZE) = CORBSIZE_SZ_2E;
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}
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/* Determine and set size of RIRB */
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rirbSize = REG8(controller, RIRBSIZE);
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if (rirbSize & RIRBSIZE_CAP_256E) {
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controller->rirb_length = 256;
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REG8(controller, RIRBSIZE) = RIRBSIZE_SZ_256E;
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} else if (rirbSize & RIRBSIZE_CAP_16E) {
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controller->rirb_length = 16;
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REG8(controller, RIRBSIZE) = RIRBSIZE_SZ_16E;
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} else if (rirbSize & RIRBSIZE_CAP_2E) {
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controller->rirb_length = 2;
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REG8(controller, RIRBSIZE) = RIRBSIZE_SZ_2E;
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}
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/* Determine rirb offset in memory and total size of corb+alignment+rirb */
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rirbOffset = (controller->corb_length * sizeof(corb_t) + 0x7f) & ~0x7f;
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posOffset = (rirbOffset + controller->rirb_length * sizeof(rirb_t) + 0x7f)
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& 0x7f;
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posSize = 8 * (controller->num_input_streams
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+ controller->num_output_streams + controller->num_bidir_streams);
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memSize = (posOffset + posSize + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
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/* Allocate memory area */
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controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos",
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(void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize,
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B_CONTIGUOUS, 0);
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if (controller->corb_rirb_pos_area < 0)
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return controller->corb_rirb_pos_area;
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/* Rirb is after corb+aligment */
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controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset);
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if ((rc = get_memory_map(controller->corb, memSize, &pe, 1)) != B_OK) {
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delete_area(controller->corb_rirb_pos_area);
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return rc;
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}
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/* Program CORB/RIRB for these locations */
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REG32(controller, CORBLBASE) = (uint32)pe.address;
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REG32(controller, CORBUBASE) = 0;
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REG32(controller, RIRBLBASE) = (uint32)pe.address + rirbOffset;
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REG32(controller, RIRBUBASE) = 0;
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/* Program DMA position update */
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REG32(controller, DMA_POSITION_BASE_LOWER) = (uint32)pe.address + posOffset;
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REG32(controller, DMA_POSITION_BASE_UPPER) = 0;
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controller->stream_positions = (uint32*)
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((uint8*)controller->corb + posOffset);
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/* Reset CORB read pointer */
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/* NOTE: See HDA011 for corrected procedure! */
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REG16(controller, CORBRP) = CORBRP_RST;
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do {
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spin(10);
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} while ( !(REG16(controller, CORBRP) & CORBRP_RST) );
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REG16(controller, CORBRP) = 0;
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/* Reset RIRB write pointer */
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REG16(controller, RIRBWP) = RIRBWP_RST;
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/* Generate interrupt for every response */
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REG16(controller, RINTCNT) = 1;
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/* Setup cached read/write indices */
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controller->rirb_read_pos = 1;
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controller->corb_write_pos = 0;
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/* Gentlemen, start your engines... */
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REG8(controller, CORBCTL) = CORBCTL_RUN | CORBCTL_MEIE;
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REG8(controller, RIRBCTL) = RIRBCTL_DMAEN | RIRBCTL_OIC | RIRBCTL_RINTCTL;
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return B_OK;
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}
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// #pragma mark - public stream functions
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void
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@ -113,6 +360,9 @@ hda_stream_new(hda_controller* controller, int type)
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}
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/*! Starts a stream's DMA engine, and enables generating and receiving
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interrupts for this stream.
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*/
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status_t
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hda_stream_start(hda_controller* controller, hda_stream* stream)
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{
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@ -136,38 +386,9 @@ hda_stream_start(hda_controller* controller, hda_stream* stream)
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}
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//! Called with interrupts off
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static void
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hda_stream_check_intr(hda_controller* controller, hda_stream* stream)
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{
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uint8 status;
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if (!stream->running)
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return;
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status = OREG8(controller, stream->off, STS);
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if (status == 0)
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return;
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OREG8(controller, stream->off, STS) = status;
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if ((status & STS_BCIS) != 0) {
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// Buffer Completed Interrupt
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acquire_spinlock(&stream->lock);
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stream->real_time = system_time();
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stream->frames_count += stream->buffer_length;
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stream->buffer_cycle = (stream->buffer_cycle + 1)
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% stream->num_buffers;
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release_spinlock(&stream->lock);
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release_sem_etc(stream->buffer_ready_sem, 1, B_DO_NOT_RESCHEDULE);
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} else
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dprintf("HDA: stream status %x\n", status);
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}
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/*! Stops the stream's DMA engine, and turns off interrupts for this
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stream.
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*/
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status_t
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hda_stream_stop(hda_controller* controller, hda_stream* stream)
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{
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@ -330,7 +551,7 @@ dprintf("HDA: sample size %ld, num channels %ld, buffer length %ld *************
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}
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// #pragma mark -
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// #pragma mark - public controller functions
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status_t
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@ -374,215 +595,6 @@ hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses, uint32 count)
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}
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static int32
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hda_interrupt_handler(hda_controller* controller)
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{
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int32 rc = B_HANDLED_INTERRUPT;
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/* Check if this interrupt is ours */
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uint32 intsts = REG32(controller, INTSTS);
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if ((intsts & INTSTS_GIS) == 0)
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return B_UNHANDLED_INTERRUPT;
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/* Controller or stream related? */
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if (intsts & INTSTS_CIS) {
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uint32 stateStatus = REG16(controller, STATESTS);
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uint8 rirbStatus = REG8(controller, RIRBSTS);
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uint8 corbStatus = REG8(controller, CORBSTS);
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if (stateStatus) {
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/* Detected Codec state change */
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REG16(controller, STATESTS) = stateStatus;
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controller->codec_status = stateStatus;
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}
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/* Check for incoming responses */
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if (rirbStatus) {
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REG8(controller, RIRBSTS) = rirbStatus;
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if (rirbStatus & RIRBSTS_RINTFL) {
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uint16 writePos = (REG16(controller, RIRBWP) + 1)
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% controller->rirb_length;
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for (; controller->rirb_read_pos != writePos;
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controller->rirb_read_pos = next_rirb(controller)) {
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uint32 response = current_rirb(controller).response;
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uint32 responseFlags = current_rirb(controller).flags;
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uint32 cad = responseFlags & RESPONSE_FLAGS_CODEC_MASK;
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hda_codec* codec = controller->codecs[cad];
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if ((responseFlags & RESPONSE_FLAGS_UNSOLICITED) != 0) {
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dprintf("hda: Unsolicited response: %08lx/%08lx\n",
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response, responseFlags);
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continue;
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}
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if (codec == NULL) {
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dprintf("hda: Response for unknown codec %ld: "
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"%08lx/%08lx\n", cad, response, responseFlags);
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continue;
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}
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if (codec->response_count >= MAX_CODEC_RESPONSES) {
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dprintf("hda: too many responses received for codec %ld"
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": %08lx/%08lx!\n", cad, response, responseFlags);
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continue;
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}
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/* Store response in codec */
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codec->responses[codec->response_count++] = response;
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release_sem_etc(codec->response_sem, 1, B_DO_NOT_RESCHEDULE);
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rc = B_INVOKE_SCHEDULER;
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}
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}
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if (rirbStatus & RIRBSTS_OIS)
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dprintf("%s: RIRB Overflow\n", __func__);
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}
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/* Check for sending errors */
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if (corbStatus) {
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REG8(controller, CORBSTS) = corbStatus;
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if (corbStatus & CORBSTS_MEI)
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dprintf("%s: CORB Memory Error!\n", __func__);
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}
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}
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if (intsts & ~(INTSTS_CIS | INTSTS_GIS)) {
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int index;
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for (index = 0; index < HDA_MAX_STREAMS; index++) {
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if ((intsts & (1 << index)) != 0) {
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if (controller->streams[index])
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hda_stream_check_intr(controller, controller->streams[index]);
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else {
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dprintf("%s: Stream interrupt for unconfigured stream "
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"%d!\n", __func__, index);
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}
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}
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}
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}
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/* NOTE: See HDA001 => CIS/GIS cannot be cleared! */
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return rc;
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}
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static status_t
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hda_hw_start(hda_controller* controller)
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{
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int timeout = 10;
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/* Put controller out of reset mode */
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REG32(controller, GCTL) |= GCTL_CRST;
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do {
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snooze(100);
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} while (--timeout && !(REG32(controller, GCTL) & GCTL_CRST));
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return timeout ? B_OK : B_TIMED_OUT;
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}
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static status_t
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hda_hw_corb_rirb_pos_init(hda_controller* controller)
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{
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uint32 memSize, rirbOffset, posOffset;
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uint8 corbSize, rirbSize, posSize;
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status_t rc = B_OK;
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physical_entry pe;
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/* Determine and set size of CORB */
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corbSize = REG8(controller, CORBSIZE);
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if (corbSize & CORBSIZE_CAP_256E) {
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controller->corb_length = 256;
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REG8(controller, CORBSIZE) = CORBSIZE_SZ_256E;
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} else if (corbSize & CORBSIZE_CAP_16E) {
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controller->corb_length = 16;
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REG8(controller, CORBSIZE) = CORBSIZE_SZ_16E;
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} else if (corbSize & CORBSIZE_CAP_2E) {
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controller->corb_length = 2;
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REG8(controller, CORBSIZE) = CORBSIZE_SZ_2E;
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}
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/* Determine and set size of RIRB */
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rirbSize = REG8(controller, RIRBSIZE);
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if (rirbSize & RIRBSIZE_CAP_256E) {
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controller->rirb_length = 256;
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REG8(controller, RIRBSIZE) = RIRBSIZE_SZ_256E;
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} else if (rirbSize & RIRBSIZE_CAP_16E) {
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controller->rirb_length = 16;
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REG8(controller, RIRBSIZE) = RIRBSIZE_SZ_16E;
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} else if (rirbSize & RIRBSIZE_CAP_2E) {
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controller->rirb_length = 2;
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REG8(controller, RIRBSIZE) = RIRBSIZE_SZ_2E;
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}
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/* Determine rirb offset in memory and total size of corb+alignment+rirb */
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rirbOffset = (controller->corb_length * sizeof(corb_t) + 0x7f) & ~0x7f;
|
||||
posOffset = (rirbOffset + controller->rirb_length * sizeof(rirb_t) + 0x7f)
|
||||
& 0x7f;
|
||||
posSize = 8 * (controller->num_input_streams
|
||||
+ controller->num_output_streams + controller->num_bidir_streams);
|
||||
|
||||
memSize = (posOffset + posSize + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
|
||||
|
||||
/* Allocate memory area */
|
||||
controller->corb_rirb_pos_area = create_area("hda corb/rirb/pos",
|
||||
(void**)&controller->corb, B_ANY_KERNEL_ADDRESS, memSize,
|
||||
B_CONTIGUOUS, 0);
|
||||
if (controller->corb_rirb_pos_area < 0)
|
||||
return controller->corb_rirb_pos_area;
|
||||
|
||||
/* Rirb is after corb+aligment */
|
||||
controller->rirb = (rirb_t*)(((uint8*)controller->corb) + rirbOffset);
|
||||
|
||||
if ((rc = get_memory_map(controller->corb, memSize, &pe, 1)) != B_OK) {
|
||||
delete_area(controller->corb_rirb_pos_area);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Program CORB/RIRB for these locations */
|
||||
REG32(controller, CORBLBASE) = (uint32)pe.address;
|
||||
REG32(controller, CORBUBASE) = 0;
|
||||
REG32(controller, RIRBLBASE) = (uint32)pe.address + rirbOffset;
|
||||
REG32(controller, RIRBUBASE) = 0;
|
||||
|
||||
/* Program DMA position update */
|
||||
REG32(controller, DMA_POSITION_BASE_LOWER) = (uint32)pe.address + posOffset;
|
||||
REG32(controller, DMA_POSITION_BASE_UPPER) = 0;
|
||||
|
||||
controller->stream_positions = (uint32*)
|
||||
((uint8*)controller->corb + posOffset);
|
||||
|
||||
/* Reset CORB read pointer */
|
||||
/* NOTE: See HDA011 for corrected procedure! */
|
||||
REG16(controller, CORBRP) = CORBRP_RST;
|
||||
do {
|
||||
spin(10);
|
||||
} while ( !(REG16(controller, CORBRP) & CORBRP_RST) );
|
||||
REG16(controller, CORBRP) = 0;
|
||||
|
||||
/* Reset RIRB write pointer */
|
||||
REG16(controller, RIRBWP) = RIRBWP_RST;
|
||||
|
||||
/* Generate interrupt for every response */
|
||||
REG16(controller, RINTCNT) = 1;
|
||||
|
||||
/* Setup cached read/write indices */
|
||||
controller->rirb_read_pos = 1;
|
||||
controller->corb_write_pos = 0;
|
||||
|
||||
/* Gentlemen, start your engines... */
|
||||
REG8(controller, CORBCTL) = CORBCTL_RUN | CORBCTL_MEIE;
|
||||
REG8(controller, RIRBCTL) = RIRBCTL_DMAEN | RIRBCTL_OIC | RIRBCTL_RINTCTL;
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
// #pragma mark -
|
||||
|
||||
|
||||
/*! Setup hardware for use; detect codecs; etc */
|
||||
status_t
|
||||
hda_hw_init(hda_controller* controller)
|
||||
@ -626,7 +638,7 @@ hda_hw_init(hda_controller* controller)
|
||||
goto reset_failed;
|
||||
|
||||
/* Setup CORB/RIRB/DMA POS */
|
||||
rc = hda_hw_corb_rirb_pos_init(controller);
|
||||
rc = init_corb_rirb_pos(controller);
|
||||
if (rc != B_OK)
|
||||
goto corb_rirb_failed;
|
||||
|
||||
@ -714,7 +726,7 @@ hda_hw_uninit(hda_controller* controller)
|
||||
REG32(controller, RIRBLBASE) = 0;
|
||||
REG32(controller, DMA_POSITION_BASE_LOWER) = 0;
|
||||
|
||||
/* Disable interrupts and remove interrupt handler */
|
||||
/* Disable interrupts, reset controller, and remove interrupt handler */
|
||||
REG32(controller, INTCTL) = 0;
|
||||
REG32(controller, GCTL) &= ~GCTL_CRST;
|
||||
remove_io_interrupt_handler(controller->irq,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user