* Added buslogic SCSI driver

* Added 54c8xx SCSI driver

Both drivers originated from the BeOS sample code.



git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@18018 a95241bf-73f2-0310-859d-f6bbb57e9c96

src/add-ons/kernel/busses/scsi/53c8xx/53c8xx.h

@@ -0,0 +1,389 @@
+/*
+	Copyright 1999, Be Incorporated.   All Rights Reserved.
+	This file may be used under the terms of the Be Sample Code License.
+*/
+
+#ifndef _SYM53C8XX_H
+#define _SYM53C8XX_H
+
+/*======================================================================*/
+/* operating registers definitions */
+
+#define sym_scntl0	0x00	/* scsi control 0 */
+#define sym_scntl1	0x01	/* scsi control 1 */
+#define sym_scntl2	0x02	/* scsi control 2 */
+#define sym_scntl3	0x03	/* scsi control 3 */
+#define sym_scid	0x04	/* scsi chip ID */
+#define sym_sxfer	0x05	/* scsi transfer */
+#define sym_sdid	0x06	/* scsi destination ID */
+#define sym_gpreg	0x07	/* general purpose bits */
+#define sym_sfbr	0x08	/* scsi first byte received */
+#define sym_socl	0x09	/* scsi output control latch */
+#define sym_ssid	0x0a	/* scsi selector ID */
+#define sym_sbcl	0x0b	/* scsi bus control lines */
+#define sym_dstat	0x0c	/* dma status */
+#define sym_sstat0	0x0d	/* scsi status 0 */
+#define sym_sstat1	0x0e	/* scsi status 1 */
+#define sym_sstat2	0x0f	/* scsi status 2 */
+#define	sym_dsa		0x10	/* data structure address [4 bytes] */
+#define	sym_istat	0x14	/* interrupt status */
+#define sym_ctest0	0x18	/* chip test 0 */
+#define sym_ctest1	0x19	/* chip test 1 */
+#define sym_ctest2	0x1a	/* chip test 2 */
+#define sym_ctest3	0x1b	/* chip test 3 */
+#define sym_temp	0x1c	/* temporary stack [4 bytes] */
+#define sym_dfifo	0x20	/* dma fifo */
+#define sym_ctest4	0x21	/* chip test 4 */
+#define sym_ctest5	0x22	/* chip test 5 */
+#define sym_ctest6	0x23	/* chip test 6 */
+#define sym_dbc		0x24	/* dma byte counter [3 bytes] */
+#define sym_dcmd	0x27	/* dma command */
+#define sym_dnad	0x28	/* dma next address for data [4 bytes] */
+#define sym_dsp		0x2c	/* dma scripts pointer [4 bytes] */
+#define sym_dsps	0x30	/* dma scripts pointer save [4 bytes] */
+#define sym_scratcha 0x34	/* general purpose scratch pad a [4 bytes] */
+#define sym_dmode	0x38	/* dma mode */
+#define sym_dien	0x39	/* dma interrupt enable */
+#define sym_dwt		0x3a	/* dma watchdog timer */
+#define sym_dcntl	0x3b	/* dma control */
+#define sym_adder	0x3c	/* sum output of internal adder [4 bytes] */
+#define sym_sien0	0x40	/* scsi interrupt enable 0 */
+#define sym_sien1	0x41	/* scsi interrupt enable 1 */
+#define sym_sist0	0x42	/* scsi interrupt status 0 */
+#define sym_sist1	0x43	/* scsi interrupt status 1 */
+#define sym_slpar	0x44	/* scsi longitudinal parity */
+#define sym_macntl	0x46	/* memory access control */
+#define sym_gpcntl	0x47	/* general purpose control */
+#define sym_stime0	0x48	/* scsi timer 0 */
+#define sym_stime1	0x49	/* scsi timer 1 */
+#define sym_respid	0x4a	/* responce ID */
+#define sym_stest0	0x4c	/* scsi test 0 */
+#define sym_stest1	0x4d	/* scsi test 1 */
+#define sym_stest2	0x4e	/* scsi test 2 */
+#define sym_stest3	0x4f	/* scsi test 3 */
+#define sym_sidl	0x50	/* scsi input data latch */
+#define sym_stest4  0x52    /* new with 895/896 */
+#define sym_sodl	0x54	/* scsi output data latch */
+#define sym_sbdl	0x58	/* scsi bus data lines */
+#define sym_scratchb 0x5c	/* general purpose scratch pad b [4 bytes] */
+
+
+/*----------------------------------------------------------------------*/
+/* operating registers bit definitions */
+
+/* 0x00 - scntl0 (scsi control 0) bit definitions */
+
+#define sym_scntl0_trg	0x01	/* target mode [1 = target, 0 = initiator */
+#define sym_scntl0_aap	0x02	/* assert SATN on parity */
+#define sym_scntl0_epc	0x08	/* enable parity checking */
+#define sym_scntl0_watn	0x10	/* select with SATN on a start sequence */
+#define sym_scntl0_start 0x20	/* start sequence */
+#define sym_scntl0_arb0	0x40	/* arbitration mode bit 0 */
+#define sym_scntl0_arb1	0x80	/* arbitration mode bit 1 */
+
+
+/* 0x01 - scntl1 (scsi control 1) bit definitions */
+
+#define sym_scntl1_sst	0x01	/* start scsi transfer */
+#define sym_scntl1_iarb	0x02	/* immediate arbitration */
+#define sym_scntl1_aesp	0x04	/* assert even scsi parity (force bad parity) */
+#define sym_scntl1_rst	0x08	/* assert scsi RST signal */
+#define sym_scntl1_con	0x10	/* connected */
+#define sym_scntl1_dhp	0x20	/* disable halt on parity error or ATN */
+#define sym_scntl1_adb	0x40	/* assert scsi data bus */
+#define sym_scntl1_exc	0x80	/* extra clock cycle of data setup */
+
+
+/* 0x02 - scntl2 (scsi control 2) bit definitions */
+
+#define sym_scntl2_sdu	0x80	/* scsi disconnect unexpected */
+
+
+/* 0x03 - scntl3 (scsi control 3) bit definitions */
+
+#define sym_scntl3_ccf	0x07	/* clock conversion factor [mask] */
+#define sym_scntl3_scf	0x70	/* synchronous clock conversion factor [mask] */
+
+
+/* 0x04 - scid (scsi chip id) bit definitions */
+
+#define sym_scid_enc	0x07	/* encoded scsi id [mask] */
+#define sym_scid_sre	0x20	/* enable responce to selection */
+#define sym_scid_rre	0x40	/* enable responce to reselection */
+
+
+/* 0x05 - sxfer (scsi transfer) bit definitions */
+
+#define sym_sxfer_mo	0x0f	/* max scsi synchronous offset [mask] */
+#define sym_sxfer_tp	0xe0	/* scsi synchronous transfer period [mask] */
+
+
+/* 0x06 - sdid (scsi destination id) bit definitions */
+
+#define sym_sdid_enc	0x07	/* encoded destination scsi id [mask] */
+
+
+/* 0x07 - gpreg (general purpose) bit definitions */
+
+#define sym_gpreg_gpio0	0x01	/* general purpose */
+#define sym_gpreg_gpio1	0x02	/* general purpose */
+
+
+/* 0x09 - socl (scsi output control latch) bit definitions */
+
+#define sym_socl_io		0x01	/* assert i/o signal */
+#define sym_socl_cd		0x02	/* assert c/d signal */
+#define sym_socl_msg	0x04	/* assert msg signal */
+#define sym_socl_atn	0x08	/* assert atn signal */
+#define sym_socl_sel	0x10	/* assert sel signal */
+#define sym_socl_bsy	0x20	/* assert bsy signal */
+#define sym_socl_ack	0x40	/* assert ack signal */
+#define sym_socl_req	0x80	/* assert req signal */
+
+
+/* 0x0a - ssid (scsi selector id) bit definitions */
+
+#define sym_ssid_encid	0x07	/* encoded destination scsi id [mask] */
+#define sym_ssid_val	0x80	/* scsi valid bit */
+
+
+/* 0x0b - sbcl (scsi bus control lines) bit definitions */
+
+#define sym_sbcl_io		0x01	/* i/o status */
+#define sym_sbcl_cd		0x02	/* c/d status */
+#define sym_sbcl_msg	0x04	/* msg status */
+#define sym_sbcl_atn	0x08	/* atn status */
+#define sym_sbcl_sel	0x10	/* sel status */
+#define sym_sbcl_bsy	0x20	/* bsy status */
+#define sym_sbcl_ack	0x40	/* ack status */
+#define sym_sbcl_req	0x80	/* req status */
+
+
+/* 0x0c - dstat (dma status) bit definitions */
+
+#define sym_dstat_iid	0x01	/* illegal instruction detected */
+#define sym_dstat_sir	0x04	/* scripts interrupt instruction received */
+#define sym_dstat_ssi	0x08	/* single step interrupt */
+#define sym_dstat_abrt	0x10	/* aborted */
+#define sym_dstat_bf	0x20	/* bus fault */
+#define sym_dstat_mdpe	0x40	/* master data parity error */
+#define sym_dstat_dfe	0x80	/* dma fifo empty */
+
+
+/* 0x0d - sstat0 (scsi status 0) bit definitions */
+
+#define sym_sstat0_sdp	0x01	/* scsi parity signal */
+#define sym_sstat0_rst	0x02	/* scsi reset signal */
+#define sym_sstat0_woa	0x04	/* won arbitration */
+#define sym_sstat0_loa	0x08	/* lost arbitration */
+#define sym_sstat0_aip	0x10	/* arbitration in progress */
+#define sym_sstat0_olf	0x20	/* scsi output data latch full */
+#define sym_sstat0_orf	0x40	/* scsi output data register full */
+#define sym_sstat0_ilf	0x80	/* scsi input data latch full */
+
+
+/* 0x0e - sstat1 (scsi status 1) bit definitions */
+
+#define sym_sstat1_io	0x01	/* scsi i/o signal */
+#define sym_sstat1_cd	0x02	/* scsi c/d signal */
+#define sym_sstat1_msg	0x04	/* scsi msg signal */
+#define sym_sstat1_sdpl	0x08	/* latched scsi parity */
+#define sym_sstat1_fifo	0xf0	/* mask for fifo flags [mask] */
+
+
+/* 0x0f - sstat2 (scsi status 2) bit definitions */
+
+#define sym_sstat2_ldsc	0x02	/* last disconnect */
+
+
+/* 0x14 - istat (interrupt status) bit definitions */
+
+#define sym_istat_dip	0x01	/* dma interrupt pending */
+#define sym_istat_sip	0x02	/* scsi interrupt pending */
+#define sym_istat_intf	0x04	/* interrupt on the fly */
+#define sym_istat_con	0x08	/* connected */
+#define sym_istat_sem	0x10	/* semaphore */
+#define sym_istat_sigp	0x20	/* signal process */
+#define sym_istat_srst	0x40	/* software reset */
+#define sym_istat_abrt	0x80	/* abort operation */
+
+
+/* 0x19 - ctest1 (chip test 1) bit definitions */
+
+#define sym_ctest1_ffl	0x0f	/* byte empty in dma fifo [mask] */
+#define sym_ctest1_fmt	0xf0	/* byte full in dma fifo [mask] */
+
+
+/* 0x1a - ctest2 (chip test 2) bit definitions */
+
+#define sym_ctest2_dack	0x01	/* data acknowledge status */
+#define sym_ctest2_dreq	0x02	/* data request status */
+#define sym_ctest2_teop	0x04	/* scsi true end of process */
+#define sym_ctest2_cm	0x10	/* configured as memory */
+#define sym_ctest2_cio	0x20	/* configured as i/o */
+#define sym_ctest2_sigp	0x40	/* signal process */
+#define sym_ctest2_ddir	0x80	/* data transfer direction */
+
+
+/* 0x1b - ctest3 (chip test 3) bit definitions */
+
+#define sym_ctest3_fm	0x02	/* fetch pin mode */
+#define sym_ctest3_clf	0x04	/* clear dma fifo */
+#define sym_ctest3_flf	0x08	/* flush dma fifo */
+#define sym_ctest3_v	0xf0	/* chip revision level [mask] */
+
+
+/* 0x20 - dfifo (dma fifo) bit definitions */
+
+#define sym_dfifo_bo	0x7f	/* byte offset counter */
+
+
+/* 0x21 - ctest4 (chip test 4) bit definitions */
+
+#define sym_ctest4_fbl	0x07	/* fifo byte control [mask] */
+#define sym_ctest4_mpee	0x08	/* master parity error enable */
+#define sym_ctest4_srtm	0x10	/* shadow register test mode */
+#define sym_ctest4_zsd	0x20	/* scsi data high impedance */
+#define sym_ctest4_zmod	0x40	/* high impedance mode */
+#define sym_ctest4_bdis	0x80	/* burst disable */
+
+/* 0x22 - ctest5 (chip test 5) bit definitions */
+
+#define sym_ctest5_ddir	0x08	/* dma direction */
+#define sym_ctest5_masr	0x10	/* master control for set or reset pulses */
+#define sym_ctest5_bbck	0x40	/* clock byte counter */
+#define sym_ctest5_adck	0x80	/* clock address incrementor */
+
+
+/* 0x38 - dmode (dma mode) bit definitions */
+
+#define sym_dmode_man	0x01	/* manual start mode */
+#define sym_dmode_erl	0x08	/* enable read line */
+#define sym_dmode_diom	0x10	/* destination i/o memory enable */
+#define sym_dmode_siom	0x20	/* source i/o memory enable */
+#define sym_dmode_bl	0xc0	/* burst length */
+
+
+/* 0x39 - dien (dma interrupt enable) bit definitions */
+
+#define sym_dien_iid	0x01	/* illegal instruction detected */
+#define sym_dien_sir	0x04	/* scripts interrupt instruction received */
+#define sym_dien_ssi	0x08	/* single step instruction */
+#define sym_dien_abrt	0x10	/* aborted */
+#define sym_dien_bf		0x20	/* bus fault */
+#define sym_dien_mdpe	0x40	/* master data parity error */
+
+
+/* 0x3b - dcntl (dma control) bit definitions */
+
+#define sym_dcntl_com	0x01	/* 53c700 compatibility */
+#define sym_dcntl_std	0x04	/* start dma operation */
+#define sym_dcntl_irqm	0x08	/* irq mode */
+#define sym_dcntl_ssm	0x10	/* single step mode */
+
+
+/* 0x40 - sien0 (scsi interrupt enable 0) bit definitions */
+
+#define sym_sien0_par	0x01	/* scsi parity error */
+#define sym_sien0_rst	0x02	/* scsi reset condition */
+#define sym_sien0_udc	0x04	/* unexpected disconnect */
+#define sym_sien0_sge	0x08	/* scsi gross error */
+#define sym_sien0_rsl	0x10	/* reselected */
+#define sym_sien0_sel	0x20	/* selected */
+#define sym_sien0_cmp	0x40	/* function complete */
+#define sym_sien0_ma	0x80	/* scsi phase mismatch or scsi atn condition */
+
+
+/* 0x41 - sien1 (scsi interrupt enable 1) bit definitions */
+
+#define sym_sien1_hth	0x01	/* handshake to handshake timer expired */
+#define sym_sien1_gen	0x02	/* general purpose timer expired */
+#define sym_sien1_sto	0x04	/* selection or reselection timeout */
+#define sym_sien1_sbmc  0x10    /* SCSI Bus Mode Change */
+
+/* 0x42 - sist0 (scsi interrupt status 0) bit definitions */
+
+#define sym_sist0_par	0x01	/* parity error */
+#define sym_sist0_rst	0x02	/* scsi rst/received */
+#define sym_sist0_udc	0x04	/* unexpected disconnect */
+#define sym_sist0_sge	0x08	/* scsi gross error */
+#define sym_sist0_rsl	0x10	/* reselected */
+#define sym_sist0_sel	0x20	/* selected */
+#define sym_sist0_cmp	0x40	/* function complete */
+#define sym_sist0_ma	0x80	/* scsi phase mismatch or scsi atn condition */
+
+
+/* 0x43 - sist1 (scsi interrupt status 1) bit definitions */
+
+#define sym_sist1_hth	0x01	/* handshake to handshake timer expired */
+#define sym_sist1_gen	0x02	/* general purpose timer expired */
+#define sym_sist1_sto	0x04	/* selection or reselection timeout */
+#define sym_sist1_sbmc  0x10    /* SCSI Bus Mode Change */
+
+/* 0x46 - macntl (memory access control) bit definitions */
+
+#define sym_macntl_scpts 0x01	/* scripts */
+#define sym_macntl_pscpt 0x02	/* pointer scripts */
+#define sym_macntl_drd	0x04	/* data read */
+#define sym_macntl_dwr	0x08	/* data write */
+#define sym_macntl_typ	0xf0	/* chip type [mask] */
+
+
+/* 0x47 - gpcntl (general purpose pin control) bit definitions */
+
+#define sym_gpcntl_gpio0 0x01	/* gpio 0 */
+#define sym_gpcntl_gpio1 0x02	/* gpio 1 */
+#define sym_gpcntl_fe	0x40	/* fetch enable */
+#define sym_gpcntl_me	0x80	/* master enable */
+
+
+/* 0x48 - stime0 (scsi timer 0) bit definitions */
+
+#define sym_stime0_sel	0x07	/* selection time-out [mask] */
+#define sym_stime0_hth	0xf8	/* handshake to handshake timer period [mask] */
+
+
+/* 0x49 - stime1 (scsi timer 1) bit definitions */
+
+#define sym_stime1_gen	0x0f	/* general purpose timer period [mask] */
+
+
+/* 0x4c - stest0 (scsi test 0) bit definitions */
+
+#define sym_stest0_som	0x01	/* scsi synchronous offset maximum */
+#define sym_stest0_soz	0x02	/* scsi synchronous offset zero */
+#define sym_stest0_art	0x04	/* arbitration priority encoder test */
+#define sym_stest0_slt	0x08	/* selection response logic test */
+
+
+/* 0x4d - stest1 (scsi test 1) bit definitions */
+
+#define sym_stest1_sclk	0x80	/* sclk */
+
+
+/* 0x4e - stest2 (scsi test 2) bit definitions */
+
+#define sym_stest2_low	0x01	/* scsi low level mode */
+#define sym_stest2_ext	0x02	/* extend sreq/sack filtering */
+#define sym_stest2_szm	0x08	/* scsi high-impedance mode */
+#define sym_stest2_slb	0x10	/* scsi loopback mode */
+#define sym_stest2_rof	0x40	/* reset scsi offset */
+#define sym_stest2_sce	0x80	/* scsi control enable */
+
+
+/* 0x4f - stest3 (scsi test 3) bit definitions */
+
+#define sym_stest3_stw	0x01	/* scsi fifo test write */
+#define sym_stest3_csf	0x02	/* clear scsi fifo */
+#define sym_stest3_ttm	0x04	/* timer test mode */
+#define sym_stest3_dsi	0x10	/* disable single initiator response */
+#define sym_stest3_hsc	0x20	/* halt scsi clock */
+#define sym_stest3_str	0x40	/* scsi fifo test read */
+#define sym_stest3_te	0x80	/* tolerant enable */
+
+#define sym_stest4_hvd  0x40    /* high voltage diff */
+#define sym_stest4_se   0x80    /* single ended */
+#define sym_stest4_lvd  0xc0    /* low voltage diff */
+#define sym_stest4_lock 0x20    /* clock quadrupler locker */
+
+#endif

src/add-ons/kernel/busses/scsi/53c8xx/Jamfile

@@ -0,0 +1,15 @@
+SubDir HAIKU_TOP src add-ons kernel busses scsi symbios ;
+
+SetSubDirSupportedPlatformsBeOSCompatible ;
+
+SubDirCcFlags -DBUILD_LOADABLE ;
+
+KernelAddon 53c8xx : kernel busses scsi :
+	53c8xx.c
+;
+
+Package haiku-53c8xx-cvs
+	:
+	53c8xx
+	:
+	boot home config add-ons kernel busses scsi ;

src/add-ons/kernel/busses/scsi/53c8xx/LICENSE

@@ -0,0 +1,31 @@
+----------------------
+Be Sample Code License
+----------------------
+
+Copyright 1991-1999, Be Incorporated.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions, and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions, and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. The name of the author may not be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.    

src/add-ons/kernel/busses/scsi/53c8xx/scripts.c

@@ -0,0 +1,279 @@
+/*
+	Copyright 1999, Be Incorporated.   All Rights Reserved.
+	This file may be used under the terms of the Be Sample Code License.
+*/
+
+typedef unsigned long ULONG;
+
+ULONG	SCRIPT[] = {
+	0x50000000L,	0x00000010L,
+	0x98080000L,	0x00000011L,
+	0x721A0000L,	0x00000000L,
+	0x98080000L,	0x00000010L,
+	0x43000000L,	0x00000040L,
+	0x860B0000L,	0x00000038L,
+	0x98080000L,	0x00000012L,
+	0x98080000L,	0x00000013L,
+	0x98080000L,	0x00000011L,
+	0x42000000L,	0x00000050L,
+	0x870B0000L,	0x00000088L,
+	0x860A0000L,	0x000001D8L,
+	0x820A0000L,	0x000001E8L,
+	0x810A0000L,	0x000001F8L,
+	0x800A0000L,	0x000001F8L,
+	0x830A0000L,	0x00000200L,
+	0x98080000L,	0x00000019L,
+	0x1F000000L,	0x00000010L,
+	0x800C0001L,	0x00000170L,
+	0x800C0004L,	0x00000238L,
+	0x800C0023L,	0x00000150L,
+	0x60000040L,	0x00000000L,
+	0x800C0002L,	0x00000050L,
+	0x800C0007L,	0x00000050L,
+	0x800C0003L,	0x00000050L,
+	0x800C0080L,	0x00000050L,
+	0x800C0081L,	0x00000050L,
+	0x800C0082L,	0x00000050L,
+	0x800C0083L,	0x00000050L,
+	0x800C0084L,	0x00000050L,
+	0x800C0085L,	0x00000050L,
+	0x800C0086L,	0x00000050L,
+	0x800C0087L,	0x00000050L,
+	0x800C00C0L,	0x00000050L,
+	0x800C00C1L,	0x00000050L,
+	0x800C00C2L,	0x00000050L,
+	0x800C00C3L,	0x00000050L,
+	0x800C00C4L,	0x00000050L,
+	0x800C00C5L,	0x00000050L,
+	0x800C00C6L,	0x00000050L,
+	0x800C00C7L,	0x00000050L,
+	0x98080000L,	0x0000001AL,
+	0x60000040L,	0x00000000L,
+	0x1F000000L,	0x00000018L,
+	0x60000040L,	0x00000000L,
+	0x80080000L,	0x00000050L,
+	0x60000040L,	0x00000000L,
+	0x1F000000L,	0x00000018L,
+	0x800C0003L,	0x000001B8L,
+	0x800C0002L,	0x00000198L,
+	0x98080000L,	0x0000001BL,
+	0x60000040L,	0x00000000L,
+	0x1F000000L,	0x00000038L,
+	0x60000040L,	0x00000000L,
+	0x98080000L,	0x0000001FL,
+	0x60000040L,	0x00000000L,
+	0x1F000000L,	0x00000020L,
+	0x60000040L,	0x00000000L,
+	0x98080000L,	0x0000001EL,
+	0x1E000000L,	0x00000008L,
+	0x80080000L,	0x00000050L,
+	0x1A000000L,	0x00000030L,
+	0x80080000L,	0x00000050L,
+	0x98080000L,	0x00000017L,
+	0x1B000000L,	0x00000028L,
+	0x9F030000L,	0x00000016L,
+	0x1F000000L,	0x00000010L,
+	0x7C027F00L,	0x00000000L,
+	0x60000040L,	0x00000000L,
+	0x48000000L,	0x00000000L,
+	0x98080000L,	0x00000014L,
+	0x7C027F00L,	0x00000000L,
+	0x60000040L,	0x00000000L,
+	0x48000000L,	0x00000000L,
+	0x98080000L,	0x00000015L,
+	0x98080000L,	0x0000001CL
+
+};
+
+#define Abs_Count 22
+char *Absolute_Names[Abs_Count] = {
+	"ctxt_command",
+	"ctxt_extdmsg",
+	"ctxt_recvmsg",
+	"ctxt_sendmsg",
+	"ctxt_device",
+	"ctxt_status",
+	"ctxt_syncmsg",
+	"ctxt_widemsg",
+	"status_badextmsg",
+	"status_badmsg",
+	"status_badphase",
+	"status_badstatus",
+	"status_disconnect",
+	"status_complete",
+	"status_overrun",
+	"status_ready",
+	"status_reselected",
+	"status_selected",
+	"status_selftest",
+	"status_syncin",
+	"status_timeout",
+	"status_widein"
+};
+
+#define A_ctxt_device	0x00000000L
+ULONG A_ctxt_device_Used[] = {
+	0x00000008L,
+	0x00000012L
+};
+
+#define A_ctxt_sendmsg	0x00000008L
+ULONG A_ctxt_sendmsg_Used[] = {
+	0x00000077L
+};
+
+#define A_ctxt_recvmsg	0x00000010L
+ULONG A_ctxt_recvmsg_Used[] = {
+	0x00000023L,
+	0x00000085L
+};
+
+#define A_status_ready	0x00000010L
+ULONG A_status_ready_Used[] = {
+	0x00000007L
+};
+
+#define A_status_reselected	0x00000011L
+ULONG A_status_reselected_Used[] = {
+	0x00000003L,
+	0x00000011L
+};
+
+#define A_status_timeout	0x00000012L
+ULONG A_status_timeout_Used[] = {
+	0x0000000DL
+};
+
+#define A_status_selected	0x00000013L
+ULONG A_status_selected_Used[] = {
+	0x0000000FL
+};
+
+#define A_status_complete	0x00000014L
+ULONG A_status_complete_Used[] = {
+	0x0000008DL
+};
+
+#define A_status_disconnect	0x00000015L
+ULONG A_status_disconnect_Used[] = {
+	0x00000095L
+};
+
+#define A_status_badstatus	0x00000016L
+ULONG A_status_badstatus_Used[] = {
+	0x00000083L
+};
+
+#define A_status_overrun	0x00000017L
+ULONG A_status_overrun_Used[] = {
+	0x0000007FL
+};
+
+#define A_ctxt_extdmsg	0x00000018L
+ULONG A_ctxt_extdmsg_Used[] = {
+	0x00000057L,
+	0x0000005FL
+};
+
+#define A_status_badphase	0x00000019L
+ULONG A_status_badphase_Used[] = {
+	0x00000021L
+};
+
+#define A_status_badmsg	0x0000001AL
+ULONG A_status_badmsg_Used[] = {
+	0x00000053L
+};
+
+#define A_status_badextmsg	0x0000001BL
+ULONG A_status_badextmsg_Used[] = {
+	0x00000065L
+};
+
+#define A_status_selftest	0x0000001CL
+ULONG A_status_selftest_Used[] = {
+	0x00000097L
+};
+
+#define A_status_syncin	0x0000001EL
+ULONG A_status_syncin_Used[] = {
+	0x00000075L
+};
+
+#define A_status_widein	0x0000001FL
+ULONG A_status_widein_Used[] = {
+	0x0000006DL
+};
+
+#define A_ctxt_syncmsg	0x00000020L
+ULONG A_ctxt_syncmsg_Used[] = {
+	0x00000071L
+};
+
+#define A_ctxt_status	0x00000028L
+ULONG A_ctxt_status_Used[] = {
+	0x00000081L
+};
+
+#define A_ctxt_command	0x00000030L
+ULONG A_ctxt_command_Used[] = {
+	0x0000007BL
+};
+
+#define A_ctxt_widemsg	0x00000038L
+ULONG A_ctxt_widemsg_Used[] = {
+	0x00000069L
+};
+
+#define Ent_do_dataout       	0x00000070L
+#define Ent_do_datain        	0x00000068L
+#define Ent_idle             	0x00000000L
+#define Ent_phase_dataerr    	0x000001F8L
+#define Ent_start            	0x00000020L
+#define Ent_switch           	0x00000050L
+#define Ent_switch_resel     	0x00000048L
+#define Ent_test             	0x00000258L
+
+
+ULONG	LABELPATCHES[] = {
+	0x00000001L,
+	0x00000009L,
+	0x0000000BL,
+	0x00000013L,
+	0x00000015L,
+	0x00000017L,
+	0x00000019L,
+	0x0000001BL,
+	0x0000001DL,
+	0x0000001FL,
+	0x00000025L,
+	0x00000027L,
+	0x00000029L,
+	0x0000002DL,
+	0x0000002FL,
+	0x00000031L,
+	0x00000033L,
+	0x00000035L,
+	0x00000037L,
+	0x00000039L,
+	0x0000003BL,
+	0x0000003DL,
+	0x0000003FL,
+	0x00000041L,
+	0x00000043L,
+	0x00000045L,
+	0x00000047L,
+	0x00000049L,
+	0x0000004BL,
+	0x0000004DL,
+	0x0000004FL,
+	0x00000051L,
+	0x0000005BL,
+	0x00000061L,
+	0x00000063L,
+	0x00000079L,
+	0x0000007DL
+};
+
+ULONG	INSTRUCTIONS	= 0x0000004CL;
+ULONG	PATCHES		= 0x00000025L;

src/add-ons/kernel/busses/scsi/53c8xx/scripts.ss

@@ -0,0 +1,186 @@
+;
+; BeOS 53c8xx SCRIPTS
+;
+ARCH     810
+
+; Interrupt codes used to signal driver from SCRIPTS
+;
+ABSOLUTE status_ready           = 0x10  ; idle loop interrupted by driver
+ABSOLUTE status_reselected      = 0x11  ; select or idle interrupted by reselection
+ABSOLUTE status_timeout         = 0x12  ; select timed out
+ABSOLUTE status_selected        = 0x13  ; select succeeded
+ABSOLUTE status_complete        = 0x14  ; transaction completed
+ABSOLUTE status_disconnect      = 0x15  ; device disconnected in the middle
+ABSOLUTE status_badstatus       = 0x16  ; snafu in the status phase
+ABSOLUTE status_overrun         = 0x17  ; data overrun occurred
+ABSOLUTE status_underrun        = 0x18  ; data underrun occurred
+ABSOLUTE status_badphase        = 0x19  ; weird phase transition occurred
+ABSOLUTE status_badmsg          = 0x1a  ; bad msg received
+ABSOLUTE status_badextmsg       = 0x1b  ; bad extended msg received
+ABSOLUTE status_selftest        = 0x1c  ; used by selftest stub
+ABSOLUTE status_iocomplete      = 0x1d  ; used by driver
+ABSOLUTE status_syncin          = 0x1e  ; inbound sync msg
+ABSOLUTE status_widein          = 0x1f  ; inbound wdtr msg
+ABSOLUTE status_ignore_residue  = 0x20  ; ignore wide residue bytes
+
+; DSA-offset data table
+;
+ABSOLUTE ctxt_device      = 0x00             ; targ id, sync params, etc
+ABSOLUTE ctxt_sendmsg     = 0x08             ; outgoing (ID) msg(1) pointer
+ABSOLUTE ctxt_recvmsg     = 0x10             ; incoming msg(1) pointer
+ABSOLUTE ctxt_extdmsg     = 0x18             ; extdmsg(1) pointer
+ABSOLUTE ctxt_syncmsg     = 0x20             ; sync(2) pointer
+ABSOLUTE ctxt_status      = 0x28             ; status(1) pointer
+ABSOLUTE ctxt_command     = 0x30             ; command(6,10,12) pointer
+ABSOLUTE ctxt_widemsg     = 0x38             ; wide(2) pointer
+
+ENTRY start
+ENTRY idle
+ENTRY switch
+ENTRY switch_resel
+ENTRY phase_dataerr
+ENTRY test
+
+ENTRY do_datain
+ENTRY do_dataout
+
+; ------------------------------------------------------------------------------------
+; Idle loop -- when no new requests are pending wait for a reselect
+; or interrupt from the driver
+;
+idle:
+	WAIT RESELECT interrupted
+	INT status_reselected
+	
+interrupted:	
+	MOVE CTEST2 TO SFBR                      ; read sigp to clear it
+	INT status_ready		
+
+	
+; ------------------------------------------------------------------------------------
+; Driver must load DSA and jump here to attempt to select a target, beginning a new
+; transaction.  Interrupt will indicate success, timeout, or reselection
+;
+start:
+	SELECT ATN FROM ctxt_device, resel       ; try to select the dev for the req
+	JUMP selected, WHEN MSG_OUT              ; force wait for timeout
+	INT status_timeout
+	
+selected:
+	INT status_selected		
+
+resel:
+	INT status_reselected
+
+
+; ------------------------------------------------------------------------------------
+; If we're entering the main dispatcher after a reselection, we must insure that 
+; the registers for SYNC/WIDE transfers are properly loaded.  This is the solution
+; suggested in 9-18 of the Symbios programming guide.
+;
+switch_resel:
+	SELECT FROM ctxt_device, switch          ; force the load of SXFER/SCNTL3, etc
+	
+; ------------------------------------------------------------------------------------
+; Main activity entry -- driver must set DSA and patch do_datain and do_dataout
+; before starting this dispatch function.
+;	
+switch:
+	JUMP phase_msgin, WHEN MSG_IN
+	JUMP phase_msgout, IF MSG_OUT	
+	JUMP phase_command, IF CMD
+do_datain:	                                 ; Patched by driver 
+	JUMP phase_dataerr, IF DATA_IN
+do_dataout:                                  ; Patched by driver
+	JUMP phase_dataerr, IF DATA_OUT
+	JUMP phase_status, IF STATUS
+	INT status_badphase
+
+phase_msgin:
+	MOVE FROM ctxt_recvmsg, WHEN MSG_IN
+	JUMP phase_msgin_ext, IF 0x01
+	JUMP disc, IF 0x04
+	JUMP ignore, IF 0x23       ; /* wide ignore residue */
+	CLEAR ACK
+	JUMP switch, IF 0x02       ; ignore save data pointers
+	JUMP switch, IF 0x07       ; ignore message reject :)
+	JUMP switch, IF 0x03       ; ignore restore data pointers
+	JUMP switch, IF 0x80       ; ignore ident after reselect
+	JUMP switch, IF 0x81       ; ignore ident after reselect
+	JUMP switch, IF 0x82       ; ignore ident after reselect
+	JUMP switch, IF 0x83       ; ignore ident after reselect
+	JUMP switch, IF 0x84       ; ignore ident after reselect
+	JUMP switch, IF 0x85       ; ignore ident after reselect
+	JUMP switch, IF 0x86       ; ignore ident after reselect
+	JUMP switch, IF 0x87       ; ignore ident after reselect
+	JUMP switch, IF 0xC0       ; ignore ident after reselect
+	JUMP switch, IF 0xC1       ; ignore ident after reselect
+	JUMP switch, IF 0xC2       ; ignore ident after reselect
+	JUMP switch, IF 0xC3       ; ignore ident after reselect
+	JUMP switch, IF 0xC4       ; ignore ident after reselect
+	JUMP switch, IF 0xC5       ; ignore ident after reselect
+	JUMP switch, IF 0xC6       ; ignore ident after reselect
+	JUMP switch, IF 0xC7       ; ignore ident after reselect
+	INT status_badmsg
+
+ignore:
+	CLEAR ACK
+	MOVE FROM ctxt_extdmsg, WHEN MSG_IN  ; read status byte
+	CLEAR ACK
+	JUMP switch
+;	INT status_ignore_residue
+	
+phase_msgin_ext:
+	CLEAR ACK
+	MOVE FROM ctxt_extdmsg, WHEN MSG_IN  ; read extended message length
+	JUMP phase_msgin_sync, IF 0x03
+	JUMP phase_msgin_wide, IF 0x02
+	INT status_badextmsg
+
+phase_msgin_wide:
+	CLEAR ACK
+	MOVE FROM ctxt_widemsg, WHEN MSG_IN
+	CLEAR ACK
+	INT status_widein
+	
+phase_msgin_sync:
+	CLEAR ACK
+	MOVE FROM ctxt_syncmsg, WHEN MSG_IN
+	CLEAR ACK
+	INT status_syncin
+	
+phase_msgout:
+	MOVE FROM ctxt_sendmsg, WHEN MSG_OUT
+	JUMP switch
+	
+phase_command:
+	MOVE FROM ctxt_command, WHEN CMD
+	JUMP switch
+	
+phase_dataerr:
+	INT status_overrun
+	
+phase_status:
+	MOVE FROM ctxt_status, WHEN STATUS
+	INT status_badstatus, WHEN NOT MSG_IN
+	MOVE FROM ctxt_recvmsg, WHEN MSG_IN
+	INT status_badmsg, IF NOT 0x00 ; not disconnect?!
+	MOVE SCNTL2 & 0x7f TO SCNTL2
+	CLEAR ACK
+	WAIT DISCONNECT
+	INT status_complete
+
+disc:
+	MOVE SCNTL2 & 0x7f to SCNTL2              ; expect disconnect
+	CLEAR ACK
+	WAIT DISCONNECT
+	INT status_disconnect
+
+; ------------------------------------------------------------------------------------
+; Self-test snippet
+;
+test:
+	INT status_selftest
+
+
+	

src/add-ons/kernel/busses/scsi/53c8xx/symbios.h

@@ -0,0 +1,167 @@
+/*
+	Copyright 1999, Be Incorporated.   All Rights Reserved.
+	This file may be used under the terms of the Be Sample Code License.
+*/
+
+/*
+** 53c8xx Driver - Data structures and shared constants 
+*/
+
+/* status codes signaled from SCRIPTS to driver */
+#define status_ready           0x10  // idle loop interrupted by driver
+#define status_reselected      0x11  // select or idle interrupted by reselection
+#define status_timeout         0x12  // select timed out
+#define status_selected        0x13  // select succeeded
+#define status_complete        0x14  // transaction completed
+#define status_disconnect      0x15  // device disconnected in the middle
+#define status_badstatus       0x16  // snafu in the status phase
+#define status_overrun         0x17  // data overrun occurred
+#define status_underrun        0x18  // data underrun occurred
+#define status_badphase        0x19  // weird phase transition occurred
+#define status_badmsg          0x1a  // bad msg received
+#define status_badextmsg       0x1b  // bad extended msg received
+#define status_selftest        0x1c  // used by selftest stub
+#define status_iocomplete      0x1d  
+#define status_syncin          0x1e
+#define status_widein          0x1f
+#define status_ignore_residue  0x20
+
+/* status codes private to driver */
+#define status_inactive        0x00  // no request pending
+#define status_queued          0x01  // start request is in the startqueue
+#define status_selecting       0x02  // attempting to select
+#define status_active          0x03  // SCRIPTS is handling it
+#define status_waiting         0x04  // Waiting for reselection
+
+#define OP_NDATA_IN  0x09000000L
+#define OP_NDATA_OUT 0x08000000L
+#define OP_WDATA_IN  0x01000000L
+#define OP_WDATA_OUT 0x00000000L
+
+#define OP_END      0x98080000L
+#define ARG_END     (status_iocomplete)
+
+typedef struct
+{
+	uint32 count;
+	uint32 address;
+} SymInd;
+
+#define PATCH_DATAIN ((Ent_do_datain/4) + 1)
+#define PATCH_DATAOUT ((Ent_do_dataout/4) + 1)
+
+
+#define ctxt_device    0
+#define ctxt_sendmsg   1
+#define ctxt_recvmsg   2
+#define ctxt_extdmsg   3
+#define ctxt_syncmsg   4
+#define ctxt_status    5
+#define ctxt_command   6
+#define ctxt_widemsg   7
+#define ctxt_program   8
+
+typedef struct 
+{
+	uchar _command[12];       /*  0 - 11 */
+	uchar _syncmsg[2];        /* 12 - 13 */
+	uchar _widemsg[2];        /* 14 - 15 */
+	uchar _sendmsg[8];        /* 16 - 23 */
+	uchar _recvmsg[1];        /*      24 */
+	uchar _extdmsg[1];        /*      25 */
+	uchar _status[1];         /*      26 */
+	uchar _padding[1];        /*      27 */
+ 
+	SymInd device;            /*      28 */
+	SymInd sendmsg;           /*      36 */
+	SymInd recvmsg;           /*      44 */
+	SymInd extdmsg;           /*      52 */
+	SymInd syncmsg;           /*      60 */
+	SymInd status;            /*      68 */
+	SymInd command;           /*      76 */
+	SymInd widemsg;           /*      84 */
+	
+/* MUST be dword aligned! */
+	SymInd table[131];        /*      92 --- 129 entries, 1 eot, 1 scratch */ 
+} SymPriv;
+
+#define ADJUST_PRIV_TO_DSA    28
+#define ADJUST_PRIV_TO_TABLE  92
+
+typedef struct _SymTarg
+{
+	struct _Symbios *adapter;
+	struct _SymTarg *next;
+	
+	uchar device[4];     /* symbios register defs for the device */
+	int sem_targ;        /* mutex allowing only one req per target */
+	int sem_done;        /* notification semaphore */
+	CCB_SCSIIO *ccb;     /* ccb for the current request for this target or NULL */
+	
+	SymPriv *priv;	     /* priv data area within ccb */
+	uint32 priv_phys;    /* physical address of priv */
+	uint32 table_phys;   /* physical address of sgtable */
+	uint32 datain_phys;  
+	uint32 dataout_phys;
+	
+	int inbound;         /* read data from device */
+	
+	uint32 period;       /* sync period */
+	uint32 offset;       /* sync offset */
+	uint32 wide;
+	
+	uint32 flags;
+	uint32 status;
+	uint32 id;	
+} SymTarg;
+
+#define tf_ask_sync   0x0001
+#define tf_ask_wide   0x0002
+#define tf_is_sync    0x0010
+#define tf_is_wide    0x0020
+#define tf_ignore     0x0100
+
+typedef struct _Symbios
+{
+	uint32 num;           /* card number */
+	uint32 iobase;        /* io base address */ 
+	uint32 irq;           /* assigned irq */
+	
+	char *name;           /* device type name */
+	uint32 host_targ_id; 
+	uint32 max_targ_id;
+	int reset;
+
+	int registered;
+		
+	uint32 *script;       /* 1 page of on/offboard scripts ram */
+	uint32 sram_phys;     /* physical address thereof */
+	
+	SymTarg targ[16];     /* one targ descriptor per target */
+	spinlock hwlock;      /* lock protecting register access */
+	
+	SymTarg *startqueue;   /* target being started */
+	SymTarg *startqueuetail;
+	SymTarg *active;      /* target currently being interacted with */
+	                      /* null if IDLE, == startqueue if starting */
+
+	enum {
+		OFFLINE, IDLE, START, ACTIVE, TEST
+	} status;
+	
+	struct {
+		uint period;    /* negotiated period */
+		uint  period_ns; /* configured period in ns */
+		uchar scntl3;    /* values for scntl3 SCF and CCF bits */
+		uchar sxfer;     /* values for xfer TP2-0 bits */
+	} syncinfo[16];
+	uint32 syncsize;     /* number of syncinfo entries to look at */
+	uint32 idmask;
+	
+	uint32 scntl3;
+	uint32 sclk;         /* SCLK in KHz */
+	uint32 maxoffset;
+	
+	uint32 op_in;
+	uint32 op_out;
+} Symbios;

src/add-ons/kernel/busses/scsi/Jamfile

@@ -1,3 +1,5 @@
 SubDir HAIKU_TOP src add-ons kernel busses scsi ; 
 
 SubInclude HAIKU_TOP src add-ons kernel busses scsi usb ;
+SubInclude HAIKU_TOP src add-ons kernel busses scsi buslogic ;
+SubInclude HAIKU_TOP src add-ons kernel busses scsi 53c8xx ;

src/add-ons/kernel/busses/scsi/buslogic/Jamfile

@@ -0,0 +1,15 @@
+SubDir HAIKU_TOP src add-ons kernel busses scsi buslogic ;
+
+SetSubDirSupportedPlatformsBeOSCompatible ;
+
+SubDirCcFlags -DBUILD_LOADABLE ;
+
+KernelAddon buslogic : kernel busses scsi :
+	buslogic.c
+;
+
+Package haiku-buslogic-cvs
+	:
+	buslogic
+	:
+	boot home config add-ons kernel busses scsi ;

src/add-ons/kernel/busses/scsi/buslogic/LICENSE

@@ -0,0 +1,31 @@
+----------------------
+Be Sample Code License
+----------------------
+
+Copyright 1991-1999, Be Incorporated.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions, and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions, and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. The name of the author may not be used to endorse or promote products
+   derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF TITLE, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.    

src/add-ons/kernel/busses/scsi/buslogic/buslogic.h

@@ -0,0 +1,167 @@
+/*
+** $Id: buslogic.h,v 1.2 1998/04/21 00:51:57 swetland Exp $
+** 
+** Constants and Structures for BusLogic MultiMaster Controllers
+** Copyright 1998, Brian J. Swetland <swetland@frotz.net>
+**
+** This file may be used under the terms of the Be Sample Code License.
+*/
+
+#define PCI_VENDOR_BUSLOGIC     0x104b
+#define PCI_DEVICE_MULTIMASTER  0x1040
+
+
+/* BusLogic MultiMaster Register Definitions
+** cf. Technical Reference Manual, pp. 1-10 - 1-17
+*/
+#define BL_CONTROL_REG    (bl->iobase)
+#define BL_CONTROL_RHARD  0x80           /* Controller Hard Reset           */
+#define BL_CONTROL_RSOFT  0x40           /* Controller Soft Reset           */
+#define BL_CONTROL_RINT   0x20           /* Reset (Acknowledge) Interrupts  */
+#define BL_CONTROL_RSBUS  0x10           /* Reset SCSI Bus                  */
+
+#define BL_STATUS_REG     (bl->iobase)
+#define BL_STATUS_DACT    0x80           /* Diagnostic Active               */
+#define BL_STATUS_DFAIL   0x40           /* Diagnostic Failure              */
+#define BL_STATUS_INREQ   0x20           /* Initialization Required         */
+#define BL_STATUS_HARDY   0x10           /* Host Adapter Ready              */
+#define BL_STATUS_CPRBSY  0x08           /* Command/Param Out Register Busy */
+#define BL_STATUS_DIRRDY  0x04           /* Data In Register Ready          */
+#define BL_STATUS_CMDINV  0x01           /* Command Invalid                 */
+
+#define BL_COMMAND_REG    (bl->iobase + 1)
+#define BL_DATA_REG       (bl->iobase + 1)
+
+#define BL_INT_REG        (bl->iobase + 2)
+#define BL_INT_INTV       0x80           /* Interrupt Valid                 */
+#define BL_INT_RSTS       0x08           /* SCSI Reset State                */
+#define BL_INT_CMDC       0x04           /* Command Complete                */
+#define BL_INT_MBOR       0x02           /* Mailbox Out Ready               */
+#define BL_INT_IMBL       0x01           /* Incoming Mailbox Loaded         */
+
+
+#define MAX_SCATTER 130
+
+typedef struct _bl_ccb32
+{
+        /* buslogic ccb structure */
+    uchar   opcode;         /* operation code - see CCB_OP_* below         */
+    uchar   direction;      /* data direction control - see CCB_DIR_*      */
+    uchar   length_cdb;     /* length of the cdb                           */
+    uchar   length_sense;   /* length of sense data block                  */
+    uint32  length_data;    /* length of data block                        */
+    uint32  data;           /* 32bit physical pointer to data or s/g table */
+    uchar   _reserved1;     /* set to zero                                 */
+    uchar   _reserved2;     /* set to zero                                 */
+    uchar   btstat;         /* Host Adapter Status Return                  */
+    uchar   sdstat;         /* SCSI Device Status Return                   */
+    uchar   target_id;      /* Target SCSI ID                              */
+    uchar   lun_tag;        /* bits 0-2 = LUN, | with CCB_TAG_*            */
+    uchar   cdb[12];        /* SCSI CDB area                               */
+    uchar   ccb_control;    /* controle bits - see CCB_CONTROL_*           */
+    uchar   link_id;        /* id number for linked CCB's                  */
+    uint32  link;           /* 32bit physical pointer to a linked CCB      */
+    uint32  sense;          /* 32bit physical pointer to the sense datablk */
+
+        /* used by the driver */
+    
+    sem_id  done;           /* used by ISR for completion notification     */
+    int completion_code;    /* completion code storage from mailbox        */
+    struct _bl_ccb32 *next; /* chain pointer for CCB32 freelist            */
+    uint _reserved[3];      /* padding                                     */
+} BL_CCB32;
+
+typedef struct 
+{
+        /* used by the driver */
+    uchar sensedata[256];   /* data area for sense data return             */
+    
+    struct {
+        uint length;        /* length of this SG segment (bytes)           */
+        uint phys;          /* physical address of this SG segment         */
+    } sg[MAX_SCATTER];      /* scatter/gather table                        */
+} BL_PRIV;
+
+#define BL_CCB_TAG_SIMPLE    0x20
+#define BL_CCB_TAG_HEAD      0x60
+#define BL_CCB_TAG_ORDERED   0xA0
+
+#define BL_CCB_OP_INITIATE           0x00 
+#define BL_CCB_OP_INITIATE_SG        0x02
+
+/* returns dif between req/actual xmit bytecount */
+#define BL_CCB_OP_INITIATE_RETLEN    0x03
+#define BL_CCB_OP_INITIATE_RETLEN_SG 0x04
+#define BL_CCB_OP_SCSI_BUS_RESET     0x81
+
+#define BL_CCB_DIR_DEFAULT   0x00  /* transfer in direction native to scsi */
+#define BL_CCB_DIR_INBOUND   0x08
+#define BL_CCB_DIR_OUTBOUND  0x10
+#define BL_CCB_DIR_NO_XFER   0x18
+
+typedef struct 
+{
+    uint32 ccb_phys;
+    uchar _reserved1;
+    uchar _reserved2;
+    uchar _reserved3;
+    uchar action_code;
+} BL_Out_Mailbox32;
+
+#define BL_ActionCode_NotInUse   0x00
+#define BL_ActionCode_Start      0x01
+#define BL_ActionCode_Abort      0x02
+ 
+
+
+typedef struct 
+{
+    uint32 ccb_phys;
+    uchar btstat;
+    uchar sdstat;
+    uchar _reserved1;
+    uchar completion_code;
+} BL_In_Mailbox32;
+
+#define BL_CompletionCode_NotInUse     0x00
+#define BL_CompletionCode_NoError      0x01
+#define BL_CompletionCode_HostAbort    0x02
+#define BL_CompletionCode_NotFound     0x03
+#define BL_CompletionCode_Error        0x04
+
+#define MAX_CCB_COUNT 32
+
+/* Host Adapter State Structure
+**
+*/
+typedef struct 
+{
+    int id;                         /* board id 0, 1, ...    */
+    int done;                       /* command complete from ISR */
+    int irq;                        /* board's irq */
+    int iobase;                     /* base io address */
+	int scsi_id;					/* board's SCSI id */
+	int wide;                       /* wide target id's allowed */
+    long reqid;                     /* request counter for debugging */
+    
+	char productname[16];
+	
+    uint32 phys_to_virt;            /* adjustment for mapping BL_CCB32's */
+    uint32 virt_to_phys;            /* between virt and phys addrs       */
+    
+    uint32 phys_mailboxes;          /* phys addr of mailboxes */
+      
+    sem_id hw_lock;                 /* lock for hardware and outbox access */
+    sem_id ccb_lock;                /* lock protecting the ccb chain */
+    sem_id ccb_count;               /* counting sem protecting the ccb chain */
+    
+    int box_count;
+    int out_nextbox;
+    int in_nextbox;
+    BL_Out_Mailbox32  *out_boxes;
+    BL_In_Mailbox32   *in_boxes;
+
+    BL_CCB32 *ccb;                  /* table of MAX_CCB_COUNT CCB's */
+    BL_CCB32 *first_ccb;            /* head of ccb freelist         */
+} BusLogic;
+