removed small bug that could mess-up AGP3 compliance.

git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8417 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-07-18 18:32:12 +00:00
parent f24cfa8680
commit a93e7bcbd3
3 changed files with 15 additions and 8 deletions

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@ -74,7 +74,7 @@ This option is disabled by default (preceded by a '#').<br>
<li><strong>block_agp:</strong> (set to 'false' by default)<br>
If set to 'true' this option blocks use of AGP transfers entirely including PCI fastwrites: so fallback to standard 'old-fashioned' PCI mode.
<li><strong>block_sba:</strong> (set to 'false' by default)<br>
If set to 'true' this option blocks use of sideband adressing. Sideband adressing speeds up AGP transfers a bit because it's a seperate (low-speed) communications 'channel' that's used alongside the main transfer channel concurrently. So this enables 'full-duplex' communications, while disabling SBA forces the hardware to use 'half-duplex' communications.
If set to 'true' this option blocks use of sideband adressing if at least one of the devices on the bus is pre-AGP3.0. Sideband adressing speeds up AGP transfers a bit because it's a seperate (low-speed) communications 'channel' that's used alongside the main transfer channel concurrently. So this enables 'full-duplex' communications, while disabling SBA forces the hardware to use 'half-duplex' communications. SBA is a requirement for AGP3 compliance, so if AGP3 is in effect, this setting is ignored.
<li><strong>block_fw:</strong> (set to 'false' by default)<br>
If set to 'true' this option blocks use of PCI fastwrites. PCI fastwrites work in the same speed AGP transfers work. This means PCI fastwrites are faster in AGP4x mode than they are in AGP2x mode (for instance). PCI fastwrites are used whenever the system initializes transfers to the graphicscard, while 'standard PCI' or AGP transfers are used if the graphicscard's acceleration engine initializes transfers to or from the system.<br>
This means that PCI FW is the only AGP 'feature' that has an effect on the graphics speed on BeOS as it is currently. The use of AGP transfers require graphicsdriver support, and these type of transfers are 'officially' targeted specific for hardware accelerated 3D (which we do not yet have).<br>

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@ -302,6 +302,8 @@ void enable_agp (uint32 *command)
/* AGP 3.0 scheme applies */
if (*command & AGP_3_8x) *command |= AGP_3_4x;
*command &= ~0x00000004;
/* SBA is required for AGP3 */
*command |= AGP_SBA;
}
/* reset all other reserved and currently unused bits */
*command &= ~0x00fffce0;
@ -366,11 +368,9 @@ void enable_agp (uint32 *command)
if (pd->di[count].agpi.class_base == PCI_display)
{
pci_info *pcii = &(pd->di[count].pcii);
/* program graphicscard */
set_pci(pd->di[count].agp_adress + 8, 4, *command);
/* program graphicscard, making sure not-implemented bits are written as zeros */
set_pci(pd->di[count].agp_adress + 8, 4, (*command & ~AGP_rate_rev));
/* update our agp_cmd info with read back setting from register just programmed */
/* note:
* this 'sequence' resets the non-writable register bit AGP_rate_rev in our info */
pd->di[count].agpi.interface.agp_cmd = get_pci(pd->di[count].agp_adress + 8, 4);
}
}
@ -440,8 +440,15 @@ static void check_settings(uint32 *command)
}
if (current_settings.block_sba)
{
TRACE("agp_man: blocking SBA (agp.settings)\n");
*command &= ~AGP_SBA;
if (!(*command & AGP_rate_rev))
{
TRACE("agp_man: blocking SBA (agp.settings)\n");
*command &= ~AGP_SBA;
}
else
{
TRACE("agp_man: SBA is required for AGP3, not blocking (agp.settings)\n");
}
}
if (current_settings.block_fw)
{

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@ -8,5 +8,5 @@
#max_speed 2 # max AGP speed that may be used (valid are 1,2,4 or 8)
block_agp false # if true blocks use of AGP entirely: so fallback to PCI mode
block_sba false # if true blocks use of 'sideband adressing'
block_sba false # if true blocks use of 'sideband adressing' if possible
block_fw false # if true blocks use of 'fastwrites'