* Implemented clearing port enabled change
* Fixed build with debug output turned on * Cleaned up the uhci_hardware header a bit git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19861 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -280,8 +280,6 @@ Queue::PrintToStream()
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dprintf("USB UHCI Queue:\n");
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dprintf("link phy: 0x%08lx; link type: %s; terminate: %s\n", fQueueHead->link_phy & 0xfff0, fQueueHead->link_phy & 0x0002 ? "QH" : "TD", fQueueHead->link_phy & 0x0001 ? "yes" : "no");
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dprintf("elem phy: 0x%08lx; elem type: %s; terminate: %s\n", fQueueHead->element_phy & 0xfff0, fQueueHead->element_phy & 0x0002 ? "QH" : "TD", fQueueHead->element_phy & 0x0001 ? "yes" : "no");
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dprintf("elements:\n");
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print_descriptor_chain(fQueueTop);
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#endif
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}
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@ -990,6 +988,10 @@ UHCI::ClearPortFeature(uint8 index, uint16 feature)
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case C_PORT_CONNECTION:
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WriteReg16(portRegister, portStatus | UHCI_PORTSC_STATCHA);
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return B_OK;
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case C_PORT_ENABLE:
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WriteReg16(portRegister, portStatus | UHCI_PORTSC_ENABCHA);
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return B_OK;
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}
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return B_BAD_VALUE;
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@ -23,53 +23,53 @@
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#define PCI_LEGSUP_USBPIRQDEN 0x2000
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// Registers
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#define UHCI_USBCMD 0x0 // USB Command - word - R/W
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#define UHCI_USBSTS 0x2 // USB Status - word - R/WC
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#define UHCI_USBINTR 0x4 // USB Interrupt Enable - word - R/W
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#define UHCI_FRNUM 0x6 // Frame number - word - R/W**
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#define UHCI_FRBASEADD 0x08 // Frame List BAse Address - dword - R/W
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#define UHCI_SOFMOD 0xC // Start of Frame Modify - byte - R/W
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#define UHCI_PORTSC1 0x10 // Port 1 Status/Control - word - R/WC**
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#define UHCI_PORTSC2 0x12 // Port 2 Status/Control - word - R/WC**
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#define UHCI_USBCMD 0x00 // USB Command - word - R/W
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#define UHCI_USBSTS 0x02 // USB Status - word - R/WC
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#define UHCI_USBINTR 0x04 // USB Interrupt Enable - word - R/W
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#define UHCI_FRNUM 0x06 // Frame number - word - R/W**
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#define UHCI_FRBASEADD 0x08 // Frame List BAse Address - dword - R/W
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#define UHCI_SOFMOD 0x0c // Start of Frame Modify - byte - R/W
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#define UHCI_PORTSC1 0x10 // Port 1 Status/Control - word - R/WC**
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#define UHCI_PORTSC2 0x12 // Port 2 Status/Control - word - R/WC**
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// USBCMD
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#define UHCI_USBCMD_RS 0x1 // Run/Stop
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#define UHCI_USBCMD_HCRESET 0x2 // Host Controller Reset
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#define UHCI_USBCMD_GRESET 0x4 // Global Reset
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#define UHCI_USBCMD_EGSM 0x8 // Enter Global Suspensd mode
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#define UHCI_USBCMD_FGR 0x10 // Force Global resume
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#define UHCI_USBCMD_SWDBG 0x20 // Software Debug
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#define UHCI_USBCMD_CF 0x40 // Configure Flag
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#define UHCI_USBCMD_MAXP 0x80 // Max packet
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#define UHCI_USBCMD_RS 0x01 // Run/Stop
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#define UHCI_USBCMD_HCRESET 0x02 // Host Controller Reset
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#define UHCI_USBCMD_GRESET 0x04 // Global Reset
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#define UHCI_USBCMD_EGSM 0x08 // Enter Global Suspensd mode
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#define UHCI_USBCMD_FGR 0x10 // Force Global resume
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#define UHCI_USBCMD_SWDBG 0x20 // Software Debug
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#define UHCI_USBCMD_CF 0x40 // Configure Flag
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#define UHCI_USBCMD_MAXP 0x80 // Max packet
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//USBSTS
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#define UHCI_USBSTS_USBINT 0x1 // USB interrupt
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#define UHCI_USBSTS_ERRINT 0x2 // USB error interrupt
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#define UHCI_USBSTS_RESDET 0x4 // Resume Detect
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#define UHCI_USBSTS_HOSTERR 0x8 // Host System Error
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#define UHCI_USBSTS_HCPRERR 0x10// Host Controller Process error
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#define UHCI_USBSTS_HCHALT 0x20 // HCHalted
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#define UHCI_INTERRUPT_MASK 0x3F //Mask for all the interrupts
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#define UHCI_USBSTS_USBINT 0x01 // USB interrupt
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#define UHCI_USBSTS_ERRINT 0x02 // USB error interrupt
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#define UHCI_USBSTS_RESDET 0x04 // Resume Detect
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#define UHCI_USBSTS_HOSTERR 0x08 // Host System Error
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#define UHCI_USBSTS_HCPRERR 0x10 // Host Controller Process error
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#define UHCI_USBSTS_HCHALT 0x20 // HCHalted
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#define UHCI_INTERRUPT_MASK 0x3f // Mask for all the interrupts
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//USBINTR
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#define UHCI_USBINTR_CRC 0x1 // Timeout/ CRC interrupt enable
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#define UHCI_USBINTR_RESUME 0x2 // Resume interrupt enable
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#define UHCI_USBINTR_IOC 0x4 // Interrupt on complete enable
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#define UHCI_USBINTR_SHORT 0x8 // Short packet interrupt enable
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#define UHCI_USBINTR_CRC 0x01 // Timeout/ CRC interrupt enable
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#define UHCI_USBINTR_RESUME 0x02 // Resume interrupt enable
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#define UHCI_USBINTR_IOC 0x04 // Interrupt on complete enable
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#define UHCI_USBINTR_SHORT 0x08 // Short packet interrupt enable
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//PORTSC
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#define UHCI_PORTSC_CURSTAT 0x1 // Current connect status
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#define UHCI_PORTSC_STATCHA 0x2 // Current connect status change
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#define UHCI_PORTSC_ENABLED 0x4 // Port enabled/disabled
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#define UHCI_PORTSC_ENABCHA 0x8 // Change in enabled/disabled
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#define UHCI_PORTSC_LINE_0 0x10 // The status of D+ /D-
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#define UHCI_PORTSC_LINE_1 0x20
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#define UHCI_PORTSC_RESUME 0x40 // Something with the suspend state ???
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#define UHCI_PORTSC_LOWSPEED 0x100// Low speed device attached?
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#define UHCI_PORTSC_RESET 0x200// Port is in reset
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#define UHCI_PORTSC_SUSPEND 0x1000//Set port in suspend state
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#define UHCI_PORTSC_CURSTAT 0x0001 // Current connect status
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#define UHCI_PORTSC_STATCHA 0x0002 // Current connect status change
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#define UHCI_PORTSC_ENABLED 0x0004 // Port enabled/disabled
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#define UHCI_PORTSC_ENABCHA 0x0008 // Change in enabled/disabled
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#define UHCI_PORTSC_LINE_0 0x0010 // The status of D+
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#define UHCI_PORTSC_LINE_1 0x0020 // The status of D-
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#define UHCI_PORTSC_RESUME 0x0040 // Something with the suspend state ???
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#define UHCI_PORTSC_LOWSPEED 0x0100 // Low speed device attached?
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#define UHCI_PORTSC_RESET 0x0200 // Port is in reset
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#define UHCI_PORTSC_SUSPEND 0x1000 // Set port in suspend state
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#define UHCI_PORTSC_DATAMASK 0x13F5 //Mask that excludes the change bits of portsc
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#define UHCI_PORTSC_DATAMASK 0x13f5 // Mask that excludes the change bits
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/************************************************************
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* Hardware structs *
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