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* Implemented clearing port enabled change 

* Fixed build with debug output turned on
* Cleaned up the uhci_hardware header a bit

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@19861 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz 2007-01-18 22:28:34 +00:00
parent c4cce7277c
commit a3dfc2743a
2 changed files with 42 additions and 40 deletions
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6
src/add-ons/kernel/busses/usb/uhci.cpp
View File

@ -280,8 +280,6 @@ Queue::PrintToStream()
dprintf("USB UHCI Queue:\n");
dprintf("link phy: 0x%08lx; link type: %s; terminate: %s\n", fQueueHead->link_phy & 0xfff0, fQueueHead->link_phy & 0x0002 ? "QH" : "TD", fQueueHead->link_phy & 0x0001 ? "yes" : "no");
dprintf("elem phy: 0x%08lx; elem type: %s; terminate: %s\n", fQueueHead->element_phy & 0xfff0, fQueueHead->element_phy & 0x0002 ? "QH" : "TD", fQueueHead->element_phy & 0x0001 ? "yes" : "no");
dprintf("elements:\n");
print_descriptor_chain(fQueueTop);
#endif
}
@ -990,6 +988,10 @@ UHCI::ClearPortFeature(uint8 index, uint16 feature)
case C_PORT_CONNECTION:
WriteReg16(portRegister, portStatus | UHCI_PORTSC_STATCHA);
return B_OK;
case C_PORT_ENABLE:
WriteReg16(portRegister, portStatus | UHCI_PORTSC_ENABCHA);
return B_OK;
}
return B_BAD_VALUE;

76
src/add-ons/kernel/busses/usb/uhci_hardware.h
View File

@ -23,53 +23,53 @@
#define PCI_LEGSUP_USBPIRQDEN 0x2000
// Registers
#define UHCI_USBCMD 0x0 // USB Command - word - R/W
#define UHCI_USBSTS 0x2 // USB Status - word - R/WC
#define UHCI_USBINTR 0x4 // USB Interrupt Enable - word - R/W
#define UHCI_FRNUM 0x6 // Frame number - word - R/W**
#define UHCI_FRBASEADD 0x08 // Frame List BAse Address - dword - R/W
#define UHCI_SOFMOD 0xC // Start of Frame Modify - byte - R/W
#define UHCI_PORTSC1 0x10 // Port 1 Status/Control - word - R/WC**
#define UHCI_PORTSC2 0x12 // Port 2 Status/Control - word - R/WC**
#define UHCI_USBCMD 0x00 // USB Command - word - R/W
#define UHCI_USBSTS 0x02 // USB Status - word - R/WC
#define UHCI_USBINTR 0x04 // USB Interrupt Enable - word - R/W
#define UHCI_FRNUM 0x06 // Frame number - word - R/W**
#define UHCI_FRBASEADD 0x08 // Frame List BAse Address - dword - R/W
#define UHCI_SOFMOD 0x0c // Start of Frame Modify - byte - R/W
#define UHCI_PORTSC1 0x10 // Port 1 Status/Control - word - R/WC**
#define UHCI_PORTSC2 0x12 // Port 2 Status/Control - word - R/WC**
// USBCMD
#define UHCI_USBCMD_RS 0x1 // Run/Stop
#define UHCI_USBCMD_HCRESET 0x2 // Host Controller Reset
#define UHCI_USBCMD_GRESET 0x4 // Global Reset
#define UHCI_USBCMD_EGSM 0x8 // Enter Global Suspensd mode
#define UHCI_USBCMD_FGR 0x10 // Force Global resume
#define UHCI_USBCMD_SWDBG 0x20 // Software Debug
#define UHCI_USBCMD_CF 0x40 // Configure Flag
#define UHCI_USBCMD_MAXP 0x80 // Max packet
#define UHCI_USBCMD_RS 0x01 // Run/Stop
#define UHCI_USBCMD_HCRESET 0x02 // Host Controller Reset
#define UHCI_USBCMD_GRESET 0x04 // Global Reset
#define UHCI_USBCMD_EGSM 0x08 // Enter Global Suspensd mode
#define UHCI_USBCMD_FGR 0x10 // Force Global resume
#define UHCI_USBCMD_SWDBG 0x20 // Software Debug
#define UHCI_USBCMD_CF 0x40 // Configure Flag
#define UHCI_USBCMD_MAXP 0x80 // Max packet
//USBSTS
#define UHCI_USBSTS_USBINT 0x1 // USB interrupt
#define UHCI_USBSTS_ERRINT 0x2 // USB error interrupt
#define UHCI_USBSTS_RESDET 0x4 // Resume Detect
#define UHCI_USBSTS_HOSTERR 0x8 // Host System Error
#define UHCI_USBSTS_HCPRERR 0x10// Host Controller Process error
#define UHCI_USBSTS_HCHALT 0x20 // HCHalted
#define UHCI_INTERRUPT_MASK 0x3F //Mask for all the interrupts
#define UHCI_USBSTS_USBINT 0x01 // USB interrupt
#define UHCI_USBSTS_ERRINT 0x02 // USB error interrupt
#define UHCI_USBSTS_RESDET 0x04 // Resume Detect
#define UHCI_USBSTS_HOSTERR 0x08 // Host System Error
#define UHCI_USBSTS_HCPRERR 0x10 // Host Controller Process error
#define UHCI_USBSTS_HCHALT 0x20 // HCHalted
#define UHCI_INTERRUPT_MASK 0x3f // Mask for all the interrupts
//USBINTR
#define UHCI_USBINTR_CRC 0x1 // Timeout/ CRC interrupt enable
#define UHCI_USBINTR_RESUME 0x2 // Resume interrupt enable
#define UHCI_USBINTR_IOC 0x4 // Interrupt on complete enable
#define UHCI_USBINTR_SHORT 0x8 // Short packet interrupt enable
#define UHCI_USBINTR_CRC 0x01 // Timeout/ CRC interrupt enable
#define UHCI_USBINTR_RESUME 0x02 // Resume interrupt enable
#define UHCI_USBINTR_IOC 0x04 // Interrupt on complete enable
#define UHCI_USBINTR_SHORT 0x08 // Short packet interrupt enable
//PORTSC
#define UHCI_PORTSC_CURSTAT 0x1 // Current connect status
#define UHCI_PORTSC_STATCHA 0x2 // Current connect status change
#define UHCI_PORTSC_ENABLED 0x4 // Port enabled/disabled
#define UHCI_PORTSC_ENABCHA 0x8 // Change in enabled/disabled
#define UHCI_PORTSC_LINE_0 0x10 // The status of D+ /D-
#define UHCI_PORTSC_LINE_1 0x20
#define UHCI_PORTSC_RESUME 0x40 // Something with the suspend state ???
#define UHCI_PORTSC_LOWSPEED 0x100// Low speed device attached?
#define UHCI_PORTSC_RESET 0x200// Port is in reset
#define UHCI_PORTSC_SUSPEND 0x1000//Set port in suspend state
#define UHCI_PORTSC_CURSTAT 0x0001 // Current connect status
#define UHCI_PORTSC_STATCHA 0x0002 // Current connect status change
#define UHCI_PORTSC_ENABLED 0x0004 // Port enabled/disabled
#define UHCI_PORTSC_ENABCHA 0x0008 // Change in enabled/disabled
#define UHCI_PORTSC_LINE_0 0x0010 // The status of D+
#define UHCI_PORTSC_LINE_1 0x0020 // The status of D-
#define UHCI_PORTSC_RESUME 0x0040 // Something with the suspend state ???
#define UHCI_PORTSC_LOWSPEED 0x0100 // Low speed device attached?
#define UHCI_PORTSC_RESET 0x0200 // Port is in reset
#define UHCI_PORTSC_SUSPEND 0x1000 // Set port in suspend state
#define UHCI_PORTSC_DATAMASK 0x13F5 //Mask that excludes the change bits of portsc
#define UHCI_PORTSC_DATAMASK 0x13f5 // Mask that excludes the change bits
/************************************************************
* Hardware structs *