added some DFP programming stuff
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@6933 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -1,6 +1,6 @@
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/* CTRC functionality */
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/* Author:
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Rudolf Cornelissen 11/2002-1/2004
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Rudolf Cornelissen 11/2002-3/2004
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*/
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#define MODULE_BIT 0x00040000
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@ -127,10 +127,12 @@ status_t nv_crtc_set_timing(display_mode target)
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/* enable access to CRTC1 on dualhead cards */
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if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
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//fixme: flatpanel 'don't touch' update needed for 'Go' cards!?!
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if (true)
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/* Note for laptop and DVI flatpanels:
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* CRTC timing has a seperate set of registers from flatpanel timing.
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* The flatpanel timing registers have scaling registers that are used to match
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* these two modelines. */
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{
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LOG(4,("CRTC: CRT only mode, setting full timing...\n"));
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LOG(4,("CRTC: Setting full timing...\n"));
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/* log the mode that will be set */
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LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));
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@ -239,6 +241,24 @@ status_t nv_crtc_set_timing(display_mode target)
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/* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
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CRTCW(INTERLACE, 0xff);
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/* setup flatpanel scaling if needed */
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//fixme: unlock registers and/or setup chksum?!? doesn't work yet :-/
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if (si->ps.tmds1_active)
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{
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uint32 iscale_x, iscale_y;
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//fixme: checkout upscaling and aspect!!!
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iscale_x = ((4096 * target.timing.h_display) / si->ps.panel1_width);
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iscale_y = ((4096 * target.timing.v_display) / si->ps.panel1_height);
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DACW(FP_DEBUG3, (iscale_x & 0x00001fff) | ((iscale_y & 0x00001fff) << 16));
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/* limit last fetched line if vertical scaling is done */
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if (iscale_y != 4096)
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DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));
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else
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DACW(FP_DEBUG2, 0x00000000);
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}
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return B_OK;
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}
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@ -1,6 +1,6 @@
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/* second CTRC functionality for GeForce cards */
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/* Author:
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Rudolf Cornelissen 11/2002-1/2004
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Rudolf Cornelissen 11/2002-3/2004
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*/
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#define MODULE_BIT 0x00020000
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@ -112,10 +112,12 @@ status_t nv_crtc2_set_timing(display_mode target)
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/* enable access to CRTC2 */
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CRTC2W(OWNER, 0x03);
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//fixme: flatpanel 'don't touch' update needed for 'Go' cards!?!
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if (true)
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/* Note for laptop and DVI flatpanels:
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* CRTC timing has a seperate set of registers from flatpanel timing.
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* The flatpanel timing registers have scaling registers that are used to match
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* these two modelines. */
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{
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LOG(4,("CRTC2: CRT only mode, setting full timing...\n"));
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LOG(4,("CRTC2: Setting full timing...\n"));
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/* log the mode that will be set */
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LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));
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@ -221,6 +223,24 @@ status_t nv_crtc2_set_timing(display_mode target)
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/* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
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CRTC2W(INTERLACE, 0xff);
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/* setup flatpanel scaling if needed */
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//fixme: unlock registers and/or setup chksum?!? doesn't work yet :-/
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if (si->ps.tmds2_active)
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{
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uint32 iscale_x, iscale_y;
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//fixme: checkout upscaling and aspect!!!
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iscale_x = ((4096 * target.timing.h_display) / si->ps.panel1_width);
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iscale_y = ((4096 * target.timing.v_display) / si->ps.panel1_height);
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DAC2W(FP_DEBUG3, (iscale_x & 0x00001fff) | ((iscale_y & 0x00001fff) << 16));
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/* limit last fetched line if vertical scaling is done */
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if (iscale_y != 4096)
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DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));
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else
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DAC2W(FP_DEBUG2, 0x00000000);
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}
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return B_OK;
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}
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@ -1,6 +1,6 @@
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/* program the DAC */
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/* Author:
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Rudolf Cornelissen 12/2003-2/2004
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Rudolf Cornelissen 12/2003-3/2004
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*/
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#define MODULE_BIT 0x00010000
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@ -144,6 +144,20 @@ status_t nv_dac_set_pix_pll(display_mode target)
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float pix_setting, req_pclk;
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status_t result;
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/* fix a DVI or laptop flatpanel to 60Hz refresh! */
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/* Note:
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* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
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if (si->ps.tmds1_active)
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{
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LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n"));
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/* readout the panel's modeline to determine the needed pixelclock */
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target.timing.pixel_clock = (
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((DACR(FP_HTOTAL) & 0x0000ffff) + 1) *
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((DACR(FP_VTOTAL) & 0x0000ffff) + 1) *
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60) / 1000;
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}
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req_pclk = (target.timing.pixel_clock)/1000.0;
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LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));
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@ -1,6 +1,6 @@
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/* program the secondary DAC */
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/* Author:
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Rudolf Cornelissen 12/2003-2/2004
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Rudolf Cornelissen 12/2003-3/2004
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*/
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#define MODULE_BIT 0x00001000
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@ -145,6 +145,20 @@ status_t nv_dac2_set_pix_pll(display_mode target)
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float pix_setting, req_pclk;
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status_t result;
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/* fix a DVI or laptop flatpanel to 60Hz refresh! */
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/* Note:
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* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
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if (si->ps.tmds2_active)
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{
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LOG(4,("DAC2: Fixing DFP refresh to 60Hz!\n"));
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/* readout the panel's modeline to determine the needed pixelclock */
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target.timing.pixel_clock = (
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((DAC2R(FP_HTOTAL) & 0x0000ffff) + 1) *
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((DAC2R(FP_VTOTAL) & 0x0000ffff) + 1) *
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60) / 1000;
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}
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req_pclk = (target.timing.pixel_clock)/1000.0;
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LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk));
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@ -252,10 +252,12 @@ static void detect_panels()
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/* detect if the BIOS enabled LCD's (internal panels or DVI) or TVout */
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{
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/* both external TMDS transmitters (used for LCD/DVI) and external TVencoders
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* use the CRTC's in slaved mode. */
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* can use the CRTC's in slaved mode. */
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/* Note:
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* It looks like GeForceFX cards have on die TMDS encoders that nolonger
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* require the CRTC to be slaved. */
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* Apparantly a panel on CRTC1 uses the CRTC in slaved mode, while a panel
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* on CRTC2 uses the CRTC in master mode. */
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/* Note also:
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* DFP's are programmed with standard VESA modelines by the card's BIOS! */
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bool slaved_for_dev1 = false, slaved_for_dev2 = false;
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bool tvout1 = false, tvout2 = false;
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