Aren
/
haiku
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

added some DFP programming stuff 

git-svn-id: file:///srv/svn/repos/haiku/trunk/current@6933 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-03-08 20:34:40 +00:00
parent 349b01808e
commit a16d55dd54
5 changed files with 83 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
src/add-ons/accelerants/nvidia/engine/nv_crtc.c
View File

@ -1,6 +1,6 @@
/* CTRC functionality */
/* Author:
Rudolf Cornelissen 11/2002-1/2004
Rudolf Cornelissen 11/2002-3/2004
*/
#define MODULE_BIT 0x00040000
@ -127,10 +127,12 @@ status_t nv_crtc_set_timing(display_mode target)
/* enable access to CRTC1 on dualhead cards */
if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
//fixme: flatpanel 'don't touch' update needed for 'Go' cards!?!
if (true)
/* Note for laptop and DVI flatpanels:
* CRTC timing has a seperate set of registers from flatpanel timing.
* The flatpanel timing registers have scaling registers that are used to match
* these two modelines. */
{
LOG(4,("CRTC: CRT only mode, setting full timing...\n"));
LOG(4,("CRTC: Setting full timing...\n"));
/* log the mode that will be set */
LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));
@ -239,6 +241,24 @@ status_t nv_crtc_set_timing(display_mode target)
/* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
CRTCW(INTERLACE, 0xff);
/* setup flatpanel scaling if needed */
//fixme: unlock registers and/or setup chksum?!? doesn't work yet :-/
if (si->ps.tmds1_active)
{
uint32 iscale_x, iscale_y;
//fixme: checkout upscaling and aspect!!!
iscale_x = ((4096 * target.timing.h_display) / si->ps.panel1_width);
iscale_y = ((4096 * target.timing.v_display) / si->ps.panel1_height);
DACW(FP_DEBUG3, (iscale_x & 0x00001fff) | ((iscale_y & 0x00001fff) << 16));
/* limit last fetched line if vertical scaling is done */
if (iscale_y != 4096)
DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));
else
DACW(FP_DEBUG2, 0x00000000);
}
return B_OK;
}

28
src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
View File

@ -1,6 +1,6 @@
/* second CTRC functionality for GeForce cards */
/* Author:
Rudolf Cornelissen 11/2002-1/2004
Rudolf Cornelissen 11/2002-3/2004
*/
#define MODULE_BIT 0x00020000
@ -112,10 +112,12 @@ status_t nv_crtc2_set_timing(display_mode target)
/* enable access to CRTC2 */
CRTC2W(OWNER, 0x03);
//fixme: flatpanel 'don't touch' update needed for 'Go' cards!?!
if (true)
/* Note for laptop and DVI flatpanels:
* CRTC timing has a seperate set of registers from flatpanel timing.
* The flatpanel timing registers have scaling registers that are used to match
* these two modelines. */
{
LOG(4,("CRTC2: CRT only mode, setting full timing...\n"));
LOG(4,("CRTC2: Setting full timing...\n"));
/* log the mode that will be set */
LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));
@ -221,6 +223,24 @@ status_t nv_crtc2_set_timing(display_mode target)
/* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
CRTC2W(INTERLACE, 0xff);
/* setup flatpanel scaling if needed */
//fixme: unlock registers and/or setup chksum?!? doesn't work yet :-/
if (si->ps.tmds2_active)
{
uint32 iscale_x, iscale_y;
//fixme: checkout upscaling and aspect!!!
iscale_x = ((4096 * target.timing.h_display) / si->ps.panel1_width);
iscale_y = ((4096 * target.timing.v_display) / si->ps.panel1_height);
DAC2W(FP_DEBUG3, (iscale_x & 0x00001fff) | ((iscale_y & 0x00001fff) << 16));
/* limit last fetched line if vertical scaling is done */
if (iscale_y != 4096)
DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));
else
DAC2W(FP_DEBUG2, 0x00000000);
}
return B_OK;
}

16
src/add-ons/accelerants/nvidia/engine/nv_dac.c
View File

@ -1,6 +1,6 @@
/* program the DAC */
/* Author:
Rudolf Cornelissen 12/2003-2/2004
Rudolf Cornelissen 12/2003-3/2004
*/
#define MODULE_BIT 0x00010000
@ -144,6 +144,20 @@ status_t nv_dac_set_pix_pll(display_mode target)
float pix_setting, req_pclk;
status_t result;
/* fix a DVI or laptop flatpanel to 60Hz refresh! */
/* Note:
* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
if (si->ps.tmds1_active)
{
LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n"));
/* readout the panel's modeline to determine the needed pixelclock */
target.timing.pixel_clock = (
((DACR(FP_HTOTAL) & 0x0000ffff) + 1) *
((DACR(FP_VTOTAL) & 0x0000ffff) + 1) *
60) / 1000;
}
req_pclk = (target.timing.pixel_clock)/1000.0;
LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));

16
src/add-ons/accelerants/nvidia/engine/nv_dac2.c
View File

@ -1,6 +1,6 @@
/* program the secondary DAC */
/* Author:
Rudolf Cornelissen 12/2003-2/2004
Rudolf Cornelissen 12/2003-3/2004
*/
#define MODULE_BIT 0x00001000
@ -145,6 +145,20 @@ status_t nv_dac2_set_pix_pll(display_mode target)
float pix_setting, req_pclk;
status_t result;
/* fix a DVI or laptop flatpanel to 60Hz refresh! */
/* Note:
* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
if (si->ps.tmds2_active)
{
LOG(4,("DAC2: Fixing DFP refresh to 60Hz!\n"));
/* readout the panel's modeline to determine the needed pixelclock */
target.timing.pixel_clock = (
((DAC2R(FP_HTOTAL) & 0x0000ffff) + 1) *
((DAC2R(FP_VTOTAL) & 0x0000ffff) + 1) *
60) / 1000;
}
req_pclk = (target.timing.pixel_clock)/1000.0;
LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk));

8
src/add-ons/accelerants/nvidia/engine/nv_info.c
View File

@ -252,10 +252,12 @@ static void detect_panels()
/* detect if the BIOS enabled LCD's (internal panels or DVI) or TVout */
{
/* both external TMDS transmitters (used for LCD/DVI) and external TVencoders
* use the CRTC's in slaved mode. */
* can use the CRTC's in slaved mode. */
/* Note:
* It looks like GeForceFX cards have on die TMDS encoders that nolonger
* require the CRTC to be slaved. */
* Apparantly a panel on CRTC1 uses the CRTC in slaved mode, while a panel
* on CRTC2 uses the CRTC in master mode. */
/* Note also:
* DFP's are programmed with standard VESA modelines by the card's BIOS! */
bool slaved_for_dev1 = false, slaved_for_dev2 = false;
bool tvout1 = false, tvout2 = false;