A few x86_64 debugger fixes + style fixes.
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@ -53,6 +53,7 @@ static const int32 kFromDwarfRegisters[] = {
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-1, -1, -1, -1, -1, -1, -1, -1, // SSE
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-1, -1, -1, -1, -1, -1, -1, -1 // MMX
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};
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static const int32 kFromDwarfRegisterCount = sizeof(kFromDwarfRegisters) / 4;
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@ -216,6 +217,7 @@ ArchitectureX86::InitRegisterRules(CfaContext& context) const
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return B_OK;
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}
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status_t
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ArchitectureX86::GetDwarfRegisterMaps(RegisterMap** _toDwarf,
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RegisterMap** _fromDwarf) const
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@ -46,7 +46,7 @@ static const int32 kFromDwarfRegisters[] = {
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X86_64_REGISTER_R13,
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X86_64_REGISTER_R14,
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X86_64_REGISTER_R15,
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-1
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X86_64_REGISTER_RIP,
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-1, -1, -1, -1, -1, -1, -1, -1, // xmm0-xmm7
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-1, -1, -1, -1, -1, -1, -1, -1, // xmm8-xmm15
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-1, -1, -1, -1, -1, -1, -1, -1, // st0-st7
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@ -59,6 +59,7 @@ static const int32 kFromDwarfRegisters[] = {
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X86_64_REGISTER_FS,
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X86_64_REGISTER_GS,
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};
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static const int32 kFromDwarfRegisterCount = sizeof(kFromDwarfRegisters) / 4;
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@ -157,18 +158,18 @@ ArchitectureX8664::Init()
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REGISTER_TYPE_GENERAL_PURPOSE, false);
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_AddIntegerRegister(X86_64_REGISTER_RSI, "rsi", B_UINT64_TYPE,
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REGISTER_TYPE_GENERAL_PURPOSE, true);
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REGISTER_TYPE_GENERAL_PURPOSE, false);
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_AddIntegerRegister(X86_64_REGISTER_RDI, "rdi", B_UINT64_TYPE,
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REGISTER_TYPE_GENERAL_PURPOSE, true);
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REGISTER_TYPE_GENERAL_PURPOSE, false);
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_AddIntegerRegister(X86_64_REGISTER_R8, "r8", B_UINT64_TYPE,
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REGISTER_TYPE_GENERAL_PURPOSE, true);
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REGISTER_TYPE_GENERAL_PURPOSE, false);
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_AddIntegerRegister(X86_64_REGISTER_R9, "r9", B_UINT64_TYPE,
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REGISTER_TYPE_GENERAL_PURPOSE, true);
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REGISTER_TYPE_GENERAL_PURPOSE, false);
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_AddIntegerRegister(X86_64_REGISTER_R10, "r10", B_UINT64_TYPE,
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REGISTER_TYPE_GENERAL_PURPOSE, true);
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REGISTER_TYPE_GENERAL_PURPOSE, false);
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_AddIntegerRegister(X86_64_REGISTER_R11, "r11", B_UINT64_TYPE,
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REGISTER_TYPE_GENERAL_PURPOSE, true);
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REGISTER_TYPE_GENERAL_PURPOSE, false);
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_AddIntegerRegister(X86_64_REGISTER_R12, "r12", B_UINT64_TYPE,
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REGISTER_TYPE_GENERAL_PURPOSE, true);
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_AddIntegerRegister(X86_64_REGISTER_R13, "r13", B_UINT64_TYPE,
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@ -232,15 +233,14 @@ ArchitectureX8664::InitRegisterRules(CfaContext& context) const
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if (error != B_OK)
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return error;
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// set up rule for EIP register
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// FIXME: Huh? x86_64's DWARF spec doesn't seem to include RIP in the
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// register mapping? Does this matter?
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//context.RegisterRule(fToDwarfRegisterMap->MapRegisterIndex(
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// X86_REGISTER_EIP))->SetToLocationOffset(-4);
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// set up rule for RIP register
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context.RegisterRule(fToDwarfRegisterMap->MapRegisterIndex(
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X86_64_REGISTER_RIP))->SetToLocationOffset(0);
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return B_OK;
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}
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status_t
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ArchitectureX8664::GetDwarfRegisterMaps(RegisterMap** _toDwarf,
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RegisterMap** _fromDwarf) const
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@ -592,8 +592,8 @@ DwarfImageDebugInfo::CreateFrame(Image* image,
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const Register* reg = registers + i;
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BVariant value;
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if (previousCpuState->GetRegisterValue(reg, value)) {
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TRACE_CFI(" %3s: %#" B_PRIx32 "\n", reg->Name(),
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value.ToUInt32());
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TRACE_CFI(" %3s: %#" B_PRIx64 "\n", reg->Name(),
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value.ToUInt64());
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} else
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TRACE_CFI(" %3s: undefined\n", reg->Name());
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}
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