From 9690b012b467828662af0bcc7d12cdf32f32cfcc Mon Sep 17 00:00:00 2001 From: Augustin Cavalier Date: Thu, 9 Jun 2022 18:46:09 -0400 Subject: [PATCH] libroot/musl: Import riscv64 atomic_arch.h. --- .../posix/musl/arch/riscv64/atomic_arch.h | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 src/system/libroot/posix/musl/arch/riscv64/atomic_arch.h diff --git a/src/system/libroot/posix/musl/arch/riscv64/atomic_arch.h b/src/system/libroot/posix/musl/arch/riscv64/atomic_arch.h new file mode 100644 index 0000000000..0c38258868 --- /dev/null +++ b/src/system/libroot/posix/musl/arch/riscv64/atomic_arch.h @@ -0,0 +1,38 @@ +#define a_barrier a_barrier +static inline void a_barrier() +{ + __asm__ __volatile__ ("fence rw,rw" : : : "memory"); +} + +#define a_cas a_cas +static inline int a_cas(volatile int *p, int t, int s) +{ + int old, tmp; + __asm__ __volatile__ ( + "\n1: lr.w.aqrl %0, (%2)\n" + " bne %0, %3, 1f\n" + " sc.w.aqrl %1, %4, (%2)\n" + " bnez %1, 1b\n" + "1:" + : "=&r"(old), "=&r"(tmp) + : "r"(p), "r"((long)t), "r"((long)s) + : "memory"); + return old; +} + +#define a_cas_p a_cas_p +static inline void *a_cas_p(volatile void *p, void *t, void *s) +{ + void *old; + int tmp; + __asm__ __volatile__ ( + "\n1: lr.d.aqrl %0, (%2)\n" + " bne %0, %3, 1f\n" + " sc.d.aqrl %1, %4, (%2)\n" + " bnez %1, 1b\n" + "1:" + : "=&r"(old), "=&r"(tmp) + : "r"(p), "r"(t), "r"(s) + : "memory"); + return old; +}