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radeon_hd/atombios: Sync up to latest published atombios

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Change-Id: Ic0b80da7fb88fabcc1a7e87fb055351a06aa4e68
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5528
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
This commit is contained in:
Alexander von Gluck IV 2022-08-05 12:40:59 -05:00 committed by waddlesplash
parent 8c46059114
commit 967cfb4d56
2 changed files with 108 additions and 18 deletions
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49
headers/private/graphics/radeon_hd/atombios/atombios.h
View File

@ -1990,9 +1990,9 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V6
#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct definition for 36bpp should be 2 for 36bpp(2:1)
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct definition for 30bpp should be 1 for 36bpp(5:4)
#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
@ -3258,8 +3258,8 @@ ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of t
ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
*/
@ -4302,6 +4302,7 @@ typedef struct _ATOM_DPCD_INFO
#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30
#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1
#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0
#define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2
/***********************************************************************************/
// Structure used in VRAM_UsageByFirmwareTable
@ -4371,7 +4372,7 @@ typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
// GPIO use to control PCIE_VDDC in certain SLT board
#define PCIE_VDDC_CONTROL_GPIO_PINID 56
//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable
//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable
#define PP_AC_DC_SWITCH_GPIO_PINID 60
//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
#define VDDC_VRHOT_GPIO_PINID 61
@ -4667,7 +4668,7 @@ typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
UCHAR Reserved[3]; // for potential expansion
}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
//Related definitions, all records are differnt but they have a commond header
//Related definitions, all records are different but they have a common header
typedef struct _ATOM_COMMON_RECORD_HEADER
{
UCHAR ucRecordType; //An emun to indicate the record type
@ -5180,11 +5181,11 @@ typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3
{
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2
// 14:7 <EFBFBD> PSI0_VID
// 6 <EFBFBD> PSI0_EN
// 5 <EFBFBD> PSI1
// 4:2 <EFBFBD> load line slope trim.
// 1:0 <EFBFBD> offset trim,
// 14:7 - PSI0_VID
// 6 - PSI0_EN
// 5 - PSI1
// 4:2 - load line slope trim.
// 1:0 - offset trim,
USHORT usLoadLine_PSI;
// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
@ -5638,7 +5639,9 @@ typedef struct _ATOM_SMU_INFO_V2_1
{
ATOM_COMMON_TABLE_HEADER asHeader;
UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
UCHAR ucReserved[3];
UCHAR ucSMUVer;
UCHAR ucSharePowerSource;
UCHAR ucReserved;
ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8];
}ATOM_SMU_INFO_V2_1;
@ -5657,6 +5660,22 @@ typedef struct _ATOM_GFX_INFO_V2_1
UCHAR max_texture_channel_caches;
}ATOM_GFX_INFO_V2_1;
typedef struct _ATOM_GFX_INFO_V2_3
{
ATOM_COMMON_TABLE_HEADER asHeader;
UCHAR GfxIpMinVer;
UCHAR GfxIpMajVer;
UCHAR max_shader_engines;
UCHAR max_tile_pipes;
UCHAR max_cu_per_sh;
UCHAR max_sh_per_se;
UCHAR max_backends_per_se;
UCHAR max_texture_channel_caches;
USHORT usHiLoLeakageThreshold;
USHORT usEdcDidtLoDpm7TableOffset; //offset of DPM7 low leakage table _ATOM_EDC_DIDT_TABLE_V1
USHORT usEdcDidtHiDpm7TableOffset; //offset of DPM7 high leakage table _ATOM_EDC_DIDT_TABLE_V1
USHORT usReserverd[3];
}ATOM_GFX_INFO_V2_3;
typedef struct _ATOM_POWER_SOURCE_OBJECT
{
@ -7132,7 +7151,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
#else // not __cplusplus
#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
#define GetIndexIntoMasterTable(MasterOrData, FieldName) (offsetof(ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES, FieldName) / sizeof(USHORT))
#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
@ -9190,7 +9209,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3
/*********************************************************************************/
#pragma pack() // BIOS data must use byte aligment
#pragma pack() // BIOS data must use byte alignment
#pragma pack(1)
@ -9221,7 +9240,7 @@ typedef struct _ATOM_SERVICE_INFO
#pragma pack() // BIOS data must use byte aligment
#pragma pack() // BIOS data must use byte alignment
//
// AMD ACPI Table

77
headers/private/graphics/radeon_hd/atombios/pptable.h
View File

@ -61,13 +61,17 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
#define ATOM_PP_THERMALCONTROLLER_LM96163 17
#define ATOM_PP_THERMALCONTROLLER_CISLANDS 18
#define ATOM_PP_THERMALCONTROLLER_KAVERI 19
#define ATOM_PP_THERMALCONTROLLER_ICELAND 20
#define ATOM_PP_THERMALCONTROLLER_TONGA 21
#define ATOM_PP_THERMALCONTROLLER_FIJI 22
#define ATOM_PP_THERMALCONTROLLER_POLARIS10 23
#define ATOM_PP_THERMALCONTROLLER_VEGA10 24
// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
// We probably should reserve the bit 0x80 for this use.
// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
// The driver can pick the correct internal controller based on the ASIC.
#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller
#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller
@ -96,6 +100,29 @@ typedef struct _ATOM_PPLIB_FANTABLE2
USHORT usTMax; // The max temperature
} ATOM_PPLIB_FANTABLE2;
typedef struct _ATOM_PPLIB_FANTABLE3
{
ATOM_PPLIB_FANTABLE2 basicTable2;
UCHAR ucFanControlMode;
USHORT usFanPWMMax;
USHORT usFanOutputSensitivity;
} ATOM_PPLIB_FANTABLE3;
typedef struct _ATOM_PPLIB_FANTABLE4
{
ATOM_PPLIB_FANTABLE3 basicTable3;
USHORT usFanRPMMax;
} ATOM_PPLIB_FANTABLE4;
typedef struct _ATOM_PPLIB_FANTABLE5
{
ATOM_PPLIB_FANTABLE4 basicTable4;
USHORT usFanCurrentLow;
USHORT usFanCurrentHigh;
USHORT usFanRPMLow;
USHORT usFanRPMHigh;
} ATOM_PPLIB_FANTABLE5;
typedef struct _ATOM_PPLIB_EXTENDEDHEADER
{
USHORT usSize;
@ -107,7 +134,11 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
/* points to ATOM_PPLIB_POWERTUNE_Table */
USHORT usPowerTuneTableOffset;
/* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
USHORT usSclkVddgfxTableOffset;
USHORT usVQBudgetingTableOffset; /* points to the vqBudgetingTable; */
} ATOM_PPLIB_EXTENDEDHEADER;
//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
@ -135,6 +166,10 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
#define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable.
#define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature.
#define ATOM_PP_PLATFORM_CAP_EVV 0x00800000
#define ATOM_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL 0x01000000
#define ATOM_PP_PLATFORM_LOAD_POST_PRODUCTION_FIRMWARE 0x02000000
#define ATOM_PP_PLATFORM_CAP_DISABLE_USING_ACTUAL_TEMPERATURE_FOR_POWER_CALC 0x04000000
#define ATOM_PP_PLATFORM_CAP_VRHOT_POLARITY_HIGH 0x08000000
typedef struct _ATOM_PPLIB_POWERPLAYTABLE
{
@ -413,6 +448,20 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
ULONG rsv2[2];
}ATOM_PPLIB_SUMO_CLOCK_INFO;
typedef struct _ATOM_PPLIB_KV_CLOCK_INFO {
USHORT usEngineClockLow;
UCHAR ucEngineClockHigh;
UCHAR vddcIndex;
USHORT tdpLimit;
USHORT rsv1;
ULONG rsv2[2];
} ATOM_PPLIB_KV_CLOCK_INFO;
typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
UCHAR index;
UCHAR rsv[3];
} ATOM_PPLIB_CZ_CLOCK_INFO;
typedef struct _ATOM_PPLIB_STATE_V2
{
//number of valid dpm levels in this state; Driver uses it to calculate the whole
@ -657,7 +706,8 @@ typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1
UCHAR revid;
ATOM_PowerTune_Table power_tune_table;
USHORT usMaximumPowerDeliveryLimit;
USHORT usReserve[7];
USHORT usTjMax;
USHORT usReserve[6];
} ATOM_PPLIB_POWERTUNE_Table_V1;
#define ATOM_PPM_A_A 1
@ -677,6 +727,27 @@ typedef struct _ATOM_PPLIB_PPM_Table
ULONG ulTjmax;
} ATOM_PPLIB_PPM_Table;
#define VQ_DisplayConfig_NoneAWD 1
#define VQ_DisplayConfig_AWD 2
typedef struct ATOM_PPLIB_VQ_Budgeting_Record{
ULONG ulDeviceID;
ULONG ulSustainableSOCPowerLimitLow; /* in mW */
ULONG ulSustainableSOCPowerLimitHigh; /* in mW */
ULONG ulDClk;
ULONG ulEClk;
ULONG ulDispSclk;
UCHAR ucDispConfig;
} ATOM_PPLIB_VQ_Budgeting_Record;
typedef struct ATOM_PPLIB_VQ_Budgeting_Table {
UCHAR revid;
UCHAR numEntries;
ATOM_PPLIB_VQ_Budgeting_Record entries[1];
} ATOM_PPLIB_VQ_Budgeting_Table;
#pragma pack()
#endif