diff --git a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
index 56e5d46985..c21c6c30ca 100644
--- a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
+++ b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
@@ -64,13 +64,13 @@ FDITransmitter::Enable()
 void
 FDITransmitter::Disable()
 {
-    CALLED();
-    uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
-    uint32 value = read32(targetRegister);
+	CALLED();
+	uint32 targetRegister = fRegisterBase + PCH_FDI_TX_CONTROL;
+	uint32 value = read32(targetRegister);
 
-    write32(targetRegister, value & ~FDI_TX_ENABLE);
-    read32(targetRegister);
-    spin(150);
+	write32(targetRegister, value & ~FDI_TX_ENABLE);
+	read32(targetRegister);
+	spin(150);
 }
 
 
@@ -149,13 +149,13 @@ FDIReceiver::Enable()
 void
 FDIReceiver::Disable()
 {
-    CALLED();
-    uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
-    uint32 value = read32(targetRegister);
+	CALLED();
+	uint32 targetRegister = fRegisterBase + PCH_FDI_RX_CONTROL;
+	uint32 value = read32(targetRegister);
 
-    write32(targetRegister, value & ~FDI_RX_ENABLE);
-    read32(targetRegister);
-    spin(150);
+	write32(targetRegister, value & ~FDI_RX_ENABLE);
+	read32(targetRegister);
+	spin(150);
 }
 
 
@@ -237,7 +237,7 @@ FDILink::Train(display_mode* target)
 		default:
 			bitsPerPixel = 8;
 			break;
-    }
+	}
 
 	// Khz / 10. ( each output octet encoded as 10 bits.
 	uint32 linkBandwidth = gInfo->shared_info->fdi_link_frequency * 1000 / 10;
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp
index ece8cfd4d9..7b91200113 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -105,14 +105,14 @@ Port::HasEDID()
 status_t
 Port::SetPipe(Pipe* pipe)
 {
-    CALLED();
+	CALLED();
 
 	if (pipe == NULL) {
 		ERROR("%s: Invalid pipe provided!\n", __func__);
 		return B_ERROR;
 	}
 
-    uint32 portRegister = _PortRegister();
+	uint32 portRegister = _PortRegister();
 	if (portRegister == 0) {
 		ERROR("%s: Invalid PortRegister ((0x%" B_PRIx32 ") for %s\n", __func__,
 			portRegister, PortName());
@@ -128,7 +128,7 @@ Port::SetPipe(Pipe* pipe)
 	TRACE("%s: Assigning %s (0x%" B_PRIx32 ") to pipe %s\n", __func__,
 		PortName(), portRegister, (pipe->Index() == INTEL_PIPE_A) ? "A" : "B");
 
-    uint32 portState = read32(portRegister);
+	uint32 portState = read32(portRegister);
 
 	if (pipe->Index() == INTEL_PIPE_A)
 		write32(portRegister, portState & ~DISPLAY_MONITOR_PIPE_B);
@@ -422,7 +422,7 @@ LVDSPort::_PortRegister()
 status_t
 LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 {
-    CALLED();
+	CALLED();
 	if (target == NULL) {
 		ERROR("%s: Invalid target mode passed!\n", __func__);
 		return B_ERROR;
@@ -955,8 +955,8 @@ EmbeddedDisplayPort::IsConnected()
 
 DigitalDisplayInterface::DigitalDisplayInterface(port_index index,
 		const char* baseName)
-    :
-    Port(index, baseName)
+	:
+	Port(index, baseName)
 {
 	// As of Haswell, Intel decided to change eDP ports to a "DDI" bus...
 	// on a dare because the hardware engineers were drunk one night.
diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp
index 0c2f9a866a..3c4e05d337 100644
--- a/src/add-ons/accelerants/intel_extreme/mode.cpp
+++ b/src/add-ons/accelerants/intel_extreme/mode.cpp
@@ -415,9 +415,10 @@ intel_propose_display_mode(display_mode* target, const display_mode* low,
 		// TODO: improve this, ie. adapt pixel clock to allowed values!!!
 
 		if (target->virtual_width != mode->virtual_width
-		        || target->virtual_height != mode->virtual_height
-		        || target->space != mode->space)
-		        continue;
+			|| target->virtual_height != mode->virtual_height
+			|| target->space != mode->space) {
+			continue;
+		}
 
 		*target = *mode;
 		return B_OK;
diff --git a/src/add-ons/accelerants/intel_extreme/pll.h b/src/add-ons/accelerants/intel_extreme/pll.h
index bc243a537f..706f97b6c1 100644
--- a/src/add-ons/accelerants/intel_extreme/pll.h
+++ b/src/add-ons/accelerants/intel_extreme/pll.h
@@ -14,22 +14,22 @@
 
 
 struct pll_divisors {
-    uint32  post;
-    uint32  post1;
-    uint32  post2;
-    bool    post2_high;
-    uint32  n;
-    uint32  m;
-    uint32  m1;
-    uint32  m2;
+	uint32  post;
+	uint32  post1;
+	uint32  post2;
+	bool    post2_high;
+	uint32  n;
+	uint32  m;
+	uint32  m1;
+	uint32  m2;
 };
 
 struct pll_limits {
-    pll_divisors    min;
-    pll_divisors    max;
-    uint32          min_post2_frequency;
-    uint32          min_vco;
-    uint32          max_vco;
+	pll_divisors    min;
+	pll_divisors    max;
+	uint32          min_post2_frequency;
+	uint32          min_vco;
+	uint32          max_vco;
 };
 
 
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
index 9c33a9f8e1..33eb884324 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
@@ -52,7 +52,7 @@ intel_en_gating(intel_info &info)
 		uint32 gateValue = (1L << 28) | (1L << 3) | (1L << 2);
 		if ((info.device_type.type & INTEL_TYPE_MOBILE) == INTEL_TYPE_MOBILE) {
 			TRACE("G4x mobile clock gating\n");
-		    gateValue |= 1L << 18;
+			gateValue |= 1L << 18;
 		}
 		write32(info, 0x6200, gateValue);
 	} else {