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added two new nv.settings (TWEAK options): gpu_clk and ram_clk. These options if enabled overrule your gfx card GPU and RAM speeds set by their BIOS (or set via coldstarting the card with the driver). note: overclocking might destroy your computer! Use with extreme caution. These options were added because it offers application developers a means to find bottlenecks (use underclocking), and it offers gamers the option to overclock for max fps. Disabled by default. 'Undocumented'.

Browse Source 
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16787 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2006-03-14 16:32:43 +00:00
parent 821d63fe0a
commit 912ea16e29
4 changed files with 43 additions and 6 deletions
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6
src/add-ons/accelerants/nvidia/InitAccelerant.c
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@ -4,7 +4,7 @@
Other authors:
Mark Watson,
Rudolf Cornelissen 10/2002-2/2006.
Rudolf Cornelissen 10/2002-3/2006.
*/
#define MODULE_BIT 0x00800000
@ -42,8 +42,8 @@ static status_t init_common(int the_fd) {
si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.switchhead, si->settings.force_pci));
LOG(4,("init_common: dumprom %d, unhide_fw %d, pgm_panel %d, dma_acc %d, tv_output %d, vga_on_tv %d\n",
si->settings.dumprom, si->settings.unhide_fw, si->settings.pgm_panel, si->settings.dma_acc, si->settings.tv_output, si->settings.vga_on_tv));
LOG(4,("init_common: force_sync %d\n",
si->settings.force_sync));
LOG(4,("init_common: force_sync %d, gpu_clk %dMhz, ram_clk %dMhz\n",
si->settings.force_sync, si->settings.gpu_clk, si->settings.ram_clk));
/*Check for R4.5.0 and if it is running, use work around*/
{

20
src/add-ons/accelerants/nvidia/engine/nv_general.c
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@ -1,7 +1,7 @@
/* Authors:
Mark Watson 12/1999,
Apsed,
Rudolf Cornelissen 10/2002-2/2006
Rudolf Cornelissen 10/2002-3/2006
*/
#define MODULE_BIT 0x00008000
@ -91,7 +91,7 @@ status_t nv_general_powerup()
{
status_t status;
LOG(1,("POWERUP: Haiku nVidia Accelerant 0.73 running.\n"));
LOG(1,("POWERUP: Haiku nVidia Accelerant 0.74 running.\n"));
/* log VBLANK INT usability status */
if (si->ps.int_assigned)
@ -1545,6 +1545,22 @@ static status_t nv_general_bios_to_powergraphics()
NV_REG32(NV32_PFB_CLS_PAGE2) &= 0xffff7fff;
}
/* tweak card GPU-core and RAM speeds if requested (hoping we'll survive)... */
if (si->settings.gpu_clk)
{
LOG(2,("INIT: tweaking GPU clock!\n"));
set_pll(NV32_COREPLL, si->settings.gpu_clk);
snooze(1000);
}
if (si->settings.ram_clk)
{
LOG(2,("INIT: tweaking cardRAM clock!\n"));
set_pll(NV32_MEMPLL, si->settings.ram_clk);
snooze(1000);
}
/* setup AGP:
* Note:
* This may only be done when no transfers are in progress on the bus, so now

22
src/add-ons/accelerants/nvidia/engine/nv_info.c
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@ -1,7 +1,7 @@
/* Read initialisation information from card */
/* some bits are hacks, where PINS is not known */
/* Author:
Rudolf Cornelissen 7/2003-1/2006
Rudolf Cornelissen 7/2003-3/2006
*/
#define MODULE_BIT 0x00002000
@ -2060,6 +2060,26 @@ static status_t translate_ISA_PCI(uint32* reg)
return B_OK;
}
void set_pll(uint32 reg, uint32 req_clk)
{
uint32 data;
float calced_clk;
uint8 m, n, p;
nv_dac_sys_pll_find(req_clk, &calced_clk, &m, &n, &p, 0);
/* programming the PLL needs to be done in steps! (confirmed NV28) */
data = NV_REG32(reg);
NV_REG32(reg) = ((data & 0xffff0000) | (n << 8) | m);
data = NV_REG32(reg);
NV_REG32(reg) = ((p << 16) | (n << 8) | m);
//fixme?
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */
/* program 2nd set N and M scalers if they exist (b31=1 enables them) */
if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);
log_pll(reg, req_clk);
}
/* doing general fail-safe default setup here */
static status_t nv_crtc_setup_fifo()
{

1
src/add-ons/accelerants/nvidia/engine/nv_proto.h
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@ -37,6 +37,7 @@ status_t i2c_init(void);
/* card info functions */
status_t parse_pins(void);
void set_pll(uint32 reg, uint32 clk);
void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2);
void fake_panel_start(void);
void set_specs(void);