added several (temporary) registerdefines for VIA.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13670 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -173,8 +173,9 @@ typedef struct {
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/* card info - information gathered from PINS (and other sources) */
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enum
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{ // card_type in order of date of NV chip design
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NV04 = 0,
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{ // card_type in order of date of VIA chip design
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CLE266 = 0,
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NV04,
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NV05,
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NV05M64,
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NV06,
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@ -201,8 +202,9 @@ typedef struct {
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NV45
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};
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enum
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{ // card_arch in order of date of NV chip design
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NV04A = 0,
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{ // card_arch in order of date of VIA chip design
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UNI_PRO = 0,
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NV04A,
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NV10A,
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NV20A,
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NV30A,
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@ -414,9 +414,6 @@
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#define RG8_MISCW 0x000c03c2
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#define RG8_MISCR 0x000c03cc
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#define RG8_VSE2 0x000c03c3
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#define RG8_SEQIND 0x000c03c4
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#define RG16_SEQIND 0x000c03c4
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#define RG8_SEQDAT 0x000c03c5
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#define RG8_GRPHIND 0x000c03ce
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#define RG16_GRPHIND 0x000c03ce
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#define RG8_GRPHDAT 0x000c03cf
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@ -445,6 +442,9 @@
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#define RG8_ATTRDATW 0x006013c0
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#define RG8_ATTRDATR 0x006013c1
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//new via
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#define RG8_SEQIND 0x000083c4
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#define RG16_SEQIND 0x000083c4
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#define RG8_SEQDAT 0x000083c5
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#define RG8_CRTCIND 0x000083d4
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#define RG16_CRTCIND 0x000083d4
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#define RG8_CRTCDAT 0x000083d5
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@ -548,7 +548,8 @@
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#define ENDAC2_FP_DEBUG2 0x00682888
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#define ENDAC2_FP_DEBUG3 0x0068288c
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/* Nvidia CRTC indexed registers */
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//new via
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/* VIA CRTC indexed registers */
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/* VGA standard registers: */
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#define ENCRTCX_HTOTAL 0x00
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#define ENCRTCX_HDISPE 0x01
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@ -561,13 +562,9 @@
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#define ENCRTCX_PRROWSCN 0x08
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#define ENCRTCX_MAXSCLIN 0x09
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#define ENCRTCX_VGACURCTRL 0x0a
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//new via
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#define ENCRTCX_FBSTADDH 0x0c
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#define ENCRTCX_FBSTADDL 0x0d
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#define ENCRTCX_PITCHL 0x13
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/* VIA specific registers: */
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#define ENCRTCX_FBSTADDE 0x34
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//end via
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#define ENCRTCX_VSYNCS 0x10
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#define ENCRTCX_VSYNCE 0x11
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#define ENCRTCX_VDISPE 0x12
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@ -575,6 +572,14 @@
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#define ENCRTCX_VBLANKE 0x16
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#define ENCRTCX_MODECTL 0x17
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#define ENCRTCX_LINECOMP 0x18
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/* VIA specific registers: */
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#define ENCRTCX_0x32 0x32
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#define ENCRTCX_0x33 0x33
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#define ENCRTCX_FBSTADDE 0x34
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#define ENCRTCX_0x35 0x35
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#define ENCRTCX_0x36 0x36 //b6,7 = DPMS, 00 = on, 11=off
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#define ENCRTCX_0x3b 0x3b //TVtype jumper: b1=1 = PAL, else NTSC
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//end via
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/* Nvidia specific registers: */
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#define ENCRTCX_REPAINT0 0x19
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#define ENCRTCX_REPAINT1 0x1a
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@ -607,11 +612,44 @@
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#define ENATBX_HORPIXPAN 0x13
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#define ENATBX_COLSEL 0x14
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/* Nvidia SEQUENCER indexed registers */
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//new via
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/* VIA SEQUENCER indexed registers */
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/* VGA standard registers: */
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#define ENSEQX_RESET 0x00
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#define ENSEQX_CLKMODE 0x01
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#define ENSEQX_MEMMODE 0x04
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/* VIA specific registers: */
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#define ENSEQX_LOCK 0x10
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#define ENSEQX_0x14 0x14
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#define ENSEQX_0x15 0x15
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#define ENSEQX_0x16 0x16 //Mclk PLL
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#define ENSEQX_0x17 0x17 //Mclk PLL
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#define ENSEQX_0x18 0x18 //Mclk PLL
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#define ENSEQX_0x19 0x19
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#define ENSEQX_0x1a 0x1a
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#define ENSEQX_0x1b 0x1b
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#define ENSEQX_0x1c 0x1c
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#define ENSEQX_0x1d 0x1d
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#define ENSEQX_0x1e 0x1e
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#define ENSEQX_0x1f 0x1f
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#define ENSEQX_0x22 0x22
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#define ENSEQX_0x23 0x23
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#define ENSEQX_0x24 0x24
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#define ENSEQX_0x25 0x25
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#define ENSEQX_0x26 0x26 // ddc
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#define ENSEQX_0x27 0x27
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#define ENSEQX_0x28 0x28
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#define ENSEQX_0x29 0x29
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#define ENSEQX_0x2a 0x2a
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#define ENSEQX_0x2b 0x2b
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#define ENSEQX_0x2e 0x2e
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#define ENSEQX_MSIZE_CLE266 0x34
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#define ENSEQX_MSIZE_OTHER 0x39
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#define ENSEQX_0x44 0x44
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#define ENSEQX_0x45 0x45
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#define ENSEQX_0x46 0x46
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#define ENSEQX_0x47 0x47
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//end new via.
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/* Nvidia GRAPHICS indexed registers */
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/* VGA standard registers: */
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