x86[_64]: Add CPU topology detection for Intel processors
This commit is contained in:
Pawel Dziepak
parent
4110b730db
commit
8ec897323e
@ -31,6 +31,15 @@ namespace BKernel {
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using BKernel::Thread;
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typedef enum cpu_topology_level {
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CPU_TOPOLOGY_SMT,
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CPU_TOPOLOGY_CORE,
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CPU_TOPOLOGY_PACKAGE,
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//
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CPU_TOPOLOGY_LEVELS
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} cpu_topology_level;
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/* CPU local data structure */
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typedef struct cpu_ent {
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@ -56,6 +65,9 @@ typedef struct cpu_ent {
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bool invoke_scheduler_if_idle;
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bool disabled;
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// CPU topology information
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int topology_id[CPU_TOPOLOGY_LEVELS];
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// arch-specific stuff
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arch_cpu_info arch;
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} cpu_ent __attribute__((aligned(64)));
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@ -34,6 +34,7 @@
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#define DUMP_FEATURE_STRING 1
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#define DUMP_CPU_TOPOLOGY 1
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/* cpu vendor info */
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@ -122,6 +123,37 @@ x86_optimized_functions gOptimizedFunctions = {
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&memset_generic_end
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};
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/* CPU topology information */
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static uint32 (*getCPUTopologyID)(int currentCPU) = NULL;
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static uint32 sHierarchyMask[CPU_TOPOLOGY_LEVELS];
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static uint32 sHierarchyShift[CPU_TOPOLOGY_LEVELS];
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// http://graphics.stanford.edu/~seander/bithacks.html
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static inline uint32
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nextPowerOf2(uint32 v)
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{
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v--;
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v |= v >> 1;
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v |= v >> 2;
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v |= v >> 4;
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v |= v >> 8;
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v |= v >> 16;
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v++;
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return v;
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}
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// http://graphics.stanford.edu/~seander/bithacks.html
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static inline uint32
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countSetBits(uint32 v)
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{
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v = v - ((v >> 1) & 0x55555555);
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v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
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return (((v + (v >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
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}
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static status_t
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acpi_shutdown(bool rebootSystem)
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@ -506,6 +538,167 @@ dump_feature_string(int currentCPU, cpu_ent* cpu)
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#endif // DUMP_FEATURE_STRING
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static uint32
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getIntelCPUInitialx2APICID(int currentCPU)
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{
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(void)currentCPU;
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cpuid_info cpuid;
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get_current_cpuid(&cpuid, 11, 0);
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return cpuid.regs.edx;
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}
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static inline status_t
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detectIntelCPUTopologyx2APIC(int maxBasicLeaf)
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{
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if (maxBasicLeaf < 11)
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return B_UNSUPPORTED;
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const int kLevelCount = CPU_TOPOLOGY_LEVELS;
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uint8 hierarchyLevels[kLevelCount];
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int currentLevel = 0;
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int levelType;
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int levelsSet = 0;
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do {
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cpuid_info cpuid;
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get_current_cpuid(&cpuid, 11, currentLevel);
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if (currentLevel == 0 && cpuid.regs.ebx == 0)
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return B_UNSUPPORTED;
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levelType = (cpuid.regs.ecx >> 8) & 0xff;
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switch (levelType) {
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case 1: // SMT
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hierarchyLevels[CPU_TOPOLOGY_SMT] = cpuid.regs.eax & 0x1f;
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levelsSet |= 1;
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break;
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case 2: // core
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hierarchyLevels[CPU_TOPOLOGY_CORE] = cpuid.regs.eax & 0x1f;
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levelsSet |= 2;
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break;
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}
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currentLevel++;
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} while(levelType != 0 && levelsSet != 3);
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getCPUTopologyID = getIntelCPUInitialx2APICID;
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for (int i = 0; i < kLevelCount; i++) {
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uint32 mask = ~uint32(0);
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if (i < kLevelCount - 1)
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mask = (1 << hierarchyLevels[i]) - 1;
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if (i > 0)
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mask &= ~sHierarchyMask[i - 1];
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sHierarchyMask[i] = mask;
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sHierarchyShift[i] = i > 0 ? hierarchyLevels[i - 1] : 0;
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}
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return B_OK;
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}
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static uint32
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getIntelCPULegacyInitialAPICID(int currentCPU)
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{
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(void)currentCPU;
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cpuid_info cpuid;
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get_current_cpuid(&cpuid, 1, 0);
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return cpuid.regs.ebx >> 24;
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}
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static inline void
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detectIntelCPUTopologyLegacy(int maxBasicLeaf)
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{
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getCPUTopologyID = getIntelCPULegacyInitialAPICID;
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cpuid_info cpuid;
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get_current_cpuid(&cpuid, 1, 0);
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int maxLogicalID = nextPowerOf2((cpuid.regs.ebx >> 16) & 0xff);
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int maxCoreID = 1;
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if (maxBasicLeaf >= 4) {
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get_current_cpuid(&cpuid, 4, 0);
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maxCoreID = nextPowerOf2((cpuid.regs.eax >> 26) + 1);
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}
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ASSERT(maxLogicalID >= maxCoreID);
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const int kMaxSMTID = maxLogicalID / maxCoreID;
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sHierarchyMask[CPU_TOPOLOGY_SMT] = kMaxSMTID - 1;
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sHierarchyShift[CPU_TOPOLOGY_SMT] = 0;
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sHierarchyMask[CPU_TOPOLOGY_CORE] = (maxCoreID - 1) * kMaxSMTID;
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sHierarchyShift[CPU_TOPOLOGY_CORE]
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= countSetBits(sHierarchyShift[CPU_TOPOLOGY_SMT]);
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const uint32 kSinglePackageMask = sHierarchyMask[CPU_TOPOLOGY_SMT]
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| sHierarchyMask[CPU_TOPOLOGY_CORE];
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sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~kSinglePackageMask;
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sHierarchyShift[CPU_TOPOLOGY_PACKAGE] = countSetBits(kSinglePackageMask);
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}
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static uint32
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getSimpleCPUTopologyID(int currentCPU)
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{
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return currentCPU;
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}
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static inline int
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getTopologyLevelID(uint32 id, cpu_topology_level level)
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{
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ASSERT(level < CPU_TOPOLOGY_LEVELS);
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return (id & sHierarchyMask[level]) >> sHierarchyShift[level];
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}
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static void
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detectCPUTopology(int currentCPU, cpu_ent* cpu, int maxBasicLeaf)
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{
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if (currentCPU == 0) {
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if (x86_check_feature(IA32_FEATURE_HTT, FEATURE_COMMON)) {
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if (cpu->arch.vendor == VENDOR_INTEL) {
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status_t result = detectIntelCPUTopologyx2APIC(maxBasicLeaf);
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if (result != B_OK)
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detectIntelCPUTopologyLegacy(maxBasicLeaf);
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return;
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}
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}
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dprintf("No CPU topology information available.\n");
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getCPUTopologyID = getSimpleCPUTopologyID;
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memset(sHierarchyMask, 0, sizeof(sHierarchyMask));
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sHierarchyMask[CPU_TOPOLOGY_PACKAGE] = ~uint32(0);
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memset(sHierarchyShift, 0, sizeof(sHierarchyShift));
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}
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ASSERT(getCPUTopologyID != NULL);
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int topologyID = getCPUTopologyID(currentCPU);
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cpu->topology_id[CPU_TOPOLOGY_SMT]
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= getTopologyLevelID(topologyID, CPU_TOPOLOGY_SMT);
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cpu->topology_id[CPU_TOPOLOGY_CORE]
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= getTopologyLevelID(topologyID, CPU_TOPOLOGY_CORE);
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cpu->topology_id[CPU_TOPOLOGY_PACKAGE]
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= getTopologyLevelID(topologyID, CPU_TOPOLOGY_PACKAGE);
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#if DUMP_CPU_TOPOLOGY
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dprintf("CPU %d: apic id %d, package %d, core %d, smt %d\n", currentCPU,
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topologyID, cpu->topology_id[CPU_TOPOLOGY_PACKAGE],
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cpu->topology_id[CPU_TOPOLOGY_CORE],
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cpu->topology_id[CPU_TOPOLOGY_SMT]);
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#endif
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}
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static void
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detect_cpu(int currentCPU)
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{
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@ -621,6 +814,8 @@ detect_cpu(int currentCPU)
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cpu->arch.feature[FEATURE_6_ECX] = cpuid.regs.ecx;
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}
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detectCPUTopology(currentCPU, cpu, maxBasicLeaf);
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#if DUMP_FEATURE_STRING
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dump_feature_string(currentCPU, cpu);
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#endif
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