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data: Drop ARM FDT dts from repo

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* We depend on FDT passed to the bootloader now
  from EFI or u-boot via fdt_addr_r now
* We leave an fdt path within the boot partition
  (for now) to allow / encourage users to optionally
  plug in their own DTB's for troubleshooting. (only
  on u-boot loader)

Change-Id: I3f2d81b60d46f388f333d5caa27aa77e6e36447d
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6081
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
Reviewed-by: X512 <danger_mail@list.ru>
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
Tested-by: Automation <automation@haiku-os.org>
This commit is contained in:
Alexander von Gluck IV 2023-02-23 09:35:50 -06:00 committed by Alex von Gluck IV
parent 4c442eb0b8
commit 8eb9f41407
41 changed files with 2 additions and 8122 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
build/jam/MainBuildRules
View File

@ -191,27 +191,6 @@ actions AssembleNasm
fi
}
rule CompileDTS target : source
{
CCDEFS on $(target) = [ FDefines $(TARGET_DEFINES_$(TARGET_PACKAGING_ARCH))
$(TARGET_DEFINES) ] ;
CC on $(target) = $(TARGET_CC_$(TARGET_PACKAGING_ARCH)) ;
MakeLocate $(target) : $(HAIKU_OUTPUT_DIR) ;
Depends $(target) : $(source) ;
CompileDTS1 $(target) : $(source) ;
}
actions CompileDTS1
{
$(CC) -E $(CCDEFS) -P -xassembler-with-cpp \
-I$(HAIKU_TOP)/src/data/dts/arch/$(TARGET_ARCH) \
-I$(HAIKU_TOP)/src/data/dts $(2) \
| dtc -O dtb -o $(1) \
-i $(HAIKU_TOP)/src/data/dts/arch/$(TARGET_ARCH) \
-i $(HAIKU_TOP)/src/data/dts ;
}
rule Ld
{
# Ld <name> : <objs> : <linkerscript> : <flags> ;

11
build/jam/images/MMCImage
View File

@ -12,7 +12,6 @@ rule BuildSDImage image : files
local mbrtool = <build>mbrtool ;
local fatshell = <build>fat_shell ;
Depends $(image) : $(files) $(TARGET_DEVICE_TREES) ;
Depends $(image) : $(HAIKU_IMAGE_NAME) ;
Depends $(image) : $(mbrtool) ;
Depends $(image) : $(fatshell) ;
@ -90,11 +89,8 @@ actions BuildUBootSDImage1
echo "cp :uEnv.txt myfs/" | ${FATFS} $(1)
# lay down FDT's
# lay down optional FDT path
echo "mkdir myfs/fdt" | ${FATFS} $(1)
for i in $(TARGET_DEVICE_TREES[1-]) ; do
echo "cp :${i} myfs/fdt/" | ${FATFS} $(1)
done
# list content
echo "ls myfs" | ${FATFS} $(1)
@ -153,11 +149,8 @@ actions BuildEfiSDImage1
done
echo "cp :uEnv.txt myfs/" | ${FATFS} $(1)
# lay down FDT's
# lay down optional FDT path
echo "mkdir myfs/fdt" | ${FATFS} $(1)
for i in $(TARGET_DEVICE_TREES[1-]) ; do
echo "cp :${i} myfs/fdt/" | ${FATFS} $(1)
done
# list content
echo "ls myfs" | ${FATFS} $(1)

5
src/data/Jamfile
View File

@ -6,8 +6,3 @@ HaikuSubInclude keyboard_layouts ;
HaikuSubInclude keymaps ;
HaikuSubInclude mime_db ;
HaikuSubInclude settings ;
# Known device trees
if $(TARGET_ARCH) = "arm" {
HaikuSubInclude dts arch $(TARGET_KERNEL_ARCH_DIR) ;
}

10
src/data/dts/arch/arm/Jamfile
View File

@ -1,10 +0,0 @@
SubDir HAIKU_TOP src data dts arch arm ;
# Our packaged device trees for this architecture
local target_boards = rpi2 boneblack verdex omap3-overo-tobi omap3-beagle-xm ;
TARGET_DEVICE_TREES = ;
for device in $(target_boards) {
CompileDTS $(device).dtb : [ FDirName $(HAIKU_TOP) src data dts arch $(TARGET_ARCH) $(device).dts ] ;
TARGET_DEVICE_TREES += $(device).dtb ;
}

349
src/data/dts/arch/arm/am335x.dtsi
View File

@ -1,349 +0,0 @@
/*-
* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&AINTC>;
SOC: am335x {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
bus-frequency = <0>;
AINTC: interrupt-controller@48200000 {
compatible = "ti,aintc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = < 0x48200000 0x1000 >;
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
};
scm@44e10000 {
compatible = "ti,scm";
reg = < 0x44e10000 0x2000 >;
};
prcm@44E00000 {
compatible = "am335x,prcm";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x44E00000 0x1300 >;
};
dmtimers@44E05000 {
compatible = "ti,am335x-dmtimer";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x44E05000 0x1000
0x44E31000 0x1000
0x48040000 0x1000
0x48042000 0x1000
0x48044000 0x1000
0x48046000 0x1000
0x48048000 0x1000
0x4804A000 0x1000 >;
interrupts = < 66 67 68 69 92 93 94 95 >;
interrupt-parent = <&AINTC>;
};
rtc: rtc@44E3E000 {
compatible = "ti,da830-rtc";
reg = <0x44E3E000 0x1000>;
interrupts = < 75 76 >;
interrupt-parent = <&AINTC>;
};
adc0: adc@44E0D000 {
compatible = "ti,adc";
reg = <0x44E0D000 0x2000>;
interrupts = < 16 >;
interrupt-parent = <&AINTC>;
};
wdt1@44E35000 {
compatible = "ti,omap3-wdt";
reg = <0x44E35000 0x1000>;
interrupts = <91>;
interrupt-parent = <&AINTC>;
};
GPIO: gpio {
#gpio-cells = <3>;
compatible = "ti,gpio";
gpio-controller;
reg =< 0x44E07000 0x1000
0x4804C000 0x1000
0x481AC000 0x1000
0x481AE000 0x1000 >;
interrupts = < 96 97 98 99 32 33 62 63 >;
interrupt-parent = <&AINTC>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart0: serial@44E09000 {
compatible = "ti,ns16550";
reg = <0x44E09000 0x1000>;
reg-shift = <2>;
interrupts = < 72 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 48000000 >;
uart-device-id = < 0 >;
};
uart1: serial@48022000 {
compatible = "ti,ns16550";
reg = <0x48022000 0x1000>;
reg-shift = <2>;
interrupts = < 73 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 48000000 >;
uart-device-id = < 1 >;
status = "disabled";
};
uart2: serial@48024000 {
compatible = "ti,ns16550";
reg = <0x48024000 0x1000>;
reg-shift = <2>;
interrupts = < 74 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 48000000 >;
uart-device-id = < 2 >;
status = "disabled";
};
uart3: serial@481a6000 {
compatible = "ti,ns16550";
reg = <0x481A6000 0x1000>;
reg-shift = <2>;
interrupts = < 44 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 48000000 >;
uart-device-id = < 3 >;
status = "disabled";
};
uart4: serial@481a8000 {
compatible = "ti,ns16550";
reg = <0x481A8000 0x1000>;
reg-shift = <2>;
interrupts = < 45 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 48000000 >;
uart-device-id = < 4 >;
status = "disabled";
};
uart5: serial@481aa000 {
compatible = "ti,ns16550";
reg = <0x481AA000 0x1000>;
reg-shift = <2>;
interrupts = < 46 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 48000000 >;
uart-device-id = < 5 >;
status = "disabled";
};
edma3@49000000 {
compatible = "ti,edma3";
reg =< 0x49000000 0x100000 /* Channel Controller Regs */
0x49800000 0x100000 /* Transfer Controller 0 Regs */
0x49900000 0x100000 /* Transfer Controller 1 Regs */
0x49a00000 0x100000 >; /* Transfer Controller 2 Regs */
interrupts = <12 13 14>;
interrupt-parent = <&AINTC>;
};
mmchs0@48060000 {
compatible = "ti,omap3-hsmmc", "ti,mmchs";
reg =<0x48060000 0x1000 >;
interrupts = <64>;
interrupt-parent = <&AINTC>;
mmchs-device-id = <0>;
mmchs-wp-gpio-pin = <0xffffffff>;
ti,dual-volt;
};
mmchs1@481D8000 {
compatible = "ti,omap3-hsmmc", "ti,mmchs";
reg =<0x481D8000 0x1000 >;
interrupts = <28>;
interrupt-parent = <&AINTC>;
mmchs-device-id = <1>;
mmchs-wp-gpio-pin = <0xffffffff>;
status = "disabled";
};
enet0: ethernet@4A100000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ti,cpsw";
reg = <0x4A100000 0x4000>;
interrupts = <40 41 42 43>;
interrupt-parent = <&AINTC>;
phy-handle = <&phy0>;
mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,cpsw-mdio";
phy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};
i2c0: i2c@44e0b000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,i2c";
reg =< 0x44e0b000 0x1000 >;
interrupts = <70>;
interrupt-parent = <&AINTC>;
i2c-device-id = <0>;
};
i2c1: i2c@4802a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,i2c";
reg =< 0x4802a000 0x1000 >;
interrupts = <71>;
interrupt-parent = <&AINTC>;
i2c-device-id = <1>;
};
i2c2: i2c@4819c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,i2c";
reg =< 0x4819c000 0x1000 >;
interrupts = <30>;
interrupt-parent = <&AINTC>;
i2c-device-id = <2>;
};
pwm@48300000 {
compatible = "ti,am335x-pwm";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x48300000 0x100 /* PWMSS0 */
0x48300100 0x80 /* eCAP0 */
0x48300180 0x80 /* eQEP0 */
0x48300200 0x60 /* ePWM0 */
>;
interrupts = <86 58>; /* ePWM0INT, ePWM0_TZINT */
interrupt-parent = <&AINTC>;
pwm-device-id = <0>;
};
pwm@48302000 {
compatible = "ti,am335x-pwm";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x48302000 0x100 /* PWMSS1 */
0x48302100 0x80 /* eCAP1 */
0x48302180 0x80 /* eQEP1 */
0x48302200 0x60 /* ePWM1 */
>;
interrupts = <87 59>; /* ePWM1INT, ePWM1_TZINT */
interrupt-parent = <&AINTC>;
pwm-device-id = <1>;
};
pwm@48304000 {
compatible = "ti,am335x-pwm";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x48304000 0x100 /* PWMSS2 */
0x48304100 0x80 /* eCAP2 */
0x48304180 0x80 /* eQEP2 */
0x48304200 0x60 /* ePWM2 */
>;
interrupts = <88 60>; /* ePWM2INT, ePWM2_TZINT */
interrupt-parent = <&AINTC>;
pwm-device-id = <2>;
};
lcd: lcd@4830e000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,am335x-lcd";
reg =< 0x4830e000 0x1000 >;
interrupts = <36>;
interrupt-parent = <&AINTC>;
};
usb@47400000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,musb-am33xx";
reg =< 0x47400000 0x1000 /* USBSS */
0x47401000 0x300 /* USB0 */
0x47401300 0x100 /* USB0_PHY */
0x47401400 0x400 /* USB0_CORE */
0x47401800 0x300 /* USB1 */
0x47401B00 0x100 /* USB1_PHY */
0x47401C00 0x400 /* USB1_CORE */
>;
interrupts = <17 18 19>;
interrupt-parent = <&AINTC>;
/* 1 - Host Mode, 0 - Device Mode */
modemask = <2>;
};
mbox0@480C8000 {
compatible = "am335x,system-mbox";
reg = < 0x480C8000 0x1000 >;
interrupts = <77>;
interrupt-parent = <&AINTC>;
};
spinlock0@480CA000 {
compatible = "am335x,spinlock";
reg = < 0x480CA000 0x1000 >;
};
pruss@4A300000 {
compatible = "ti,pruss-v2";
reg = <0x4A300000 0x80000>;
interrupt-parent = <&AINTC>;
interrupts = <20 21 22 23 24 25 26 27>;
};
};
};

505
src/data/dts/arch/arm/bcm2835.dtsi
View File

@ -1,505 +0,0 @@
/*
* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@bluezbox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
cpu@0 {
compatible = "arm,1176jzf-s";
};
};
SOC: axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x20000000 0x01000000>;
ranges = <0 0x20000000 0x01000000>;
intc: interrupt-controller {
compatible = "broadcom,bcm2835-armctrl-ic",
"broadcom,bcm2708-armctrl-ic";
reg = <0xB200 0x200>;
interrupt-controller;
#interrupt-cells = <1>;
/* Bank 0
* 0: ARM_TIMER
* 1: ARM_MAILBOX
* 2: ARM_DOORBELL_0
* 3: ARM_DOORBELL_1
* 4: VPU0_HALTED
* 5: VPU1_HALTED
* 6: ILLEGAL_TYPE0
* 7: ILLEGAL_TYPE1
*/
/* Bank 1
* 0: TIMER0 16: DMA0
* 1: TIMER1 17: DMA1
* 2: TIMER2 18: VC_DMA2
* 3: TIMER3 19: VC_DMA3
* 4: CODEC0 20: DMA4
* 5: CODEC1 21: DMA5
* 6: CODEC2 22: DMA6
* 7: VC_JPEG 23: DMA7
* 8: ISP 24: DMA8
* 9: VC_USB 25: DMA9
* 10: VC_3D 26: DMA10
* 11: TRANSPOSER 27: DMA11
* 12: MULTICORESYNC0 28: DMA12
* 13: MULTICORESYNC1 29: AUX
* 14: MULTICORESYNC2 30: ARM
* 15: MULTICORESYNC3 31: VPUDMA
*/
/* Bank 2
* 0: HOSTPORT 16: SMI
* 1: VIDEOSCALER 17: GPIO0
* 2: CCP2TX 18: GPIO1
* 3: SDC 19: GPIO2
* 4: DSI0 20: GPIO3
* 5: AVE 21: VC_I2C
* 6: CAM0 22: VC_SPI
* 7: CAM1 23: VC_I2SPCM
* 8: HDMI0 24: VC_SDIO
* 9: HDMI1 25: VC_UART
* 10: PIXELVALVE1 26: SLIMBUS
* 11: I2CSPISLV 27: VEC
* 12: DSI1 28: CPG
* 13: PWA0 29: RNG
* 14: PWA1 30: VC_ARASANSDIO
* 15: CPR 31: AVSPMON
*/
};
timer {
compatible = "broadcom,bcm2835-system-timer",
"broadcom,bcm2708-system-timer";
reg = <0x3000 0x1000>;
interrupts = <8 9 10 11>;
interrupt-parent = <&intc>;
clock-frequency = <1000000>;
};
armtimer {
/* Not AMBA compatible */
compatible = "broadcom,bcm2835-sp804", "arm,sp804";
reg = <0xB400 0x24>;
interrupts = <0>;
interrupt-parent = <&intc>;
};
watchdog0 {
compatible = "broadcom,bcm2835-wdt",
"broadcom,bcm2708-wdt";
reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */
};
gpio: gpio {
compatible = "broadcom,bcm2835-gpio",
"broadcom,bcm2708-gpio";
reg = <0x200000 0xb0>;
/* Unusual arrangement of interrupts
* (determined by testing)
* 17: Bank 0 (GPIOs 0-31)
* 19: Bank 1 (GPIOs 32-53)
* 18: Bank 2
* 20: All banks (GPIOs 0-53)
*/
interrupts = <57 59 58 60>;
interrupt-parent = <&intc>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pins_reserved>;
/* Pins that can short 3.3V to GND in output mode: 46-47
* Pins used by VideoCore: 48-53
*/
broadcom,read-only = <46>, <47>, <48>, <49>, <50>,
<51>, <52>, <53>;
/* BSC0 */
pins_bsc0_a: bsc0_a {
broadcom,pins = <0>, <1>;
};
pins_bsc0_b: bsc0_b {
broadcom,pins = <28>, <29>;
};
pins_bsc0_c: bsc0_c {
broadcom,pins = <44>, <45>;
};
/* BSC1 */
pins_bsc1_a: bsc1_a {
broadcom,pins = <2>, <3>;
};
pins_bsc1_b: bsc1_b {
broadcom,pins = <44>, <45>;
};
/* GPCLK0 */
pins_gpclk0_a: gpclk0_a {
broadcom,pins = <4>;
};
pins_gpclk0_b: gpclk0_b {
broadcom,pins = <20>;
};
pins_gpclk0_c: gpclk0_c {
broadcom,pins = <32>;
};
pins_gpclk0_d: gpclk0_d {
broadcom,pins = <34>;
};
/* GPCLK1 */
pins_gpclk1_a: gpclk1_a {
broadcom,pins = <5>;
};
pins_gpclk1_b: gpclk1_b {
broadcom,pins = <21>;
};
pins_gpclk1_c: gpclk1_c {
broadcom,pins = <42>;
};
pins_gpclk1_d: gpclk1_d {
broadcom,pins = <44>;
};
/* GPCLK2 */
pins_gpclk2_a: gpclk2_a {
broadcom,pins = <6>;
};
pins_gpclk2_b: gpclk2_b {
broadcom,pins = <43>;
};
/* SPI0 */
pins_spi0_a: spi0_a {
broadcom,pins = <7>, <8>, <9>, <10>, <11>;
};
pins_spi0_b: spi0_b {
broadcom,pins = <35>, <36>, <37>, <38>, <39>;
};
/* PWM */
pins_pwm0_a: pwm0_a {
broadcom,pins = <12>;
};
pins_pwm0_b: pwm0_b {
broadcom,pins = <18>;
};
pins_pwm0_c: pwm0_c {
broadcom,pins = <40>;
};
pins_pwm1_a: pwm1_a {
broadcom,pins = <13>;
};
pins_pwm1_b: pwm1_b {
broadcom,pins = <19>;
};
pins_pwm1_c: pwm1_c {
broadcom,pins = <41>;
};
pins_pwm1_d: pwm1_d {
broadcom,pins = <45>;
};
/* UART0 */
pins_uart0_a: uart0_a {
broadcom,pins = <14>, <15>;
};
pins_uart0_b: uart0_b {
broadcom,pins = <32>, <33>;
};
pins_uart0_c: uart0_c {
broadcom,pins = <36>, <37>;
};
pins_uart0_fc_a: uart0_fc_a {
broadcom,pins = <16>, <17>;
};
pins_uart0_fc_b: uart0_fc_b {
broadcom,pins = <30>, <31>;
};
pins_uart0_fc_c: uart0_fc_c {
broadcom,pins = <39>, <38>;
};
/* PCM */
pins_pcm_a: pcm_a {
broadcom,pins = <18>, <19>, <20>, <21>;
};
pins_pcm_b: pcm_b {
broadcom,pins = <28>, <29>, <30>, <31>;
};
/* Secondary Address Bus */
pins_sm_addr_a: sm_addr_a {
broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>;
};
pins_sm_addr_b: sm_addr_b {
broadcom,pins = <33>, <32>, <31>, <30>, <29>,
<28>;
};
pins_sm_ctl_a: sm_ctl_a {
broadcom,pins = <6>, <7>;
};
pins_sm_ctl_b: sm_ctl_b {
broadcom,pins = <34>, <35>;
};
pins_sm_data_8bit_a: sm_data_8bit_a {
broadcom,pins = <8>, <9>, <10>, <11>, <12>,
<13>, <14>, <15>;
};
pins_sm_data_8bit_b: sm_data_8bit_b {
broadcom,pins = <36>, <37>, <38>, <39>, <40>,
<41>, <42>, <43>;
};
pins_sm_data_16bit: sm_data_16bit {
broadcom,pins = <16>, <17>, <18>, <19>, <20>,
<21>, <22>, <23>;
};
pins_sm_data_18bit: sm_data_18bit {
broadcom,pins = <24>, <25>;
};
/* BSCSL */
pins_bscsl: bscsl {
broadcom,pins = <18>, <19>;
};
/* SPISL */
pins_spisl: spisl {
broadcom,pins = <18>, <19>, <20>, <21>;
};
/* SPI1 */
pins_spi1: spi1 {
broadcom,pins = <16>, <17>, <18>, <19>, <20>,
<21>;
};
/* UART1 */
pins_uart1_a: uart1_a {
broadcom,pins = <14>, <15>;
};
pins_uart1_b: uart1_b {
broadcom,pins = <32>, <33>;
};
pins_uart1_c: uart1_c {
broadcom,pins = <40>, <41>;
};
pins_uart1_fc_a: uart1_fc_a {
broadcom,pins = <16>, <17>;
};
pins_uart1_fc_b: uart1_fc_b {
broadcom,pins = <30>, <31>;
};
pins_uart1_fc_c: uart1_fc_c {
broadcom,pins = <43>, <42>;
};
/* SPI2 */
pins_spi2: spi2 {
broadcom,pins = <40>, <41>, <42>, <43>, <44>,
<45>;
};
/* ARM JTAG */
pins_arm_jtag_trst: arm_jtag_trst {
broadcom,pins = <22>;
};
pins_arm_jtag_a: arm_jtag_a {
broadcom,pins = <4>, <5>, <6>, <12>, <13>;
};
pins_arm_jtag_b: arm_jtag_b {
broadcom,pins = <23>, <24>, <25>, <26>, <27>;
};
/* Reserved */
pins_reserved: reserved {
broadcom,pins = <48>, <49>, <50>, <51>, <52>,
<53>;
};
};
rng {
compatible = "broadcom,bcm2835-rng",
"broadcom,bcm2708-rng";
reg = <0x104000 0x20>;
interrupts = <69>;
interrupt-parent = <&intc>;
};
bsc0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "broadcom,bcm2835-bsc",
"broadcom,bcm2708-bsc";
reg = <0x205000 0x20>;
interrupts = <61>;
interrupt-parent = <&intc>;
};
bsc1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "broadcom,bcm2835-bsc",
"broadcom,bcm2708-bsc";
reg = <0x804000 0x20>;
interrupts = <61>;
interrupt-parent = <&intc>;
};
spi0 {
compatible = "broadcom,bcm2835-spi",
"broadcom,bcm2708-spi";
reg = <0x204000 0x20>;
interrupts = <62>;
interrupt-parent = <&intc>;
};
dma: dma {
compatible = "broadcom,bcm2835-dma",
"broadcom,bcm2708-dma";
reg = <0x7000 0x1000>, <0xE05000 0x1000>;
interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>;
interrupt-parent = <&intc>;
broadcom,channels = <0>; /* Set by VideoCore */
};
vc_mbox: mbox {
compatible = "broadcom,bcm2835-mbox",
"broadcom,bcm2708-mbox";
reg = <0xB880 0x40>;
interrupts = <1>;
interrupt-parent = <&intc>;
/* Channels
* 0: Power
* 1: Frame buffer
* 2: Virtual UART
* 3: VCHIQ
* 4: LEDs
* 5: Buttons
* 6: Touch screen
*/
};
sdhci {
compatible = "broadcom,bcm2835-sdhci",
"broadcom,bcm2708-sdhci";
reg = <0x300000 0x100>;
interrupts = <70>;
interrupt-parent = <&intc>;
clock-frequency = <50000000>; /* Set by VideoCore */
};
uart0: uart0 {
compatible = "broadcom,bcm2835-uart",
"broadcom,bcm2708-uart", "arm,pl011",
"arm,primecell";
reg = <0x201000 0x1000>;
interrupts = <65>;
interrupt-parent = <&intc>;
clock-frequency = <3000000>; /* Set by VideoCore */
reg-shift = <2>;
};
vchiq: vchiq {
compatible = "broadcom,bcm2835-vchiq";
reg = <0xB800 0x50>;
interrupts = <2>;
interrupt-parent = <&intc>;
cache-line-size = <32>;
};
usb {
compatible = "broadcom,bcm2835-usb",
"broadcom,bcm2708-usb",
"synopsys,designware-hs-otg2";
reg = <0x980000 0x20000>;
interrupts = <17>;
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};

498
src/data/dts/arch/arm/bcm2836.dtsi
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@ -1,498 +0,0 @@
/*
* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@bluezbox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
timer {
compatible = "arm,armv7-timer";
clock-frequency = <19200000>;
interrupts = <0 1 3 2>;
interrupt-parent = <&local_intc>;
};
SOC: axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x3f000000 0x01000000>;
ranges = <0 0x3f000000 0x01000000>,
<0x40000000 0x40000000 0x00001000>;
local_intc: local_intc {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&local_intc>;
};
intc: interrupt-controller {
compatible = "broadcom,bcm2835-armctrl-ic",
"broadcom,bcm2708-armctrl-ic";
reg = <0xB200 0x200>;
interrupt-parent = <&local_intc>;
interrupts = <8>;
interrupt-controller;
#interrupt-cells = <1>;
/* Bank 0
* 0: ARM_TIMER
* 1: ARM_MAILBOX
* 2: ARM_DOORBELL_0
* 3: ARM_DOORBELL_1
* 4: VPU0_HALTED
* 5: VPU1_HALTED
* 6: ILLEGAL_TYPE0
* 7: ILLEGAL_TYPE1
*/
/* Bank 1
* 0: TIMER0 16: DMA0
* 1: TIMER1 17: DMA1
* 2: TIMER2 18: VC_DMA2
* 3: TIMER3 19: VC_DMA3
* 4: CODEC0 20: DMA4
* 5: CODEC1 21: DMA5
* 6: CODEC2 22: DMA6
* 7: VC_JPEG 23: DMA7
* 8: ISP 24: DMA8
* 9: VC_USB 25: DMA9
* 10: VC_3D 26: DMA10
* 11: TRANSPOSER 27: DMA11
* 12: MULTICORESYNC0 28: DMA12
* 13: MULTICORESYNC1 29: AUX
* 14: MULTICORESYNC2 30: ARM
* 15: MULTICORESYNC3 31: VPUDMA
*/
/* Bank 2
* 0: HOSTPORT 16: SMI
* 1: VIDEOSCALER 17: GPIO0
* 2: CCP2TX 18: GPIO1
* 3: SDC 19: GPIO2
* 4: DSI0 20: GPIO3
* 5: AVE 21: VC_I2C
* 6: CAM0 22: VC_SPI
* 7: CAM1 23: VC_I2SPCM
* 8: HDMI0 24: VC_SDIO
* 9: HDMI1 25: VC_UART
* 10: PIXELVALVE1 26: SLIMBUS
* 11: I2CSPISLV 27: VEC
* 12: DSI1 28: CPG
* 13: PWA0 29: RNG
* 14: PWA1 30: VC_ARASANSDIO
* 15: CPR 31: AVSPMON
*/
};
watchdog0 {
compatible = "broadcom,bcm2835-wdt",
"broadcom,bcm2708-wdt";
reg = <0x10001c 0x0c>; /* 0x1c, 0x20, 0x24 */
};
gpio: gpio {
compatible = "broadcom,bcm2835-gpio",
"broadcom,bcm2708-gpio";
reg = <0x200000 0xb0>;
/* Unusual arrangement of interrupts
* (determined by testing)
* 17: Bank 0 (GPIOs 0-31)
* 19: Bank 1 (GPIOs 32-53)
* 18: Bank 2
* 20: All banks (GPIOs 0-53)
*/
interrupts = <57 59 58 60>;
interrupt-parent = <&intc>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pins_reserved>;
/* Pins that can short 3.3V to GND in output mode: 46
* Pins used by VideoCore: 48-53
*/
broadcom,read-only = <46>, <48>, <49>, <50>,
<51>, <52>, <53>;
/* BSC0 */
pins_bsc0_a: bsc0_a {
broadcom,pins = <0>, <1>;
};
pins_bsc0_b: bsc0_b {
broadcom,pins = <28>, <29>;
};
pins_bsc0_c: bsc0_c {
broadcom,pins = <44>, <45>;
};
/* BSC1 */
pins_bsc1_a: bsc1_a {
broadcom,pins = <2>, <3>;
};
pins_bsc1_b: bsc1_b {
broadcom,pins = <44>, <45>;
};
/* GPCLK0 */
pins_gpclk0_a: gpclk0_a {
broadcom,pins = <4>;
};
pins_gpclk0_b: gpclk0_b {
broadcom,pins = <20>;
};
pins_gpclk0_c: gpclk0_c {
broadcom,pins = <32>;
};
pins_gpclk0_d: gpclk0_d {
broadcom,pins = <34>;
};
/* GPCLK1 */
pins_gpclk1_a: gpclk1_a {
broadcom,pins = <5>;
};
pins_gpclk1_b: gpclk1_b {
broadcom,pins = <21>;
};
pins_gpclk1_c: gpclk1_c {
broadcom,pins = <42>;
};
pins_gpclk1_d: gpclk1_d {
broadcom,pins = <44>;
};
/* GPCLK2 */
pins_gpclk2_a: gpclk2_a {
broadcom,pins = <6>;
};
pins_gpclk2_b: gpclk2_b {
broadcom,pins = <43>;
};
/* SPI0 */
pins_spi0_a: spi0_a {
broadcom,pins = <7>, <8>, <9>, <10>, <11>;
};
pins_spi0_b: spi0_b {
broadcom,pins = <35>, <36>, <37>, <38>, <39>;
};
/* PWM */
pins_pwm0_a: pwm0_a {
broadcom,pins = <12>;
};
pins_pwm0_b: pwm0_b {
broadcom,pins = <18>;
};
pins_pwm0_c: pwm0_c {
broadcom,pins = <40>;
};
pins_pwm1_a: pwm1_a {
broadcom,pins = <13>;
};
pins_pwm1_b: pwm1_b {
broadcom,pins = <19>;
};
pins_pwm1_c: pwm1_c {
broadcom,pins = <41>;
};
pins_pwm1_d: pwm1_d {
broadcom,pins = <45>;
};
/* UART0 */
pins_uart0_a: uart0_a {
broadcom,pins = <14>, <15>;
};
pins_uart0_b: uart0_b {
broadcom,pins = <32>, <33>;
};
pins_uart0_c: uart0_c {
broadcom,pins = <36>, <37>;
};
pins_uart0_fc_a: uart0_fc_a {
broadcom,pins = <16>, <17>;
};
pins_uart0_fc_b: uart0_fc_b {
broadcom,pins = <30>, <31>;
};
pins_uart0_fc_c: uart0_fc_c {
broadcom,pins = <39>, <38>;
};
/* PCM */
pins_pcm_a: pcm_a {
broadcom,pins = <18>, <19>, <20>, <21>;
};
pins_pcm_b: pcm_b {
broadcom,pins = <28>, <29>, <30>, <31>;
};
/* Secondary Address Bus */
pins_sm_addr_a: sm_addr_a {
broadcom,pins = <5>, <4>, <3>, <2>, <1>, <0>;
};
pins_sm_addr_b: sm_addr_b {
broadcom,pins = <33>, <32>, <31>, <30>, <29>,
<28>;
};
pins_sm_ctl_a: sm_ctl_a {
broadcom,pins = <6>, <7>;
};
pins_sm_ctl_b: sm_ctl_b {
broadcom,pins = <34>, <35>;
};
pins_sm_data_8bit_a: sm_data_8bit_a {
broadcom,pins = <8>, <9>, <10>, <11>, <12>,
<13>, <14>, <15>;
};
pins_sm_data_8bit_b: sm_data_8bit_b {
broadcom,pins = <36>, <37>, <38>, <39>, <40>,
<41>, <42>, <43>;
};
pins_sm_data_16bit: sm_data_16bit {
broadcom,pins = <16>, <17>, <18>, <19>, <20>,
<21>, <22>, <23>;
};
pins_sm_data_18bit: sm_data_18bit {
broadcom,pins = <24>, <25>;
};
/* BSCSL */
pins_bscsl: bscsl {
broadcom,pins = <18>, <19>;
};
/* SPISL */
pins_spisl: spisl {
broadcom,pins = <18>, <19>, <20>, <21>;
};
/* SPI1 */
pins_spi1: spi1 {
broadcom,pins = <16>, <17>, <18>, <19>, <20>,
<21>;
};
/* UART1 */
pins_uart1_a: uart1_a {
broadcom,pins = <14>, <15>;
};
pins_uart1_b: uart1_b {
broadcom,pins = <32>, <33>;
};
pins_uart1_c: uart1_c {
broadcom,pins = <40>, <41>;
};
pins_uart1_fc_a: uart1_fc_a {
broadcom,pins = <16>, <17>;
};
pins_uart1_fc_b: uart1_fc_b {
broadcom,pins = <30>, <31>;
};
pins_uart1_fc_c: uart1_fc_c {
broadcom,pins = <43>, <42>;
};
/* SPI2 */
pins_spi2: spi2 {
broadcom,pins = <40>, <41>, <42>, <43>, <44>,
<45>;
};
/* ARM JTAG */
pins_arm_jtag_trst: arm_jtag_trst {
broadcom,pins = <22>;
};
pins_arm_jtag_a: arm_jtag_a {
broadcom,pins = <4>, <5>, <6>, <12>, <13>;
};
pins_arm_jtag_b: arm_jtag_b {
broadcom,pins = <23>, <24>, <25>, <26>, <27>;
};
/* Reserved */
pins_reserved: reserved {
broadcom,pins = <48>, <49>, <50>, <51>, <52>,
<53>;
};
};
rng {
compatible = "broadcom,bcm2835-rng",
"broadcom,bcm2708-rng";
reg = <0x104000 0x20>;
interrupts = <69>;
interrupt-parent = <&intc>;
};
bsc0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "broadcom,bcm2835-bsc",
"broadcom,bcm2708-bsc";
reg = <0x205000 0x20>;
interrupts = <61>;
interrupt-parent = <&intc>;
};
bsc1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "broadcom,bcm2835-bsc",
"broadcom,bcm2708-bsc";
reg = <0x804000 0x20>;
interrupts = <61>;
interrupt-parent = <&intc>;
};
spi0 {
compatible = "broadcom,bcm2835-spi",
"broadcom,bcm2708-spi";
reg = <0x204000 0x20>;
interrupts = <62>;
interrupt-parent = <&intc>;
};
dma: dma {
compatible = "broadcom,bcm2835-dma",
"broadcom,bcm2708-dma";
reg = <0x7000 0x1000>, <0xE05000 0x1000>;
interrupts = <24 25 26 27 28 29 30 31 32 33 34 35 36>;
interrupt-parent = <&intc>;
broadcom,channels = <0>; /* Set by VideoCore */
};
vc_mbox: mbox {
compatible = "broadcom,bcm2835-mbox",
"broadcom,bcm2708-mbox";
reg = <0xB880 0x40>;
interrupts = <1>;
interrupt-parent = <&intc>;
/* Channels
* 0: Power
* 1: Frame buffer
* 2: Virtual UART
* 3: VCHIQ
* 4: LEDs
* 5: Buttons
* 6: Touch screen
*/
};
sdhci {
compatible = "broadcom,bcm2835-sdhci",
"broadcom,bcm2708-sdhci";
reg = <0x300000 0x100>;
interrupts = <70>;
interrupt-parent = <&intc>;
clock-frequency = <250000000>; /* Set by VideoCore */
};
uart0: uart0 {
compatible = "broadcom,bcm2835-uart",
"broadcom,bcm2708-uart", "arm,pl011",
"arm,primecell";
reg = <0x201000 0x1000>;
interrupts = <65>;
interrupt-parent = <&intc>;
clock-frequency = <48000000>; /* Set by VideoCore */
reg-shift = <2>;
};
vchiq: vchiq {
compatible = "broadcom,bcm2835-vchiq";
reg = <0xB800 0x50>;
interrupts = <2>;
interrupt-parent = <&intc>;
cache-line-size = <32>;
};
usb {
compatible = "broadcom,bcm2835-usb",
"broadcom,bcm2708-usb",
"synopsys,designware-hs-otg2";
reg = <0x980000 0x20000>;
interrupts = <17>;
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};

145
src/data/dts/arch/arm/beaglebone.dts
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@ -1,145 +0,0 @@
/*-
* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/dts-v1/;
/include/ "am335x.dtsi"
/ {
model = "beaglebone";
compatible = "beaglebone", "ti,am335x";
aliases {
soc = &SOC;
uart0 = &uart0;
};
memory {
device_type = "memory";
reg = < 0x80000000 0x10000000 >; /* 256MB RAM */
};
am335x {
scm@44e10000 {
/* Set of triplets < padname, muxname, padstate> */
scm-pad-config =
/* I2C0 */
"I2C0_SDA", "I2C0_SDA","i2c",
"I2C0_SCL", "I2C0_SCL","i2c",
/* Ethernet */
"MII1_RX_ER", "gmii1_rxerr", "input_pulldown",
"MII1_TX_EN", "gmii1_txen", "output",
"MII1_RX_DV", "gmii1_rxdv", "input_pulldown",
"MII1_TXD3", "gmii1_txd3", "output",
"MII1_TXD2", "gmii1_txd2", "output",
"MII1_TXD1", "gmii1_txd1", "output",
"MII1_TXD0", "gmii1_txd0", "output",
"MII1_TX_CLK", "gmii1_txclk", "input_pulldown",
"MII1_RX_CLK", "gmii1_rxclk", "input_pulldown",
"MII1_RXD3", "gmii1_rxd3", "input_pulldown",
"MII1_RXD2", "gmii1_rxd2", "input_pulldown",
"MII1_RXD1", "gmii1_rxd1", "input_pulldown",
"MII1_RXD0", "gmii1_rxd0", "input_pulldown",
"MDIO", "mdio_data", "input_pullup",
"MDC", "mdio_clk", "output_pullup",
/* MMCSD0 */
"MMC0_CMD", "mmc0_cmd", "input_pullup",
"MMC0_CLK", "mmc0_clk", "input_pullup",
"MMC0_DAT0", "mmc0_dat0", "input_pullup",
"MMC0_DAT1", "mmc0_dat1", "input_pullup",
"MMC0_DAT2", "mmc0_dat2", "input_pullup",
"MMC0_DAT3", "mmc0_dat3", "input_pullup",
/* USB0 and USB1 */
"USB0_DRVVBUS", "USB0_DRVVBUS", "output",
"USB1_DRVVBUS", "USB1_DRVVBUS", "output",
/* GPIO */
"ECAP0_IN_PWM0_OUT", "gpio0_7", "input_pulldown",
"GPMC_AD10", "gpio0_26", "input_pulldown",
"GPMC_AD11", "gpio0_27", "input_pulldown",
"GPMC_AD0", "gpio1_0", "input_pulldown",
"GPMC_AD1", "gpio1_1", "input_pulldown",
"GPMC_AD2", "gpio1_2", "input_pulldown",
"GPMC_AD3", "gpio1_3", "input_pulldown",
"GPMC_AD4", "gpio1_4", "input_pulldown",
"GPMC_AD5", "gpio1_5", "input_pulldown",
"GPMC_AD6", "gpio1_6", "input_pulldown",
"GPMC_AD7", "gpio1_7", "input_pulldown",
"GPMC_AD12", "gpio1_12", "input_pulldown",
"GPMC_AD13", "gpio1_13", "input_pulldown",
"GPMC_AD14", "gpio1_14", "input_pulldown",
"GPMC_AD15", "gpio1_15", "input_pulldown",
"GPMC_A0", "gpio1_16", "input_pulldown",
"GPMC_A1", "gpio1_17", "input_pulldown",
"GPMC_A5", "gpio1_21", "output", /* User LED 1 */
"GPMC_A6", "gpio1_22", "output", /* User LED 2 */
"GPMC_A7", "gpio1_23", "output", /* User LED 3 */
"GPMC_A8", "gpio1_24", "output", /* User LED 4 */
"GPMC_BEn1", "gpio1_28", "input_pulldown",
"GPMC_CSn0", "gpio1_29", "input_pulldown",
"GPMC_CSn1", "gpio1_30", "input_pulldown",
"GPMC_CSn2", "gpio1_31", "input_pulldown",
"GPMC_CLK", "gpio2_1", "input_pulldown",
"LCD_DATA0", "gpio2_6", "input_pulldown",
"LCD_DATA1", "gpio2_7", "input_pulldown",
"LCD_DATA2", "gpio2_8", "input_pulldown",
"LCD_DATA3", "gpio2_9", "input_pulldown",
"LCD_DATA4", "gpio2_10", "input_pulldown",
"LCD_DATA5", "gpio2_11", "input_pulldown",
"LCD_DATA6", "gpio2_12", "input_pulldown",
"LCD_DATA7", "gpio2_13", "input_pulldown",
"LCD_VSYNC", "gpio2_22", "input_pulldown",
"LCD_HSYNC", "gpio2_23", "input_pulldown",
"LCD_PCLK", "gpio2_24", "input_pulldown",
"LCD_AC_BIAS_EN", "gpio2_25", "input_pulldown",
"MCASP0_FSR", "gpio3_19", "input_pulldown",
"MCASP0_AHCLKX", "gpio3_21", "input_pulldown",
/* TIMERs */
"GPMC_ADVn_ALE", "timer4", "output",
"GPMC_BEn0_CLE", "timer5", "output",
"GPMC_WEn", "timer6", "output",
"GPMC_OEn_REn", "timer7", "output",
/* PWM */
"GPMC_A2", "ehrpwm1A", "output",
"GPMC_A3", "ehrpwm1B", "output",
"GPMC_AD8", "ehrpwm2A", "output",
"GPMC_AD9", "ehrpwm2B", "output";
};
i2c@44e0b000 {
pmic@24 {
compatible = "ti,am335x-pmic";
reg = <0x48>;
};
};
};
chosen {
stdin = "uart0";
stdout = "uart0";
};
};

184
src/data/dts/arch/arm/boneblack.dts
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@ -1,184 +0,0 @@
/*-
* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/dts-v1/;
/include/ "am335x.dtsi"
/ {
model = "beaglebone-black";
compatible = "beaglebone-black", "beaglebone", "ti,am335x";
aliases {
soc = &SOC;
uart0 = &uart0;
};
memory {
device_type = "memory";
reg = < 0x80000000 0x20000000 >; /* 512MB RAM */
};
am335x {
scm@44e10000 {
/* Set of triplets < padname, muxname, padstate> */
scm-pad-config =
/* I2C0 */
"I2C0_SDA", "I2C0_SDA","i2c",
"I2C0_SCL", "I2C0_SCL","i2c",
/* I2C1 */
"SPI0_D1", "I2C1_SDA", "i2c",
"SPI0_CS0", "I2C1_SCL", "i2c",
/* I2C2 */
"UART1_CTSn", "I2C2_SDA", "i2c",
"UART1_RTSn", "I2C2_SCL", "i2c",
/* Ethernet */
"MII1_RX_ER", "gmii1_rxerr", "input_pulldown",
"MII1_TX_EN", "gmii1_txen", "output",
"MII1_RX_DV", "gmii1_rxdv", "input_pulldown",
"MII1_TXD3", "gmii1_txd3", "output",
"MII1_TXD2", "gmii1_txd2", "output",
"MII1_TXD1", "gmii1_txd1", "output",
"MII1_TXD0", "gmii1_txd0", "output",
"MII1_TX_CLK", "gmii1_txclk", "input_pulldown",
"MII1_RX_CLK", "gmii1_rxclk", "input_pulldown",
"MII1_RXD3", "gmii1_rxd3", "input_pulldown",
"MII1_RXD2", "gmii1_rxd2", "input_pulldown",
"MII1_RXD1", "gmii1_rxd1", "input_pulldown",
"MII1_RXD0", "gmii1_rxd0", "input_pulldown",
"MDIO", "mdio_data", "input_pullup",
"MDC", "mdio_clk", "output_pullup",
/* MMCSD0 */
"MMC0_CMD", "mmc0_cmd", "input_pullup",
"MMC0_CLK", "mmc0_clk", "input_pullup",
"MMC0_DAT0", "mmc0_dat0", "input_pullup",
"MMC0_DAT1", "mmc0_dat1", "input_pullup",
"MMC0_DAT2", "mmc0_dat2", "input_pullup",
"MMC0_DAT3", "mmc0_dat3", "input_pullup",
/* MMC1 */
"GPMC_CSn1", "mmc1_clk", "input_pullup",
"GPMC_CSn2", "mmc1_cmd", "input_pullup",
"GPMC_CSn3", "gpio2_0", "output_pullup", /* Reset */
"GPMC_AD0", "mmc1_dat0", "input_pullup",
"GPMC_AD1", "mmc1_dat1", "input_pullup",
"GPMC_AD2", "mmc1_dat2", "input_pullup",
"GPMC_AD3", "mmc1_dat3", "input_pullup",
"GPMC_AD4", "mmc1_dat4", "input_pullup",
"GPMC_AD5", "mmc1_dat5", "input_pullup",
"GPMC_AD6", "mmc1_dat6", "input_pullup",
"GPMC_AD7", "mmc1_dat7", "input_pullup",
/* GPIO */
"ECAP0_IN_PWM0_OUT", "gpio0_7", "input_pulldown",
"GPMC_AD10", "gpio0_26", "input_pulldown",
"GPMC_AD11", "gpio0_27", "input_pulldown",
"GPMC_AD12", "gpio1_12", "input_pulldown",
"GPMC_AD13", "gpio1_13", "input_pulldown",
"GPMC_AD14", "gpio1_14", "input_pulldown",
"GPMC_AD15", "gpio1_15", "input_pulldown",
"GPMC_A0", "gpio1_16", "input_pulldown",
"GPMC_A1", "gpio1_17", "input_pulldown",
"GPMC_A5", "gpio1_21", "output", /* User LED 1 */
"GPMC_A6", "gpio1_22", "output", /* User LED 2 */
"GPMC_A7", "gpio1_23", "output", /* User LED 3 */
"GPMC_A8", "gpio1_24", "output", /* User LED 4 */
"GPMC_BEn1", "gpio1_28", "input_pulldown",
"GPMC_CSn0", "gpio1_29", "input_pulldown",
"GPMC_CLK", "gpio2_1", "input_pulldown",
"LCD_DATA0", "gpio2_6", "input_pulldown",
"LCD_DATA1", "gpio2_7", "input_pulldown",
"LCD_DATA2", "gpio2_8", "input_pulldown",
"LCD_DATA3", "gpio2_9", "input_pulldown",
"LCD_DATA4", "gpio2_10", "input_pulldown",
"LCD_DATA5", "gpio2_11", "input_pulldown",
"LCD_DATA6", "gpio2_12", "input_pulldown",
"LCD_DATA7", "gpio2_13", "input_pulldown",
"LCD_VSYNC", "gpio2_22", "input_pulldown",
"LCD_HSYNC", "gpio2_23", "input_pulldown",
"LCD_PCLK", "gpio2_24", "input_pulldown",
"LCD_AC_BIAS_EN", "gpio2_25", "input_pulldown",
"MCASP0_FSR", "gpio3_19", "input_pulldown",
"MCASP0_AHCLKX", "gpio3_21", "input_pulldown",
/* TIMERs */
"GPMC_ADVn_ALE", "timer4", "output",
"GPMC_BEn0_CLE", "timer5", "output",
"GPMC_WEn", "timer6", "output",
"GPMC_OEn_REn", "timer7", "output",
/* USB0 and USB1 */
"USB0_DRVVBUS", "USB0_DRVVBUS", "output",
"USB1_DRVVBUS", "USB1_DRVVBUS", "output",
/* PWM */
"GPMC_A2", "ehrpwm1A", "output",
"GPMC_A3", "ehrpwm1B", "output",
"GPMC_AD8", "ehrpwm2A", "output",
"GPMC_AD9", "ehrpwm2B", "output";
};
mmchs1@481D8000 {
bus-width = <8>;
status = "okay";
non-removable;
};
i2c@44e0b000 {
pmic@48 {
compatible = "ti,am335x-pmic";
reg = <0x48>;
};
};
};
leds {
compatible = "gpio-leds";
led1 {
gpios = <&GPIO 53 2 0>;
name = "led1";
};
led2 {
gpios = <&GPIO 54 2 0>;
name = "led2";
};
led3 {
gpios = <&GPIO 55 2 0>;
name = "led3";
};
led4 {
gpios = <&GPIO 56 2 0>;
name = "led4";
};
};
chosen {
stdin = "uart0";
stdout = "uart0";
};
};

71
src/data/dts/arch/arm/cubieboard.dts
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@ -1,71 +0,0 @@
/*-
* Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/dts-v1/;
/include/ "sun4i-a10.dtsi"
/ {
model = "Cubietech Cubieboard";
memory {
device_type = "memory";
reg = < 0x40000000 0x40000000 >; /* 1GB RAM */
};
aliases {
soc = &SOC;
UART0 = &UART0;
};
SOC: a10 {
usb1: usb@01c14000 {
status = "okay";
};
usb2: usb@01c1c000 {
status = "okay";
};
UART0: serial@01c28000 {
status = "okay";
};
emac@01c0b000 {
status = "okay";
};
};
chosen {
bootargs = "-v";
stdin = "UART0";
stdout = "UART0";
};
};

75
src/data/dts/arch/arm/cubieboard2.dts
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@ -1,75 +0,0 @@
/*-
* Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/dts-v1/;
/include/ "sun7i-a20.dtsi"
/ {
model = "Cubietech Cubieboard2";
memory {
device_type = "memory";
reg = < 0x40000000 0x40000000 >; /* 1GB RAM */
};
aliases {
soc = &SOC;
UART0 = &UART0;
};
SOC: a20 {
usb1: usb@01c14000 {
status = "okay";
};
usb2: usb@01c1c000 {
status = "okay";
};
UART0: serial@01c28000 {
status = "okay";
};
emac@01c0b000 {
status = "okay";
};
ahci: sata@01c18000 {
status = "okay";
};
};
chosen {
bootargs = "-v";
stdin = "UART0";
stdout = "UART0";
};
};

247
src/data/dts/arch/arm/imx51-efikamx.dts
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@ -1,247 +0,0 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
* Copyright 2012 Genesi USA, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "imx51.dtsi"
/ {
model = "Genesi Efika MX (Smarttop)";
compatible = "genesi,imx51-efikamx", "fsl,imx51";
memory {
reg = <0x90000000 0x20000000>;
};
soc {
aips@70000000 {
spba@70000000 {
esdhc@70004000 {
cd-gpios = <&gpio1 0 0>;
wp-gpios = <&gpio1 1 0>;
status = "okay";
};
ssi2: ssi@70014000 {
fsl,mode = "i2s-slave";
status = "okay";
};
ecspi@70010000 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
status = "okay";
pmic: mc13892@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13892";
spi-max-frequency = <6000000>;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <6 0x4>;
fsl,mc13xxx-uses-rtc;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1375000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
vpll_reg: vpll {
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vdig_reg: vdig {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
};
vsd_reg: vsd {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
};
vusb2_reg: vusb2 {
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
regulator-always-on;
};
vvideo_reg: vvideo {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
regulator-boot-on;
};
vaudio_reg: vaudio {
regulator-min-microvolt = <2300000>;
regulator-max-microvolt = <3000000>;
};
vcam_reg: vcam {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3000000>;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3150000>;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <3150000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-always-on;
};
};
};
flash: sst25vf032b@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf032b";
spi-max-frequency = <25000000>;
reg = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x200000>;
};
partition@200000 {
label = "user";
reg = <0x200000 0x200000>;
};
};
};
};
wdog@73f98000 {
status = "okay";
};
iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc";
reg = <0x73fa8000 0x4000>;
};
uart1: serial@73fbc000 {
fsl,uart-has-rtscts;
status = "okay";
};
};
aips@80000000 {
sdma@83fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
i2c@83fc4000 {
status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clock-frequency = <12288000>;
VDDA-supply = <&vdig_reg>;
VDDIO-supply = <&vvideo_reg>;
};
};
audmux@83fd0000 {
status = "okay";
};
};
};
gpio-keys {
compatible = "gpio-keys";
power {
label = "Power Button";
gpios = <&gpio2 31 0>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};
};
gpio-leds {
compatible = "gpio-leds";
red {
label = "red";
gpios = <&gpio3 13>;
linux,default-trigger = "ide-disk";
};
green {
label = "green";
gpios = <&gpio3 14>;
linux,default-trigger = "default-on";
};
blue {
label = "blue";
gpios = <&gpio3 15>;
linux,default-trigger = "mmc0";
};
};
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "efikamx-sgtl5000";
ssi-controller = <&ssi2>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Ext Spk", "LINE_OUT";
audio-codec = <&codec>;
mux-int-port = <2>;
mux-ext-port = <3>;
};
};

58
src/data/dts/arch/arm/omap-gpmc-smsc9221.dtsi
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@ -1,58 +0,0 @@
/*
* Common file for GPMC connected smsc9221 on omaps
*
* Compared to smsc911x, smsc9221 (and others like smsc9217
* or smsc 9218) has faster timings, leading to higher
* bandwidth.
*
* Note that the board specifc DTS file needs to specify
* ranges, pinctrl, reg, interrupt parent and interrupts.
*/
/ {
vddvario: regulator-vddvario {
compatible = "regulator-fixed";
regulator-name = "vddvario";
regulator-always-on;
};
vdd33a: regulator-vdd33a {
compatible = "regulator-fixed";
regulator-name = "vdd33a";
regulator-always-on;
};
};
&gpmc {
ethernet@gpmc {
compatible = "smsc,lan9221","smsc,lan9115";
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <42>;
gpmc,cs-wr-off-ns = <36>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <12>;
gpmc,adv-wr-off-ns = <12>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <42>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <36>;
gpmc,rd-cycle-ns = <60>;
gpmc,wr-cycle-ns = <54>;
gpmc,access-ns = <36>;
gpmc,page-burst-access-ns = <0>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,wr-data-mux-bus-ns = <18>;
gpmc,wr-access-ns = <42>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
vddvario-supply = <&vddvario>;
vdd33a-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};
};

366
src/data/dts/arch/arm/omap3-beagle-xm.dts
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@ -1,366 +0,0 @@
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "omap36xx.dtsi"
/ {
model = "TI OMAP3 BeagleBoard xM";
compatible = "ti,omap3-beagle-xm", "ti,omap36xx", "ti,omap3";
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
aliases {
display0 = &dvi0;
display1 = &tv0;
};
leds {
compatible = "gpio-leds";
heartbeat {
label = "beagleboard::usr0";
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
linux,default-trigger = "heartbeat";
};
mmc {
label = "beagleboard::usr1";
gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
linux,default-trigger = "mmc0";
};
};
pwmleds {
compatible = "pwm-leds";
pmu_stat {
label = "beagleboard::pmu_stat";
pwms = <&twl_pwmled 1 7812500>;
max-brightness = <127>;
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3beagle";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
gpio_keys {
compatible = "gpio-keys";
user {
label = "user";
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
linux,code = <0x114>;
gpio-key,wakeup;
};
};
/* HS USB Port 2 Power */
hsusb2_power: hsusb2_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb2_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
startup-delay-us = <70000>;
};
/* HS USB Host PHY on PORT 2 */
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
vcc-supply = <&hsusb2_power>;
};
tfp410: encoder@0 {
compatible = "ti,tfp410";
powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
/* XXX pinctrl from twl */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint@0 {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint@0 {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector@0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
tv0: connector@1 {
compatible = "svideo-connector";
label = "tv";
port {
tv_connector_in: endpoint {
remote-endpoint = <&venc_out>;
};
};
};
};
&omap3_pmx_wkup {
gpio1_pins: pinmux_gpio1_pins {
pinctrl-single,pins = <
0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
>;
};
dss_dpi_pins2: pinmux_dss_dpi_pins1 {
pinctrl-single,pins = <
0x0a (PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
0x0c (PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
0x10 (PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
0x12 (PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
0x14 (PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
0x16 (PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
>;
};
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_pins
>;
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
>;
};
hsusb2_pins: pinmux_hsusb2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
>;
};
dss_dpi_pins1: pinmux_dss_dpi_pins2 {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_2_pins
>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
twl_power: power {
compatible = "ti,twl4030-power-beagleboard-xm", "ti,twl4030-power-idle-osc-off";
ti,use_poweroff;
};
};
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <100000>;
};
&mmc1 {
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */
ti,pullups = <0x000002>;
/*
* pulldowns:
* BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
* BIT(15), BIT(16), BIT(17)
*/
ti,pulldowns = <0x03a1c4>;
};
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
&uart3 {
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_pins>;
};
&usbhshost {
port2-mode = "ehci-phy";
};
&usbhsehci {
phys = <0 &hsusb2_phy>;
};
&vaux2 {
regulator-name = "usb_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
&mcbsp2 {
status = "okay";
};
&dss {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <
&dss_dpi_pins1
&dss_dpi_pins2
>;
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
&venc {
status = "ok";
vdda-supply = <&vdac>;
port {
venc_out: endpoint {
remote-endpoint = <&tv_connector_in>;
ti,channels = <2>;
};
};
};

221
src/data/dts/arch/arm/omap3-overo-base.dtsi
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@ -1,221 +0,0 @@
/*
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* The Gumstix Overo must be combined with an expansion board.
*/
/ {
pwmleds {
compatible = "pwm-leds";
overo {
label = "overo:blue:COM";
pwms = <&twl_pwmled 1 7812500>;
max-brightness = <127>;
linux,default-trigger = "mmc0";
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "overo";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
/* HS USB Port 2 Power */
hsusb2_power: hsusb2_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio6 8 0>; /* gpio_168: vbus enable */
startup-delay-us = <70000>;
enable-active-high;
};
/* HS USB Host PHY on PORT 2 */
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; /* gpio_183 */
vcc-supply = <&hsusb2_power>;
};
/* Regulator to trigger the nPoweron signal of the Wifi module */
w3cbw003c_npoweron: regulator-w3cbw003c-npoweron {
compatible = "regulator-fixed";
regulator-name = "regulator-w3cbw003c-npoweron";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* gpio_54: nPoweron */
enable-active-high;
};
/* Regulator to trigger the nReset signal of the Wifi module */
w3cbw003c_wifi_nreset: regulator-w3cbw003c-wifi-nreset {
pinctrl-names = "default";
pinctrl-0 = <&w3cbw003c_pins &w3cbw003c_2_pins>;
compatible = "regulator-fixed";
regulator-name = "regulator-w3cbw003c-wifi-nreset";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* gpio_16: WiFi nReset */
startup-delay-us = <10000>;
};
/* Regulator to trigger the nReset signal of the Bluetooth module */
w3cbw003c_bt_nreset: regulator-w3cbw003c-bt-nreset {
compatible = "regulator-fixed";
regulator-name = "regulator-w3cbw003c-bt-nreset";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio_164: BT nReset */
startup-delay-us = <10000>;
};
};
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_pins
>;
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */
OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */
>;
};
/* WiFi/BT combo */
w3cbw003c_pins: pinmux_w3cbw003c_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */
>;
};
hsusb2_pins: pinmux_hsusb2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
OMAP3_CORE1_IOPAD(0x21c0, PIN_OUTPUT | MUX_MODE4) /* i2c2_sda.gpio_183 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
/* i2c2 pins are used for gpio */
&i2c2 {
status = "disabled";
};
/* on board microSD slot */
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
bus-width = <4>;
};
/* optional on board WiFi */
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&w3cbw003c_npoweron>;
vqmmc-supply = <&w3cbw003c_bt_nreset>;
vmmc_aux-supply = <&w3cbw003c_wifi_nreset>;
bus-width = <4>;
cap-sdio-irq;
non-removable;
};
&twl_gpio {
ti,use-leds;
};
&usb_otg_hs {
interface-type = <0>;
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
mode = <3>;
power = <50>;
};
&usbhshost {
port2-mode = "ehci-phy";
};
&usbhsehci {
phys = <0 &hsusb2_phy>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};

111
src/data/dts/arch/arm/omap3-overo-common-dvi.dtsi
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@ -1,111 +0,0 @@
/*
* Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* DVI output for some Gumstix Overo boards (Tobi and Summit)
*/
&omap3_pmx_core {
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
>;
};
};
/* Needed to power the DPI pins */
&vpll2 {
regulator-always-on;
};
&dss {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&dss_dpi_pins>;
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
/ {
aliases {
display0 = &dvi0;
};
tfp410: encoder@0 {
compatible = "ti,tfp410";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint@0 {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint@0 {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector@0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
};

95
src/data/dts/arch/arm/omap3-overo-common-peripherals.dtsi
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@ -1,95 +0,0 @@
/*
* Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Peripherals common to all Gumstix Overo boards (Tobi, Summit, Palo43,...)
*/
/ {
lis33_3v3: lis33-3v3-reg {
compatible = "regulator-fixed";
regulator-name = "lis33-3v3-reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
lis33_1v8: lis33-1v8-reg {
compatible = "regulator-fixed";
regulator-name = "lis33-1v8-reg";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&omap3_pmx_core {
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <100000>;
/* optional 1K EEPROM with revision information */
eeprom@51 {
compatible = "atmel,24c01";
reg = <0x51>;
pagesize = <8>;
};
lis33de: lis33de@1d {
compatible = "st,lis33de", "st,lis3lv02d";
reg = <0x1d>;
Vdd-supply = <&lis33_1v8>;
Vdd_IO-supply = <&lis33_3v3>;
st,click-single-x;
st,click-single-y;
st,click-single-z;
st,click-thresh-x = <10>;
st,click-thresh-y = <10>;
st,click-thresh-z = <10>;
st,irq1-click;
st,irq2-click;
st,wakeup-x-lo;
st,wakeup-x-hi;
st,wakeup-y-lo;
st,wakeup-y-hi;
st,wakeup-z-lo;
st,wakeup-z-hi;
st,min-limit-x = <120>;
st,min-limit-y = <120>;
st,min-limit-z = <140>;
st,max-limit-x = <550>;
st,max-limit-y = <550>;
st,max-limit-z = <750>;
};
};
&mmc3 {
status = "disabled";
};
&uart3 {
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};

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src/data/dts/arch/arm/omap3-overo-tobi-common.dtsi
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/*
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Tobi expansion board is manufactured by Gumstix Inc.
*/
#include "omap3-overo-common-peripherals.dtsi"
#include "omap3-overo-common-dvi.dtsi"
/ {
leds {
compatible = "gpio-leds";
heartbeat {
label = "overo:red:gpio21";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
#include "omap-gpmc-smsc9221.dtsi"
&gpmc {
ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */
ethernet@gpmc {
reg = <5 0 0xff>;
interrupt-parent = <&gpio6>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>; /* GPIO 176 */
};
};
&lis33de {
status = "disabled";
};

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src/data/dts/arch/arm/omap3-overo-tobi.dts
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/*
* Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Tobi expansion board is manufactured by Gumstix Inc.
*/
/dts-v1/;
#include "omap3-overo.dtsi"
#include "omap3-overo-tobi-common.dtsi"
/ {
model = "OMAP35xx Gumstix Overo on Tobi";
compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3";
};

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src/data/dts/arch/arm/omap3-overo.dtsi
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/*
* Copyright (C) 2014 Florian Vaussard, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap34xx.dtsi"
#include "omap3-overo-base.dtsi"
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <
&hsusb2_2_pins
>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
w3cbw003c_2_pins: pinmux_w3cbw003c_2_pins {
pinctrl-single,pins = <
OMAP3430_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
>;
};
};
&mcbsp2 {
status = "okay";
};

814
src/data/dts/arch/arm/omap3.dtsi
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/*
* Device Tree Source for OMAP3 SoC
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>
#include "skeleton.dtsi"
/ {
compatible = "ti,omap3430", "ti,omap3";
interrupt-parent = <&intc>;
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a8";
device_type = "cpu";
reg = <0x0>;
clocks = <&dpll1_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
};
};
pmu {
compatible = "arm,cortex-a8-pmu";
reg = <0x54000000 0x800000>;
interrupts = <3>;
ti,hwmods = "debugss";
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
iva: iva {
compatible = "ti,iva2.2";
ti,hwmods = "iva";
dsp {
compatible = "ti,omap3-c64";
};
};
};
/*
* XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex.
* Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "simple-bus";
reg = <0x68000000 0x10000>;
interrupts = <9 10>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
aes: aes@480c5000 {
compatible = "ti,omap3-aes";
ti,hwmods = "aes";
reg = <0x480c5000 0x50>;
interrupts = <0>;
};
prm: prm@48306000 {
compatible = "ti,omap3-prm";
reg = <0x48306000 0x4000>;
interrupts = <11>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
cm: cm@48004000 {
compatible = "ti,omap3-cm";
reg = <0x48004000 0x4000>;
cm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_clockdomains: clockdomains {
};
};
scrm: scrm@48002000 {
compatible = "ti,omap3-scrm";
reg = <0x48002000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@48320000 {
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
ti,hwmods = "counter_32k";
};
intc: interrupt-controller@48200000 {
compatible = "ti,omap3-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x48200000 0x1000>;
};
sdma: dma-controller@48056000 {
compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
reg = <0x48056000 0x1000>;
interrupts = <12>,
<13>,
<14>,
<15>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <96>;
};
omap3_pmx_core: pinmux@48002030 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002030 0x0238>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
omap3_pmx_wkup: pinmux@48002a00 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002a00 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
omap3_scm_general: tisyscon@48002270 {
compatible = "syscon";
reg = <0x48002270 0x2f0>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x2b0 0x4>;
syscon = <&omap3_scm_general>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
gpio1: gpio@48310000 {
compatible = "ti,omap3-gpio";
reg = <0x48310000 0x200>;
interrupts = <29>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@49050000 {
compatible = "ti,omap3-gpio";
reg = <0x49050000 0x200>;
interrupts = <30>;
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@49052000 {
compatible = "ti,omap3-gpio";
reg = <0x49052000 0x200>;
interrupts = <31>;
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@49054000 {
compatible = "ti,omap3-gpio";
reg = <0x49054000 0x200>;
interrupts = <32>;
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@49056000 {
compatible = "ti,omap3-gpio";
reg = <0x49056000 0x200>;
interrupts = <33>;
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@49058000 {
compatible = "ti,omap3-gpio";
reg = <0x49058000 0x200>;
interrupts = <34>;
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart1: serial@4806a000 {
compatible = "ti,omap3-uart";
reg = <0x4806a000 0x2000>;
interrupts-extended = <&intc 72>;
dmas = <&sdma 49 &sdma 50>;
dma-names = "tx", "rx";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
};
uart2: serial@4806c000 {
compatible = "ti,omap3-uart";
reg = <0x4806c000 0x400>;
interrupts-extended = <&intc 73>;
dmas = <&sdma 51 &sdma 52>;
dma-names = "tx", "rx";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
};
uart3: serial@49020000 {
compatible = "ti,omap3-uart";
reg = <0x49020000 0x400>;
interrupts-extended = <&intc 74>;
dmas = <&sdma 53 &sdma 54>;
dma-names = "tx", "rx";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
};
i2c1: i2c@48070000 {
compatible = "ti,omap3-i2c";
reg = <0x48070000 0x80>;
interrupts = <56>;
dmas = <&sdma 27 &sdma 28>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
};
i2c2: i2c@48072000 {
compatible = "ti,omap3-i2c";
reg = <0x48072000 0x80>;
interrupts = <57>;
dmas = <&sdma 29 &sdma 30>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
};
i2c3: i2c@48060000 {
compatible = "ti,omap3-i2c";
reg = <0x48060000 0x80>;
interrupts = <61>;
dmas = <&sdma 25 &sdma 26>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
};
mailbox: mailbox@48094000 {
compatible = "ti,omap3-mailbox";
ti,hwmods = "mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>;
ti,mbox-num-users = <2>;
ti,mbox-num-fifos = <2>;
mbox_dsp: dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
};
mcspi1: spi@48098000 {
compatible = "ti,omap2-mcspi";
reg = <0x48098000 0x100>;
interrupts = <65>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
<&sdma 37>,
<&sdma 38>,
<&sdma 39>,
<&sdma 40>,
<&sdma 41>,
<&sdma 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
mcspi2: spi@4809a000 {
compatible = "ti,omap2-mcspi";
reg = <0x4809a000 0x100>;
interrupts = <66>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
<&sdma 45>,
<&sdma 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi3: spi@480b8000 {
compatible = "ti,omap2-mcspi";
reg = <0x480b8000 0x100>;
interrupts = <91>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>,
<&sdma 16>,
<&sdma 23>,
<&sdma 24>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi4: spi@480ba000 {
compatible = "ti,omap2-mcspi";
reg = <0x480ba000 0x100>;
interrupts = <48>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
};
hdqw1w: 1w@480b2000 {
compatible = "ti,omap3-1w";
reg = <0x480b2000 0x1000>;
interrupts = <58>;
ti,hwmods = "hdq1w";
};
mmc1: mmc@4809c000 {
compatible = "ti,omap3-hsmmc";
reg = <0x4809c000 0x200>;
interrupts = <83>;
ti,hwmods = "mmc1";
ti,dual-volt;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
pbias-supply = <&pbias_mmc_reg>;
};
mmc2: mmc@480b4000 {
compatible = "ti,omap3-hsmmc";
reg = <0x480b4000 0x200>;
interrupts = <86>;
ti,hwmods = "mmc2";
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
};
mmc3: mmc@480ad000 {
compatible = "ti,omap3-hsmmc";
reg = <0x480ad000 0x200>;
interrupts = <94>;
ti,hwmods = "mmc3";
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
};
mmu_isp: mmu@480bd400 {
compatible = "ti,omap2-iommu";
reg = <0x480bd400 0x80>;
interrupts = <24>;
ti,hwmods = "mmu_isp";
ti,#tlb-entries = <8>;
};
mmu_iva: mmu@5d000000 {
compatible = "ti,omap2-iommu";
reg = <0x5d000000 0x80>;
interrupts = <28>;
ti,hwmods = "mmu_iva";
status = "disabled";
};
wdt2: wdt@48314000 {
compatible = "ti,omap3-wdt";
reg = <0x48314000 0x80>;
ti,hwmods = "wd_timer2";
};
mcbsp1: mcbsp@48074000 {
compatible = "ti,omap3-mcbsp";
reg = <0x48074000 0xff>;
reg-names = "mpu";
interrupts = <16>, /* OCP compliant interrupt */
<59>, /* TX interrupt */
<60>; /* RX interrupt */
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
status = "disabled";
};
mcbsp2: mcbsp@49022000 {
compatible = "ti,omap3-mcbsp";
reg = <0x49022000 0xff>,
<0x49028000 0xff>;
reg-names = "mpu", "sidetone";
interrupts = <17>, /* OCP compliant interrupt */
<62>, /* TX interrupt */
<63>, /* RX interrupt */
<4>; /* Sidetone */
interrupt-names = "common", "tx", "rx", "sidetone";
ti,buffer-size = <1280>;
ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
status = "disabled";
};
mcbsp3: mcbsp@49024000 {
compatible = "ti,omap3-mcbsp";
reg = <0x49024000 0xff>,
<0x4902a000 0xff>;
reg-names = "mpu", "sidetone";
interrupts = <22>, /* OCP compliant interrupt */
<89>, /* TX interrupt */
<90>, /* RX interrupt */
<5>; /* Sidetone */
interrupt-names = "common", "tx", "rx", "sidetone";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
status = "disabled";
};
mcbsp4: mcbsp@49026000 {
compatible = "ti,omap3-mcbsp";
reg = <0x49026000 0xff>;
reg-names = "mpu";
interrupts = <23>, /* OCP compliant interrupt */
<54>, /* TX interrupt */
<55>; /* RX interrupt */
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
status = "disabled";
};
mcbsp5: mcbsp@48096000 {
compatible = "ti,omap3-mcbsp";
reg = <0x48096000 0xff>;
reg-names = "mpu";
interrupts = <27>, /* OCP compliant interrupt */
<81>, /* TX interrupt */
<82>; /* RX interrupt */
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp5";
dmas = <&sdma 21>,
<&sdma 22>;
dma-names = "tx", "rx";
status = "disabled";
};
sham: sham@480c3000 {
compatible = "ti,omap3-sham";
ti,hwmods = "sham";
reg = <0x480c3000 0x64>;
interrupts = <49>;
};
smartreflex_core: smartreflex@480cb000 {
compatible = "ti,omap3-smartreflex-core";
ti,hwmods = "smartreflex_core";
reg = <0x480cb000 0x400>;
interrupts = <19>;
};
smartreflex_mpu_iva: smartreflex@480c9000 {
compatible = "ti,omap3-smartreflex-iva";
ti,hwmods = "smartreflex_mpu_iva";
reg = <0x480c9000 0x400>;
interrupts = <18>;
};
timer1: timer@48318000 {
compatible = "ti,omap3430-timer";
reg = <0x48318000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
ti,timer-alwon;
};
timer2: timer@49032000 {
compatible = "ti,omap3430-timer";
reg = <0x49032000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
};
timer3: timer@49034000 {
compatible = "ti,omap3430-timer";
reg = <0x49034000 0x400>;
interrupts = <39>;
ti,hwmods = "timer3";
};
timer4: timer@49036000 {
compatible = "ti,omap3430-timer";
reg = <0x49036000 0x400>;
interrupts = <40>;
ti,hwmods = "timer4";
};
timer5: timer@49038000 {
compatible = "ti,omap3430-timer";
reg = <0x49038000 0x400>;
interrupts = <41>;
ti,hwmods = "timer5";
ti,timer-dsp;
};
timer6: timer@4903a000 {
compatible = "ti,omap3430-timer";
reg = <0x4903a000 0x400>;
interrupts = <42>;
ti,hwmods = "timer6";
ti,timer-dsp;
};
timer7: timer@4903c000 {
compatible = "ti,omap3430-timer";
reg = <0x4903c000 0x400>;
interrupts = <43>;
ti,hwmods = "timer7";
ti,timer-dsp;
};
timer8: timer@4903e000 {
compatible = "ti,omap3430-timer";
reg = <0x4903e000 0x400>;
interrupts = <44>;
ti,hwmods = "timer8";
ti,timer-pwm;
ti,timer-dsp;
};
timer9: timer@49040000 {
compatible = "ti,omap3430-timer";
reg = <0x49040000 0x400>;
interrupts = <45>;
ti,hwmods = "timer9";
ti,timer-pwm;
};
timer10: timer@48086000 {
compatible = "ti,omap3430-timer";
reg = <0x48086000 0x400>;
interrupts = <46>;
ti,hwmods = "timer10";
ti,timer-pwm;
};
timer11: timer@48088000 {
compatible = "ti,omap3430-timer";
reg = <0x48088000 0x400>;
interrupts = <47>;
ti,hwmods = "timer11";
ti,timer-pwm;
};
timer12: timer@48304000 {
compatible = "ti,omap3430-timer";
reg = <0x48304000 0x400>;
interrupts = <95>;
ti,hwmods = "timer12";
ti,timer-alwon;
ti,timer-secure;
};
usbhstll: usbhstll@48062000 {
compatible = "ti,usbhs-tll";
reg = <0x48062000 0x1000>;
interrupts = <78>;
ti,hwmods = "usb_tll_hs";
};
usbhshost: usbhshost@48064000 {
compatible = "ti,usbhs-host";
reg = <0x48064000 0x400>;
ti,hwmods = "usb_host_hs";
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbhsohci: ohci@48064400 {
compatible = "ti,ohci-omap3";
reg = <0x48064400 0x400>;
interrupt-parent = <&intc>;
interrupts = <76>;
};
usbhsehci: ehci@48064800 {
compatible = "ti,ehci-omap";
reg = <0x48064800 0x400>;
interrupt-parent = <&intc>;
interrupts = <77>;
};
};
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x02d0>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
};
usb_otg_hs: usb_otg_hs@480ab000 {
compatible = "ti,omap3-musb";
reg = <0x480ab000 0x1000>;
interrupts = <92>, <93>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
};
dss: dss@48050000 {
compatible = "ti,omap3-dss";
reg = <0x48050000 0x200>;
status = "disabled";
ti,hwmods = "dss_core";
clocks = <&dss1_alwon_fck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges;
dispc@48050400 {
compatible = "ti,omap3-dispc";
reg = <0x48050400 0x400>;
interrupts = <25>;
ti,hwmods = "dss_dispc";
clocks = <&dss1_alwon_fck>;
clock-names = "fck";
};
dsi: encoder@4804fc00 {
compatible = "ti,omap3-dsi";
reg = <0x4804fc00 0x200>,
<0x4804fe00 0x40>,
<0x4804ff00 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <25>;
status = "disabled";
ti,hwmods = "dss_dsi1";
clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
clock-names = "fck", "sys_clk";
};
rfbi: encoder@48050800 {
compatible = "ti,omap3-rfbi";
reg = <0x48050800 0x100>;
status = "disabled";
ti,hwmods = "dss_rfbi";
clocks = <&dss1_alwon_fck>, <&dss_ick>;
clock-names = "fck", "ick";
};
venc: encoder@48050c00 {
compatible = "ti,omap3-venc";
reg = <0x48050c00 0x100>;
status = "disabled";
ti,hwmods = "dss_venc";
clocks = <&dss_tv_fck>;
clock-names = "fck";
};
};
ssi: ssi-controller@48058000 {
compatible = "ti,omap3-ssi";
ti,hwmods = "ssi";
status = "disabled";
reg = <0x48058000 0x1000>,
<0x48059000 0x1000>;
reg-names = "sys",
"gdd";
interrupts = <71>;
interrupt-names = "gdd_mpu";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ssi_port1: ssi-port@4805a000 {
compatible = "ti,omap3-ssi-port";
reg = <0x4805a000 0x800>,
<0x4805a800 0x800>;
reg-names = "tx",
"rx";
interrupt-parent = <&intc>;
interrupts = <67>,
<68>;
};
ssi_port2: ssi-port@4805b000 {
compatible = "ti,omap3-ssi-port";
reg = <0x4805b000 0x800>,
<0x4805b800 0x800>;
reg-names = "tx",
"rx";
interrupt-parent = <&intc>;
interrupts = <69>,
<70>;
};
};
};
};
/include/ "omap3xxx-clocks.dtsi"

268
src/data/dts/arch/arm/omap34xx-omap36xx-clocks.dtsi
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@ -1,268 +0,0 @@
/*
* Device Tree Source for OMAP34XX/OMAP36XX clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_clocks {
security_l4_ick2: security_l4_ick2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
aes1_ick: aes1_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
ti,bit-shift = <3>;
reg = <0x0a14>;
};
rng_ick: rng_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x0a14>;
ti,bit-shift = <2>;
};
sha11_ick: sha11_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x0a14>;
ti,bit-shift = <1>;
};
des1_ick: des1_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
reg = <0x0a14>;
ti,bit-shift = <0>;
};
cam_mclk: cam_mclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m5x2_ck>;
ti,bit-shift = <0>;
reg = <0x0f00>;
ti,set-rate-parent;
};
cam_ick: cam_ick {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
reg = <0x0f10>;
ti,bit-shift = <0>;
};
csi2_96m_fck: csi2_96m_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
reg = <0x0f00>;
ti,bit-shift = <1>;
};
security_l3_ick: security_l3_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l3_ick>;
clock-mult = <1>;
clock-div = <1>;
};
pka_ick: pka_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l3_ick>;
reg = <0x0a14>;
ti,bit-shift = <4>;
};
icr_ick: icr_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <29>;
};
des2_ick: des2_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <26>;
};
mspro_ick: mspro_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <23>;
};
mailboxes_ick: mailboxes_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <7>;
};
ssi_l4_ick: ssi_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
sr1_fck: sr1_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
reg = <0x0c00>;
ti,bit-shift = <6>;
};
sr2_fck: sr2_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
reg = <0x0c00>;
ti,bit-shift = <7>;
};
sr_l4_ick: sr_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
dpll2_fck: dpll2_fck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
ti,bit-shift = <19>;
ti,max-div = <7>;
reg = <0x0040>;
ti,index-starts-at-one;
};
dpll2_ck: dpll2_ck {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll2_fck>;
reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
ti,low-power-stop;
ti,lock;
ti,low-power-bypass;
};
dpll2_m2_ck: dpll2_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll2_ck>;
ti,max-div = <31>;
reg = <0x0044>;
ti,index-starts-at-one;
};
iva2_ck: iva2_ck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll2_m2_ck>;
reg = <0x0000>;
ti,bit-shift = <0>;
};
modem_fck: modem_fck {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
reg = <0x0a00>;
ti,bit-shift = <31>;
};
sad2d_ick: sad2d_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <3>;
};
mad2d_ick: mad2d_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
reg = <0x0a18>;
ti,bit-shift = <3>;
};
mspro_fck: mspro_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
reg = <0x0a00>;
ti,bit-shift = <23>;
};
};
&cm_clockdomains {
cam_clkdm: cam_clkdm {
compatible = "ti,clockdomain";
clocks = <&cam_ick>, <&csi2_96m_fck>;
};
iva2_clkdm: iva2_clkdm {
compatible = "ti,clockdomain";
clocks = <&iva2_ck>;
};
dpll2_clkdm: dpll2_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll2_ck>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
};
d2d_clkdm: d2d_clkdm {
compatible = "ti,clockdomain";
clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
<&mspro_fck>;
};
};

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src/data/dts/arch/arm/omap34xx.dtsi
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/*
* Device Tree Source for OMAP34xx/OMAP35xx SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "omap3.dtsi"
/ {
cpus {
cpu@0 {
/* OMAP343x/OMAP35xx variants OPP1-5 */
operating-points = <
/* kHz uV */
125000 975000
250000 1075000
500000 1200000
550000 1270000
600000 1350000
>;
clock-latency = <300000>; /* From legacy driver */
};
};
ocp {
omap3_pmx_core2: pinmux@480025d8 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x480025d8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
};
};
&ssi {
status = "ok";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,
<&ssi_ick>;
clock-names = "ssi_ssr_fck",
"ssi_sst_fck",
"ssi_ick";
};
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"

242
src/data/dts/arch/arm/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
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@ -1,242 +0,0 @@
/*
* Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&prm_clocks {
corex2_d3_fck: corex2_d3_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&corex2_fck>;
clock-mult = <1>;
clock-div = <3>;
};
corex2_d5_fck: corex2_d5_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&corex2_fck>;
clock-mult = <1>;
clock-div = <5>;
};
};
&cm_clocks {
dpll5_ck: dpll5_ck {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
ti,low-power-stop;
ti,lock;
};
dpll5_m2_ck: dpll5_m2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll5_ck>;
ti,max-div = <31>;
reg = <0x0d50>;
ti,index-starts-at-one;
};
sgx_gate_fck: sgx_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
ti,bit-shift = <1>;
reg = <0x0b00>;
};
core_d3_ck: core_d3_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <3>;
};
core_d4_ck: core_d4_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <4>;
};
core_d6_ck: core_d6_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <6>;
};
omap_192m_alwon_fck: omap_192m_alwon_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll4_m2x2_ck>;
clock-mult = <1>;
clock-div = <1>;
};
core_d2_ck: core_d2_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&core_ck>;
clock-mult = <1>;
clock-div = <2>;
};
sgx_mux_fck: sgx_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
reg = <0x0b40>;
};
sgx_fck: sgx_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
};
sgx_ick: sgx_ick {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&l3_ick>;
reg = <0x0b10>;
ti,bit-shift = <0>;
};
cpefuse_fck: cpefuse_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
reg = <0x0a08>;
ti,bit-shift = <0>;
};
ts_fck: ts_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_32k_fck>;
reg = <0x0a08>;
ti,bit-shift = <1>;
};
usbtll_fck: usbtll_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll5_m2_ck>;
reg = <0x0a08>;
ti,bit-shift = <2>;
};
usbtll_ick: usbtll_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a18>;
ti,bit-shift = <2>;
};
mmchs3_ick: mmchs3_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <30>;
};
mmchs3_fck: mmchs3_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
reg = <0x0a00>;
ti,bit-shift = <30>;
};
dss1_alwon_fck: dss1_alwon_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
ti,bit-shift = <0>;
reg = <0x0e00>;
ti,set-rate-parent;
};
dss_ick: dss_ick_3430es2 {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
reg = <0x0e10>;
ti,bit-shift = <0>;
};
usbhost_120m_fck: usbhost_120m_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll5_m2_ck>;
reg = <0x1400>;
ti,bit-shift = <1>;
};
usbhost_48m_fck: usbhost_48m_fck {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&omap_48m_fck>;
reg = <0x1400>;
ti,bit-shift = <0>;
};
usbhost_ick: usbhost_ick {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
reg = <0x1410>;
ti,bit-shift = <0>;
};
};
&cm_clockdomains {
dpll5_clkdm: dpll5_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll5_ck>;
};
sgx_clkdm: sgx_clkdm {
compatible = "ti,clockdomain";
clocks = <&sgx_ick>;
};
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
<&dss1_alwon_fck>, <&dss_ick>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
};
usbhost_clkdm: usbhost_clkdm {
compatible = "ti,clockdomain";
clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
<&usbhost_ick>;
};
};

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src/data/dts/arch/arm/omap36xx-clocks.dtsi
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@ -1,110 +0,0 @@
/*
* Device Tree Source for OMAP36xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_clocks {
dpll4_ck: dpll4_ck {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-per-j-type-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
};
dpll4_m5x2_ck: dpll4_m5x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m5x2_mul_ck>;
ti,bit-shift = <0x1e>;
reg = <0x0d00>;
ti,set-rate-parent;
ti,set-bit-to-disable;
};
dpll4_m2x2_ck: dpll4_m2x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
ti,bit-shift = <0x1b>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
dpll3_m3x2_ck: dpll3_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll3_m3x2_mul_ck>;
ti,bit-shift = <0xc>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
dpll4_m3x2_ck: dpll4_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m3x2_mul_ck>;
ti,bit-shift = <0x1c>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
dpll4_m6x2_ck: dpll4_m6x2_ck {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m6x2_mul_ck>;
ti,bit-shift = <0x1f>;
reg = <0x0d00>;
ti,set-bit-to-disable;
};
uart4_fck: uart4_fck {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&per_48m_fck>;
reg = <0x1000>;
ti,bit-shift = <18>;
};
};
&dpll4_m2x2_mul_ck {
clock-mult = <1>;
};
&dpll4_m3x2_mul_ck {
clock-mult = <1>;
};
&dpll4_m4x2_mul_ck {
ti,clock-mult = <1>;
};
&dpll4_m5x2_mul_ck {
ti,clock-mult = <1>;
};
&dpll4_m6x2_mul_ck {
clock-mult = <1>;
};
&cm_clockdomains {
dpll4_clkdm: dpll4_clkdm {
compatible = "ti,clockdomain";
clocks = <&dpll4_ck>;
};
per_clkdm: per_clkdm {
compatible = "ti,clockdomain";
clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
<&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
<&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
<&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
<&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
<&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
<&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
<&mcbsp4_ick>, <&uart4_fck>;
};
};

198
src/data/dts/arch/arm/omap36xx-omap3430es2plus-clocks.dtsi
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@ -1,198 +0,0 @@
/*
* Device Tree Source for OMAP34xx/OMAP36xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cm_clocks {
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <0>;
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
ti,bit-shift = <8>;
reg = <0x0a40>;
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
};
ssi_ssr_fck: ssi_ssr_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
};
ssi_sst_fck: ssi_sst_fck_3430es2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&ssi_ssr_fck>;
clock-mult = <1>;
clock-div = <2>;
};
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
#clock-cells = <0>;
compatible = "ti,omap3-hsotgusb-interface-clock";
clocks = <&core_l3_ick>;
reg = <0x0a10>;
ti,bit-shift = <4>;
};
ssi_l4_ick: ssi_l4_ick {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&l4_ick>;
clock-mult = <1>;
clock-div = <1>;
};
ssi_ick: ssi_ick_3430es2 {
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clocks = <&ssi_l4_ick>;
reg = <0x0a10>;
ti,bit-shift = <0>;
};
usim_gate_fck: usim_gate_fck {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&omap_96m_fck>;
ti,bit-shift = <9>;
reg = <0x0c00>;
};
sys_d2_ck: sys_d2_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_ck>;
clock-mult = <1>;
clock-div = <2>;
};
omap_96m_d2_fck: omap_96m_d2_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <2>;
};
omap_96m_d4_fck: omap_96m_d4_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <4>;
};
omap_96m_d8_fck: omap_96m_d8_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <8>;
};
omap_96m_d10_fck: omap_96m_d10_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&omap_96m_fck>;
clock-mult = <1>;
clock-div = <10>;
};
dpll5_m2_d4_ck: dpll5_m2_d4_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <4>;
};
dpll5_m2_d8_ck: dpll5_m2_d8_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <8>;
};
dpll5_m2_d16_ck: dpll5_m2_d16_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <16>;
};
dpll5_m2_d20_ck: dpll5_m2_d20_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&dpll5_m2_ck>;
clock-mult = <1>;
clock-div = <20>;
};
usim_mux_fck: usim_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
ti,bit-shift = <3>;
reg = <0x0c40>;
ti,index-starts-at-one;
};
usim_fck: usim_fck {
#clock-cells = <0>;
compatible = "ti,composite-clock";
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
};
usim_ick: usim_ick {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
reg = <0x0c10>;
ti,bit-shift = <9>;
};
};
&cm_clockdomains {
core_l3_clkdm: core_l3_clkdm {
compatible = "ti,clockdomain";
clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
};
wkup_clkdm: wkup_clkdm {
compatible = "ti,clockdomain";
clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
<&gpt1_ick>, <&usim_ick>;
};
core_l4_clkdm: core_l4_clkdm {
compatible = "ti,clockdomain";
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
<&ssi_ick>;
};
};

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src/data/dts/arch/arm/omap36xx.dtsi
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/*
* Device Tree Source for OMAP3 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "omap3.dtsi"
/ {
aliases {
serial3 = &uart4;
};
cpus {
/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
cpu@0 {
operating-points = <
/* kHz uV */
300000 1012500
600000 1200000
800000 1325000
>;
clock-latency = <300000>; /* From legacy driver */
};
};
ocp {
uart4: serial@49042000 {
compatible = "ti,omap3-uart";
reg = <0x49042000 0x400>;
interrupts = <80>;
dmas = <&sdma 81 &sdma 82>;
dma-names = "tx", "rx";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
};
abb_mpu_iva: regulator-abb-mpu {
compatible = "ti,abb-v1";
regulator-name = "abb_mpu_iva";
#address-cell = <0>;
#size-cells = <0>;
reg = <0x483072f0 0x8>, <0x48306818 0x4>;
reg-names = "base-address", "int-address";
ti,tranxdone-status-mask = <0x4000000>;
clocks = <&sys_ck>;
ti,settling-time = <30>;
ti,clock-cycles = <8>;
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1012500 0 0 0 0 0
1200000 0 0 0 0 0
1325000 0 0 0 0 0
1375000 1 0 0 0 0
>;
};
omap3_pmx_core2: pinmux@480025a0 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x480025a0 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
};
};
/* OMAP3630 needs dss_96m_fck for VENC */
&venc {
clocks = <&dss_tv_fck>, <&dss_96m_fck>;
clock-names = "fck", "tv_dac_clk";
};
&ssi {
status = "ok";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,
<&ssi_ick>;
clock-names = "ssi_ssr_fck",
"ssi_sst_fck",
"ssi_ick";
};
/include/ "omap34xx-omap36xx-clocks.dtsi"
/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
/include/ "omap36xx-clocks.dtsi"

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src/data/dts/arch/arm/omap3xxx-clocks.dtsi
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src/data/dts/arch/arm/pxa27x.dtsi
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/* The pxa3xx skeleton simply augments the 2xx version */
/include/ "pxa2xx.dtsi"
/ {
model = "Marvell PXA27x familiy SoC";
compatible = "marvell,pxa27x";
pxabus {
pxairq: interrupt-controller@40d00000 {
marvell,intc-priority;
marvell,intc-nr-irqs = <34>;
};
};
};

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src/data/dts/arch/arm/pxa2xx.dtsi
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/*
* pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
model = "Marvell PXA2xx family SoC";
compatible = "marvell,pxa2xx";
interrupt-parent = <&pxairq>;
aliases {
serial0 = &ffuart;
serial1 = &btuart;
serial2 = &stuart;
serial3 = &hwuart;
/* i2c0 = &pwri2c; */
i2c1 = &pxai2c1;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "marvell,xscale";
device_type = "cpu";
};
};
pxabus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pxairq: interrupt-controller@40d00000 {
#interrupt-cells = <1>;
compatible = "marvell,pxa-intc";
interrupt-controller;
interrupt-parent;
marvell,intc-nr-irqs = <32>;
reg = <0x40d00000 0xd0>;
};
gpio: gpio@40e00000 {
compatible = "mrvl,pxa-gpio";
#address-cells = <0x1>;
#size-cells = <0x1>;
reg = <0x40e00000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
interrupts = <10>;
interrupt-names = "gpio_mux";
interrupt-controller;
#interrupt-cells = <0x2>;
ranges;
gcb0: gpio@40e00000 {
reg = <0x40e00000 0x4>;
};
gcb1: gpio@40e00004 {
reg = <0x40e00004 0x4>;
};
gcb2: gpio@40e00008 {
reg = <0x40e00008 0x4>;
};
gcb3: gpio@40e0000c {
reg = <0x40e0000c 0x4>;
};
};
ffuart: uart@40100000 {
compatible = "mrvl,pxa-uart";
reg = <0x40100000 0x30>;
interrupts = <22>;
status = "disabled";
};
btuart: uart@40200000 {
compatible = "mrvl,pxa-uart";
reg = <0x40200000 0x30>;
interrupts = <21>;
status = "disabled";
};
stuart: uart@40700000 {
compatible = "mrvl,pxa-uart";
reg = <0x40700000 0x30>;
interrupts = <20>;
status = "disabled";
};
hwuart: uart@41100000 {
compatible = "mrvl,pxa-uart";
reg = <0x41100000 0x30>;
interrupts = <7>;
status = "disabled";
};
pxai2c1: i2c@40301680 {
compatible = "mrvl,pxa-i2c";
reg = <0x40301680 0x30>;
interrupts = <18>;
#address-cells = <0x1>;
#size-cells = <0>;
status = "disabled";
};
usb0: ohci@4c000000 {
compatible = "mrvl,pxa-ohci";
reg = <0x4c000000 0x10000>;
interrupts = <3>;
status = "disabled";
};
mmc0: mmc@41100000 {
compatible = "mrvl,pxa-mmc";
reg = <0x41100000 0x1000>;
interrupts = <23>;
status = "disabled";
};
rtc@40900000 {
compatible = "marvell,pxa-rtc";
reg = <0x40900000 0x3c>;
interrupts = <30 31>;
};
};
};

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src/data/dts/arch/arm/rpi.dts
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/*
* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@bluezbox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/dts-v1/;
/include/ "bcm2835.dtsi"
/ {
model = "Raspberry Pi (BCM2835)";
compatible = "raspberrypi,model-a", "raspberrypi,model-b",
"broadcom,bcm2835-vc", "broadcom,bcm2708-vc";
memreserve = <0x08000000 0x08000000>; /* Set by VideoCore */
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,1176jzf-s";
device_type = "cpu";
reg = <0>; /* CPU ID=0 */
clock-frequency = <700000000>; /* 700MHz */
};
};
memory {
device_type = "memory";
reg = <0 0x8000000>; /* 128MB, Set by VideoCore */
};
system {
revision = <0>; /* Set by VideoCore */
serial = <0 0>; /* Set by VideoCore */
};
axi {
gpio: gpio {
/* BSC0 */
pins_bsc0_a: bsc0_a {
broadcom,function = "ALT0";
};
pins_bsc0_b: bsc0_b {
broadcom,function = "ALT0";
};
pins_bsc0_c: bsc0_c {
broadcom,function = "ALT1";
};
/* BSC1 */
pins_bsc1_a: bsc1_a {
broadcom,function = "ALT0";
};
pins_bsc1_b: bsc1_b {
broadcom,function = "ALT2";
};
/* GPCLK0 */
pins_gpclk0_a: gpclk0_a {
broadcom,function = "ALT0";
};
pins_gpclk0_b: gpclk0_b {
broadcom,function = "ALT5";
};
pins_gpclk0_c: gpclk0_c {
broadcom,function = "ALT0";
};
pins_gpclk0_d: gpclk0_d {
broadcom,function = "ALT0";
};
/* GPCLK1 */
pins_gpclk1_a: gpclk1_a {
broadcom,function = "ALT0";
};
pins_gpclk1_b: gpclk1_b {
broadcom,function = "ALT5";
};
pins_gpclk1_c: gpclk1_c {
broadcom,function = "ALT0";
};
pins_gpclk1_d: gpclk1_d {
broadcom,function = "ALT0";
};
/* GPCLK2 */
pins_gpclk2_a: gpclk2_a {
broadcom,function = "ALT0";
};
pins_gpclk2_b: gpclk2_b {
broadcom,function = "ALT0";
};
/* SPI0 */
pins_spi0_a: spi0_a {
broadcom,function = "ALT0";
};
pins_spi0_b: spi0_b {
broadcom,function = "ALT0";
};
/* PWM */
pins_pwm0_a: pwm0_a {
broadcom,function = "ALT0";
};
pins_pwm0_b: pwm0_b {
broadcom,function = "ALT5";
};
pins_pwm0_c: pwm0_c {
broadcom,function = "ALT0";
};
pins_pwm1_a: pwm1_a {
broadcom,function = "ALT0";
};
pins_pwm1_b: pwm1_b {
broadcom,function = "ALT5";
};
pins_pwm1_c: pwm1_c {
broadcom,function = "ALT0";
};
pins_pwm1_d: pwm1_d {
broadcom,function = "ALT0";
};
/* UART0 */
pins_uart0_a: uart0_a {
broadcom,function = "ALT0";
};
pins_uart0_b: uart0_b {
broadcom,function = "ALT3";
};
pins_uart0_c: uart0_c {
broadcom,function = "ALT2";
};
pins_uart0_fc_a: uart0_fc_a {
broadcom,function = "ALT3";
};
pins_uart0_fc_b: uart0_fc_b {
broadcom,function = "ALT3";
};
pins_uart0_fc_c: uart0_fc_c {
broadcom,function = "ALT2";
};
/* PCM */
pins_pcm_a: pcm_a {
broadcom,function = "ALT0";
};
pins_pcm_b: pcm_b {
broadcom,function = "ALT2";
};
/* Secondary Address Bus */
pins_sm_addr_a: sm_addr_a {
broadcom,function = "ALT1";
};
pins_sm_addr_b: sm_addr_b {
broadcom,function = "ALT1";
};
pins_sm_ctl_a: sm_ctl_a {
broadcom,function = "ALT1";
};
pins_sm_ctl_b: sm_ctl_b {
broadcom,function = "ALT1";
};
pins_sm_data_8bit_a: sm_data_8bit_a {
broadcom,function = "ALT1";
};
pins_sm_data_8bit_b: sm_data_8bit_b {
broadcom,function = "ALT1";
};
pins_sm_data_16bit: sm_data_16bit {
broadcom,function = "ALT1";
};
pins_sm_data_18bit: sm_data_18bit {
broadcom,function = "ALT1";
};
/* BSCSL */
pins_bscsl: bscsl {
broadcom,function = "ALT3";
};
/* SPISL */
pins_spisl: spisl {
broadcom,function = "ALT3";
};
/* SPI1 */
pins_spi1: spi1 {
broadcom,function = "ALT4";
};
/* UART1 */
pins_uart1_a: uart1_a {
broadcom,function = "ALT5";
};
pins_uart1_b: uart1_b {
broadcom,function = "ALT5";
};
pins_uart1_c: uart1_c {
broadcom,function = "ALT5";
};
pins_uart1_fc_a: uart1_fc_a {
broadcom,function = "ALT5";
};
pins_uart1_fc_b: uart1_fc_b {
broadcom,function = "ALT5";
};
pins_uart1_fc_c: uart1_fc_c {
broadcom,function = "ALT5";
};
/* SPI2 */
pins_spi2: spi2 {
broadcom,function = "ALT4";
};
/* ARM JTAG */
pins_arm_jtag_trst: arm_jtag_trst {
broadcom,function = "ALT4";
};
pins_arm_jtag_a: arm_jtag_a {
broadcom,function = "ALT5";
};
pins_arm_jtag_b: arm_jtag_b {
broadcom,function = "ALT4";
};
/* Reserved */
pins_reserved: reserved {
broadcom,function = "ALT3";
};
};
usb {
hub {
compatible = "usb,hub", "usb,device";
reg = <0x00000001>;
#address-cells = <1>;
#size-cells = <0>;
ethernet {
compatible = "net,ethernet",
"usb,device";
reg = <0x00000001>;
mac-address = [00 00 00 00 00 00];
};
};
};
};
display {
compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb";
broadcom,vc-mailbox = <&vc_mbox>;
broadcom,vc-channel = <1>;
broadcom,width = <0>; /* Set by VideoCore */
broadcom,height = <0>; /* Set by VideoCore */
broadcom,depth = <0>; /* Set by VideoCore */
};
leds {
compatible = "gpio-leds";
ok {
label = "ok";
gpios = <&gpio 16 1>;
/* Don't change this - it configures
* how the led driver determines if
* the led is on or off when it loads.
*/
default-state = "keep";
/* This is the real default state. */
linux,default-trigger = "default-on";
};
};
power: regulator {
compatible = "broadcom,bcm2835-power-mgr",
"broadcom,bcm2708-power-mgr",
"simple-bus";
#address-cells = <1>;
#size-cells = <0>;
broadcom,vc-mailbox = <&vc_mbox>;
broadcom,vc-channel = <0>;
regulator-name = "VideoCore";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on = <1>;
sd_card_power: regulator@0 {
compatible = "broadcom,bcm2835-power-dev",
"broadcom,bcm2708-power-dev";
reg = <0>;
vin-supply = <&power>;
regulator-name = "SD Card";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/* This is for the controller itself, not the root port */
usb_hcd_power: regulator@3 {
compatible = "broadcom,bcm2835-power-dev",
"broadcom,bcm2708-power-dev";
reg = <3>;
vin-supply = <&power>;
regulator-name = "USB HCD";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
aliases {
uart0 = &uart0;
};
chosen {
bootargs = ""; /* Set by VideoCore */
stdin = "uart0";
stdout = "uart0";
};
__overrides__ {
cache_line_size = <&vchiq>, "cache-line-size:0";
};
};

406
src/data/dts/arch/arm/rpi2.dts
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@ -1,406 +0,0 @@
/*
* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@bluezbox.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/dts-v1/;
/include/ "bcm2836.dtsi"
/ {
model = "Raspberry Pi 2 Model B";
compatible = "brcm,bcm2709";
memreserve = <0x08000000 0x08000000>; /* Set by VideoCore */
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>; /* CPU ID=0xf00 */
clock-frequency = <800000000>; /* 800MHz */
};
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>; /* CPU ID=0xf01 */
clock-frequency = <800000000>; /* 800MHz */
};
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf02>; /* CPU ID=0xf02 */
clock-frequency = <800000000>; /* 800MHz */
};
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf03>; /* CPU ID=0xf03 */
clock-frequency = <800000000>; /* 800MHz */
};
};
memory {
device_type = "memory";
reg = <0 0x8000000>; /* 128MB, Set by VideoCore */
};
system {
revision = <0>; /* Set by VideoCore */
serial = <0 0>; /* Set by VideoCore */
};
axi {
gpio: gpio {
/* BSC0 */
pins_bsc0_a: bsc0_a {
broadcom,function = "ALT0";
};
pins_bsc0_b: bsc0_b {
broadcom,function = "ALT0";
};
pins_bsc0_c: bsc0_c {
broadcom,function = "ALT1";
};
/* BSC1 */
pins_bsc1_a: bsc1_a {
broadcom,function = "ALT0";
};
pins_bsc1_b: bsc1_b {
broadcom,function = "ALT2";
};
/* GPCLK0 */
pins_gpclk0_a: gpclk0_a {
broadcom,function = "ALT0";
};
pins_gpclk0_b: gpclk0_b {
broadcom,function = "ALT5";
};
pins_gpclk0_c: gpclk0_c {
broadcom,function = "ALT0";
};
pins_gpclk0_d: gpclk0_d {
broadcom,function = "ALT0";
};
/* GPCLK1 */
pins_gpclk1_a: gpclk1_a {
broadcom,function = "ALT0";
};
pins_gpclk1_b: gpclk1_b {
broadcom,function = "ALT5";
};
pins_gpclk1_c: gpclk1_c {
broadcom,function = "ALT0";
};
pins_gpclk1_d: gpclk1_d {
broadcom,function = "ALT0";
};
/* GPCLK2 */
pins_gpclk2_a: gpclk2_a {
broadcom,function = "ALT0";
};
pins_gpclk2_b: gpclk2_b {
broadcom,function = "ALT0";
};
/* SPI0 */
pins_spi0_a: spi0_a {
broadcom,function = "ALT0";
};
pins_spi0_b: spi0_b {
broadcom,function = "ALT0";
};
/* PWM */
pins_pwm0_a: pwm0_a {
broadcom,function = "ALT0";
};
pins_pwm0_b: pwm0_b {
broadcom,function = "ALT5";
};
pins_pwm0_c: pwm0_c {
broadcom,function = "ALT0";
};
pins_pwm1_a: pwm1_a {
broadcom,function = "ALT0";
};
pins_pwm1_b: pwm1_b {
broadcom,function = "ALT5";
};
pins_pwm1_c: pwm1_c {
broadcom,function = "ALT0";
};
pins_pwm1_d: pwm1_d {
broadcom,function = "ALT0";
};
/* UART0 */
pins_uart0_a: uart0_a {
broadcom,function = "ALT0";
};
pins_uart0_b: uart0_b {
broadcom,function = "ALT3";
};
pins_uart0_c: uart0_c {
broadcom,function = "ALT2";
};
pins_uart0_fc_a: uart0_fc_a {
broadcom,function = "ALT3";
};
pins_uart0_fc_b: uart0_fc_b {
broadcom,function = "ALT3";
};
pins_uart0_fc_c: uart0_fc_c {
broadcom,function = "ALT2";
};
/* PCM */
pins_pcm_a: pcm_a {
broadcom,function = "ALT0";
};
pins_pcm_b: pcm_b {
broadcom,function = "ALT2";
};
/* Secondary Address Bus */
pins_sm_addr_a: sm_addr_a {
broadcom,function = "ALT1";
};
pins_sm_addr_b: sm_addr_b {
broadcom,function = "ALT1";
};
pins_sm_ctl_a: sm_ctl_a {
broadcom,function = "ALT1";
};
pins_sm_ctl_b: sm_ctl_b {
broadcom,function = "ALT1";
};
pins_sm_data_8bit_a: sm_data_8bit_a {
broadcom,function = "ALT1";
};
pins_sm_data_8bit_b: sm_data_8bit_b {
broadcom,function = "ALT1";
};
pins_sm_data_16bit: sm_data_16bit {
broadcom,function = "ALT1";
};
pins_sm_data_18bit: sm_data_18bit {
broadcom,function = "ALT1";
};
/* BSCSL */
pins_bscsl: bscsl {
broadcom,function = "ALT3";
};
/* SPISL */
pins_spisl: spisl {
broadcom,function = "ALT3";
};
/* SPI1 */
pins_spi1: spi1 {
broadcom,function = "ALT4";
};
/* UART1 */
pins_uart1_a: uart1_a {
broadcom,function = "ALT5";
};
pins_uart1_b: uart1_b {
broadcom,function = "ALT5";
};
pins_uart1_c: uart1_c {
broadcom,function = "ALT5";
};
pins_uart1_fc_a: uart1_fc_a {
broadcom,function = "ALT5";
};
pins_uart1_fc_b: uart1_fc_b {
broadcom,function = "ALT5";
};
pins_uart1_fc_c: uart1_fc_c {
broadcom,function = "ALT5";
};
/* SPI2 */
pins_spi2: spi2 {
broadcom,function = "ALT4";
};
/* ARM JTAG */
pins_arm_jtag_trst: arm_jtag_trst {
broadcom,function = "ALT4";
};
pins_arm_jtag_a: arm_jtag_a {
broadcom,function = "ALT5";
};
pins_arm_jtag_b: arm_jtag_b {
broadcom,function = "ALT4";
};
/* Reserved */
pins_reserved: reserved {
broadcom,function = "ALT3";
};
};
usb {
hub {
compatible = "usb,hub", "usb,device";
reg = <0x00000001>;
#address-cells = <1>;
#size-cells = <0>;
ethernet {
compatible = "net,ethernet",
"usb,device";
reg = <0x00000001>;
mac-address = [00 00 00 00 00 00];
};
};
};
};
display {
compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb";
broadcom,vc-mailbox = <&vc_mbox>;
broadcom,vc-channel = <1>;
broadcom,width = <0>; /* Set by VideoCore */
broadcom,height = <0>; /* Set by VideoCore */
broadcom,depth = <0>; /* Set by VideoCore */
};
leds {
compatible = "gpio-leds";
pwr {
label = "pwr";
gpios = <&gpio 35 0>;
};
act {
label = "act";
gpios = <&gpio 47 0>;
};
};
power: regulator {
compatible = "broadcom,bcm2835-power-mgr",
"broadcom,bcm2708-power-mgr",
"simple-bus";
#address-cells = <1>;
#size-cells = <0>;
broadcom,vc-mailbox = <&vc_mbox>;
broadcom,vc-channel = <0>;
regulator-name = "VideoCore";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on = <1>;
sd_card_power: regulator@0 {
compatible = "broadcom,bcm2835-power-dev",
"broadcom,bcm2708-power-dev";
reg = <0>;
vin-supply = <&power>;
regulator-name = "SD Card";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/* This is for the controller itself, not the root port */
usb_hcd_power: regulator@3 {
compatible = "broadcom,bcm2835-power-dev",
"broadcom,bcm2708-power-dev";
reg = <3>;
vin-supply = <&power>;
regulator-name = "USB HCD";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
aliases {
uart0 = &uart0;
};
chosen {
bootargs = ""; /* Set by VideoCore */
stdin = "uart0";
stdout = "uart0";
};
__overrides__ {
cache_line_size = <&vchiq>, "cache-line-size:0";
};
};

13
src/data/dts/arch/arm/skeleton.dtsi
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@ -1,13 +0,0 @@
/*
* Skeleton device tree; the bare minimum needed to boot; just include and
* add a compatible value. The bootloader will typically populate the memory
* node.
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
memory { device_type = "memory"; reg = <0 0>; };
};

133
src/data/dts/arch/arm/sun4i-a10.dtsi
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@ -1,133 +0,0 @@
/*-
* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
compatible = "allwinner,sun4i-a10";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&AINTC>;
aliases {
soc = &SOC;
};
SOC: a10 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
bus-frequency = <0>;
AINTC: interrupt-controller@01c20400 {
compatible = "allwinner,sun4i-ic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
reg = < 0x01c20400 0x400 >;
};
sramc@01c00000 {
compatible = "allwinner,sun4i-sramc";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x01c00000 0x1000 >;
};
ccm@01c20000 {
compatible = "allwinner,sun4i-ccm";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x01c20000 0x400 >;
};
timer@01c20c00 {
compatible = "allwinner,sun4i-timer";
reg = <0x01c20c00 0x90>;
interrupts = < 22 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 24000000 >;
};
watchdog@01c20c90 {
compatible = "allwinner,sun4i-wdt";
reg = <0x01c20c90 0x08>;
};
GPIO: gpio@01c20800 {
#gpio-cells = <3>;
compatible = "allwinner,sun4i-gpio";
gpio-controller;
reg =< 0x01c20800 0x400 >;
interrupts = < 28 >;
interrupt-parent = <&AINTC>;
};
usb1: usb@01c14000 {
compatible = "allwinner,usb-ehci", "usb-ehci";
reg = <0x01c14000 0x1000>;
interrupts = < 39 >;
interrupt-parent = <&AINTC>;
};
usb2: usb@01c1c000 {
compatible = "allwinner,usb-ehci", "usb-ehci";
reg = <0x01c1c000 0x1000>;
interrupts = < 40 >;
interrupt-parent = <&AINTC>;
};
sata@01c18000 {
compatible = "allwinner,sun4i-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <56>;
interrupt-parent = <&AINTC>;
};
UART0: serial@01c28000 {
compatible = "ns16550";
reg = <0x01c28000 0x400>;
reg-shift = <2>;
interrupts = <1>;
interrupt-parent = <&AINTC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
broken-txfifo = <1>;
};
emac@01c0b000 {
compatible = "allwinner,sun4i-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
interrupt-parent = <&AINTC>;
};
};
};

139
src/data/dts/arch/arm/sun7i-a20.dtsi
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@ -1,139 +0,0 @@
/*-
* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/ {
compatible = "allwinner,sun7i-a20";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&GIC>;
aliases {
soc = &SOC;
};
SOC: a20 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
bus-frequency = <0>;
GIC: interrupt-controller@01c81000 {
compatible = "arm,gic";
reg = <0x01c81000 0x1000>, /* Distributor Registers */
<0x01c82000 0x0100>; /* CPU Interface Registers */
interrupt-controller;
#interrupt-cells = <1>;
};
sramc@01c00000 {
compatible = "allwinner,sun4i-sramc";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x01c00000 0x1000 >;
};
cpu-cfg@01c25c00 {
compatible = "allwinner,sun7i-cpu-cfg";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x01c25c00 0x400 >;
};
ccm@01c20000 {
compatible = "allwinner,sun4i-ccm";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x01c20000 0x400 >;
};
timer@01c20c00 {
compatible = "allwinner,sun7i-timer";
reg = <0x01c20c00 0x90>;
interrupts = < 22 >;
interrupt-parent = <&GIC>;
clock-frequency = < 24000000 >;
};
watchdog@01c20c90 {
compatible = "allwinner,sun4i-wdt";
reg = <0x01c20c90 0x10>;
};
GPIO: gpio@01c20800 {
#gpio-cells = <3>;
compatible = "allwinner,sun4i-gpio";
gpio-controller;
reg =< 0x01c20800 0x400 >;
interrupts = < 28 >;
interrupt-parent = <&GIC>;
};
usb1: usb@01c14000 {
compatible = "allwinner,usb-ehci", "usb-ehci";
reg = <0x01c14000 0x1000>;
interrupts = < 39 >;
interrupt-parent = <&GIC>;
};
usb2: usb@01c1c000 {
compatible = "allwinner,usb-ehci", "usb-ehci";
reg = <0x01c1c000 0x1000>;
interrupts = < 40 >;
interrupt-parent = <&GIC>;
};
sata@01c18000 {
compatible = "allwinner,sun4i-a10-ahci";
reg = <0x01c18000 0x1000>;
interrupts = <56>;
interrupt-parent = <&GIC>;
};
UART0: serial@01c28000 {
compatible = "ns16550";
reg = <0x01c28000 0x400>;
reg-shift = <2>;
interrupts = <1>;
interrupt-parent = <&GIC>;
current-speed = <115200>;
clock-frequency = < 24000000 >;
busy-detect = <1>;
broken-txfifo = <1>;
};
emac@01c0b000 {
compatible = "allwinner,sun4i-emac";
reg = <0x01c0b000 0x1000>;
interrupts = <55>;
interrupt-parent = <&GIC>;
};
};
};

161
src/data/dts/arch/arm/twl4030.dtsi
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@ -1,161 +0,0 @@
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Integrated Power Management Chip
*/
&twl {
compatible = "ti,twl4030";
interrupt-controller;
#interrupt-cells = <1>;
rtc {
compatible = "ti,twl4030-rtc";
interrupts = <11>;
};
charger: bci {
compatible = "ti,twl4030-bci";
interrupts = <9>, <2>;
bci3v1-supply = <&vusb3v1>;
};
watchdog {
compatible = "ti,twl4030-wdt";
};
vaux1: regulator-vaux1 {
compatible = "ti,twl4030-vaux1";
};
vaux2: regulator-vaux2 {
compatible = "ti,twl4030-vaux2";
};
vaux3: regulator-vaux3 {
compatible = "ti,twl4030-vaux3";
};
vaux4: regulator-vaux4 {
compatible = "ti,twl4030-vaux4";
};
vcc: regulator-vdd1 {
compatible = "ti,twl4030-vdd1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1450000>;
};
vdac: regulator-vdac {
compatible = "ti,twl4030-vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vio: regulator-vio {
compatible = "ti,twl4030-vio";
};
vintana1: regulator-vintana1 {
compatible = "ti,twl4030-vintana1";
};
vintana2: regulator-vintana2 {
compatible = "ti,twl4030-vintana2";
};
vintdig: regulator-vintdig {
compatible = "ti,twl4030-vintdig";
};
vmmc1: regulator-vmmc1 {
compatible = "ti,twl4030-vmmc1";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <3150000>;
};
vmmc2: regulator-vmmc2 {
compatible = "ti,twl4030-vmmc2";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <3150000>;
};
vusb1v5: regulator-vusb1v5 {
compatible = "ti,twl4030-vusb1v5";
};
vusb1v8: regulator-vusb1v8 {
compatible = "ti,twl4030-vusb1v8";
};
vusb3v1: regulator-vusb3v1 {
compatible = "ti,twl4030-vusb3v1";
};
vpll1: regulator-vpll1 {
compatible = "ti,twl4030-vpll1";
};
vpll2: regulator-vpll2 {
compatible = "ti,twl4030-vpll2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vsim: regulator-vsim {
compatible = "ti,twl4030-vsim";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
twl_gpio: gpio {
compatible = "ti,twl4030-gpio";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
usb2_phy: twl4030-usb {
compatible = "ti,twl4030-usb";
interrupts = <10>, <4>;
usb1v5-supply = <&vusb1v5>;
usb1v8-supply = <&vusb1v8>;
usb3v1-supply = <&vusb3v1>;
usb_mode = <1>;
#phy-cells = <0>;
};
twl_pwm: pwm {
compatible = "ti,twl4030-pwm";
#pwm-cells = <2>;
};
twl_pwmled: pwmled {
compatible = "ti,twl4030-pwmled";
#pwm-cells = <2>;
};
twl_pwrbutton: pwrbutton {
compatible = "ti,twl4030-pwrbutton";
interrupts = <8>;
};
twl_keypad: keypad {
compatible = "ti,twl4030-keypad";
interrupts = <1>;
keypad,num-rows = <8>;
keypad,num-columns = <8>;
};
twl_madc: madc {
compatible = "ti,twl4030-madc";
interrupts = <3>;
#io-channel-cells = <1>;
};
};

42
src/data/dts/arch/arm/twl4030_omap3.dtsi
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@ -1,42 +0,0 @@
/*
* Copyright (C) 2013 Linaro, Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&twl {
pinctrl-names = "default";
pinctrl-0 = <&twl4030_pins &twl4030_vpins>;
};
&omap3_pmx_core {
/*
* On most OMAP3 platforms, the twl4030 IRQ line is connected
* to the SYS_NIRQ line on OMAP. Therefore, configure the
* defaults for the SYS_NIRQ pin here.
*/
twl4030_pins: pinmux_twl4030_pins {
pinctrl-single,pins = <
0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
>;
};
};
/*
* If your board is not using the I2C4 pins with twl4030, then don't include
* this file. For proper idle mode signaling with sys_clkreq and sys_off_mode
* pins we need to configure I2C4, or else use the legacy sys_nvmode1 and
* sys_nvmode2 signaling.
*/
&omap3_pmx_wkup {
twl4030_vpins: pinmux_twl4030_vpins {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0) /* i2c4_scl.i2c4_scl */
OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0) /* i2c4_sda.i2c4_sda */
OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0) /* sys_clkreq.sys_clkreq */
OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0) /* sys_off_mode.sys_off_mode */
>;
};
};

41
src/data/dts/arch/arm/verdex.dts
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@ -1,41 +0,0 @@
/dts-v1/;
/include/ "pxa27x.dtsi"
/ {
model = "Gumstix Verdex";
compatible = "gumstix,verdex", "marvell,pxa27x";
chosen {
bootargs = "console=ttyS0,115200 debug";
};
memory {
reg = <0xa0000000 0x10000000>;
};
pxabus {
ffuart: uart@40100000 {
status = "okay";
};
usb0: ohci@4c000000 {
status = "okay";
};
/* The devices below should be in pxa27x.dtsi, but I kept them here
so to keep the files from upstream as clean as possible for now */
lcdc: lcdc@44000000 {
compatible = "mrvl,pxa-lcdc" ;
reg = <0x44000000 0xa0> ;
interrupts = <17> ;
};
timers: timers@40a00000 {
compatible = "mrvl,pxa-timers" ;
reg = <0x40a00000 0xc0> ;
interrupts = <26>, <27>, <28>, <29>, <7> ;
interrupt-names = "OST_0", "OST_1", "OST_2", "OST_3", "OST_4_11" ;
};
};
};

15
src/data/dts/dt-bindings/gpio/gpio.h
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@ -1,15 +0,0 @@
/*
* This header provides constants for most GPIO bindings.
*
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_GPIO_GPIO_H
#define _DT_BINDINGS_GPIO_GPIO_H
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
#endif

19
src/data/dts/dt-bindings/interrupt-controller/irq.h
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/*
* This header provides constants for most IRQ bindings.
*
* Most IRQ bindings include a flags cell as part of the IRQ specifier.
* In most cases, the format of the flags cell uses the standard values
* defined in this header.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISING 1
#define IRQ_TYPE_EDGE_FALLING 2
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
#endif

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src/data/dts/dt-bindings/pinctrl/omap.h
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/*
* This header provides constants for OMAP pinctrl bindings.
*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009-2010 Texas Instruments
*/
#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
#define _DT_BINDINGS_PINCTRL_OMAP_H
/* 34xx mux mode options for each pin. See TRM for options */
#define MUX_MODE0 0
#define MUX_MODE1 1
#define MUX_MODE2 2
#define MUX_MODE3 3
#define MUX_MODE4 4
#define MUX_MODE5 5
#define MUX_MODE6 6
#define MUX_MODE7 7
/* 24xx/34xx mux bit defines */
#define PULL_ENA (1 << 3)
#define PULL_UP (1 << 4)
#define ALTELECTRICALSEL (1 << 5)
/* omap3/4/5 specific mux bit defines */
#define INPUT_EN (1 << 8)
#define OFF_EN (1 << 9)
#define OFFOUT_EN (1 << 10)
#define OFFOUT_VAL (1 << 11)
#define OFF_PULL_EN (1 << 12)
#define OFF_PULL_UP (1 << 13)
#define WAKEUP_EN (1 << 14)
#define WAKEUP_EVENT (1 << 15)
/* Active pin states */
#define PIN_OUTPUT 0
#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
#define PIN_INPUT INPUT_EN
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
/* Off mode states */
#define PIN_OFF_NONE 0
#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
/*
* Macros to allow using the absolute physical address instead of the
* padconf registers instead of the offset from padconf base.
*/
#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
/*
* Macros to allow using the offset from the padconf physical address
* instead of the offset from padconf base.
*/
#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
/*
* Define some commonly used pins configured by the boards.
* Note that some boards use alternative pins, so check
* the schematics before using these.
*/
#define OMAP3_UART1_RX 0x152
#define OMAP3_UART2_RX 0x14a
#define OMAP3_UART3_RX 0x16e
#define OMAP4_UART2_RX 0xdc
#define OMAP4_UART3_RX 0x104
#define OMAP4_UART4_RX 0x11c
#endif