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Accelerants: Fix -Wformat-overflow

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* Use strlcpy() and strlcat() instead of sprintf()
  to suppress -Wformat-overflow pointed by gcc8.
* Add <string.h> to mga_std.h for strlcpy() and strlcat().

Change-Id: Ib038283fd213c9e0ac9f19482402b55d2e3f204a
Reviewed-on: https://review.haiku-os.org/429
Reviewed-by: waddlesplash <waddlesplash@gmail.com>
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
This commit is contained in:
Murai Takashi 2018-08-04 21:43:43 +09:00 committed by waddlesplash
parent 5301f108ef
commit 8d86b84d18
5 changed files with 43 additions and 42 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/add-ons/accelerants/matrox/engine/mga_crtc.c
View File

@ -286,37 +286,37 @@ status_t gx00_crtc_dpms(bool display, bool h, bool v) // MIL2
{
char msg[100];
sprintf(msg, "CRTC: setting DPMS: ");
strlcpy(msg, "CRTC: setting DPMS: ", sizeof(msg));
if (display)
{
VGAW_I(SEQ,1, 0x00);
sprintf(msg, "%sdisplay on, ", msg);
strlcat(msg, "display on, ", sizeof(msg));
}
else
{
VGAW_I(SEQ,1, 0x20);
sprintf(msg, "%sdisplay off, ", msg);
strlcat(msg, "display off, ", sizeof(msg));
}
if (h)
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) & 0xef));
sprintf(msg, "%shsync enabled, ", msg);
strlcat(msg, "hsync enabled, ", sizeof(msg));
}
else
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) | 0x10));
sprintf(msg, "%shsync disabled, ", msg);
strlcat(msg, "hsync disabled, ", sizeof(msg));
}
if (v)
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) & 0xdf));
sprintf(msg, "%svsync enabled\n", msg);
strlcat(msg, "vsync enabled\n", sizeof(msg));
}
else
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) | 0x20));
sprintf(msg, "%svsync disabled\n", msg);
strlcat(msg, "vsync disabled\n", sizeof(msg));
}
LOG(4, (msg));

26
src/add-ons/accelerants/matrox/engine/mga_crtc2.c
View File

@ -161,7 +161,7 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
char msg[100];
sprintf(msg, "CRTC2: setting DPMS: ");
strlcpy(msg, "CRTC2: setting DPMS: ", sizeof(msg));
if (si->ps.card_type <= G400MAX)
{
@ -169,13 +169,13 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable CRTC2 and don't touch the rest */
CR2W(CTL, ((CR2R(CTL) & 0xFFF0177E) | 0x01));
sprintf(msg, "%sdisplay on, hsync enabled, vsync enabled\n", msg);
strlcat(msg, "display on, hsync enabled, vsync enabled\n", sizeof(msg));
}
else
{
/* disable CRTC2 and don't touch the rest */
CR2W(CTL, (CR2R(CTL) & 0xFFF0177E));
sprintf(msg, "%sdisplay off, hsync disabled, vsync disabled\n", msg);
strlcat(msg, "display off, hsync disabled, vsync disabled\n", sizeof(msg));
}
LOG(4, (msg));
@ -194,13 +194,13 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable CRTC2 and don't touch the rest */
CR2W(CTL, ((CR2R(CTL) & 0xFFF0177E) | 0x01));
sprintf(msg, "%sdisplay on, ", msg);
strlcat(msg, "display on, ", sizeof(msg));
}
else
{
/* disable CRTC2 and don't touch the rest */
CR2W(CTL, (CR2R(CTL) & 0xFFF0177E));
sprintf(msg, "%sdisplay off, ", msg);
strlcat(msg, "display off, ", sizeof(msg));
}
if (si->crossed_conns)
@ -209,25 +209,25 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable DVI-A hsync */
temp &= ~0x01;
sprintf(msg, "%shsync enabled, ", msg);
strlcat(msg, "hsync enabled, ", sizeof(msg));
}
else
{
/* disable DVI-A hsync */
temp |= 0x01;
sprintf(msg, "%shsync disabled, ", msg);
strlcat(msg, "hsync disabled, ", sizeof(msg));
}
if (v)
{
/* enable DVI-A vsync */
temp &= ~0x02;
sprintf(msg, "%svsync enabled\n", msg);
strlcat(msg, "vsync enabled\n", sizeof(msg));
}
else
{
/* disable DVI-A vsync */
temp |= 0x02;
sprintf(msg, "%svsync disabled\n", msg);
strlcat(msg, "vsync disabled\n", sizeof(msg));
}
}
else
@ -236,25 +236,25 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable HD15 hsync */
temp &= ~0x10;
sprintf(msg, "%shsync enabled, ", msg);
strlcat(msg, "hsync enabled, ", sizeof(msg));
}
else
{
/* disable HD15 hsync */
temp |= 0x10;
sprintf(msg, "%shsync disabled, ", msg);
strlcat(msg, "hsync disabled, ", sizeof(msg));
}
if (v)
{
/* enable HD15 vsync */
temp &= ~0x20;
sprintf(msg, "%svsync enabled\n", msg);
strlcat(msg, "vsync enabled\n", sizeof(msg));
}
else
{
/* disable HD15 vsync */
temp |= 0x20;
sprintf(msg, "%svsync disabled\n", msg);
strlcat(msg, "vsync disabled\n", sizeof(msg));
}
}

1
src/add-ons/accelerants/matrox/engine/mga_std.h
View File

@ -1,4 +1,5 @@
#include <stdio.h>
#include <string.h>
#include <sys/ioctl.h>
#include <math.h>
#include <OS.h>

22
src/add-ons/accelerants/nvidia/engine/nv_crtc.c
View File

@ -603,7 +603,7 @@ status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel)
uint8 temp;
char msg[100];
sprintf(msg, "CRTC: setting DPMS: ");
strlcpy(msg, "CRTC: setting DPMS: ", sizeof(msg));
/* enable access to primary head */
set_crtc_owner(0);
@ -644,7 +644,7 @@ status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel)
/* (confirmed OK on NV28 and NV34) */
//CRTCW(0x59, (CRTCR(0x59) | 0x01));
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
else
{
@ -656,12 +656,12 @@ status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel)
/* note: this seems to be a write-only register. */
NV_REG32(NV32_LVDS_PWR) = 0x00000003;
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
}
}
sprintf(msg, "%sdisplay on, ", msg);
strlcat(msg, "display on, ", sizeof(msg));
}
else
{
@ -687,7 +687,7 @@ status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel)
/* (confirmed OK on NV28 and NV34) */
//CRTCW(0x59, (CRTCR(0x59) & 0xfe));
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
else
{
@ -699,33 +699,33 @@ status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel)
/* note: this seems to be a write-only register. */
NV_REG32(NV32_LVDS_PWR) = 0x00000007;
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
}
}
sprintf(msg, "%sdisplay off, ", msg);
strlcat(msg, "display off, ", sizeof(msg));
}
if (h)
{
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f));
sprintf(msg, "%shsync enabled, ", msg);
strlcat(msg, "hsync enabled, ", sizeof(msg));
}
else
{
CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80));
sprintf(msg, "%shsync disabled, ", msg);
strlcat(msg, "hsync disabled, ", sizeof(msg));
}
if (v)
{
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf));
sprintf(msg, "%svsync enabled\n", msg);
strlcat(msg, "vsync enabled\n", sizeof(msg));
}
else
{
CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40));
sprintf(msg, "%svsync disabled\n", msg);
strlcat(msg, "vsync disabled\n", sizeof(msg));
}
LOG(4, (msg));

22
src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
View File

@ -586,7 +586,7 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel)
uint8 temp;
char msg[100];
sprintf(msg, "CRTC2: setting DPMS: ");
strlcpy(msg, "CRTC2: setting DPMS: ", sizeof(msg));
/* enable access to secondary head */
set_crtc_owner(1);
@ -627,7 +627,7 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel)
/* (confirmed OK on NV28 and NV34) */
//CRTC2W(0x59, (CRTC2R(0x59) | 0x01));
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
else
{
@ -638,12 +638,12 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel)
/* note: this seems to be a write-only register. */
NV_REG32(NV32_LVDS_PWR) = 0x00000003;
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
}
}
sprintf(msg, "%sdisplay on, ", msg);
strlcat(msg, "display on, ", sizeof(msg));
}
else
{
@ -669,7 +669,7 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel)
/* (confirmed OK on NV28 and NV34) */
//CRTC2W(0x59, (CRTC2R(0x59) & 0xfe));
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
else
{
@ -680,33 +680,33 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel)
/* note: this seems to be a write-only register. */
NV_REG32(NV32_LVDS_PWR) = 0x00000007;
sprintf(msg, "%s(panel-)", msg);
strlcat(msg, "(panel-)", sizeof(msg));
}
}
}
sprintf(msg, "%sdisplay off, ", msg);
strlcat(msg, "display off, ", sizeof(msg));
}
if (h)
{
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f));
sprintf(msg, "%shsync enabled, ", msg);
strlcat(msg, "hsync enabled, ", sizeof(msg));
}
else
{
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80));
sprintf(msg, "%shsync disabled, ", msg);
strlcat(msg, "hsync disabled, ", sizeof(msg));
}
if (v)
{
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf));
sprintf(msg, "%svsync enabled\n", msg);
strlcat(msg, "vsync enabled\n", sizeof(msg));
}
else
{
CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40));
sprintf(msg, "%svsync disabled\n", msg);
strlcat(msg, "vsync disabled\n", sizeof(msg));
}
LOG(4, (msg));