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small simplification for reading and writing DMAGET and DMAPUT, gives a minor speedup (a few percent max). 

git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11167 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-01-31 10:53:21 +00:00
parent eb5bc5f924
commit 8d2dfc64ee
1 changed files with 19 additions and 17 deletions
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36
src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
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@ -47,9 +47,11 @@ status_t nv_acc_wait_idle_dma()
* we hit a timeout; abort if we failed at least three times before: * we hit a timeout; abort if we failed at least three times before:
* if DMA stalls, we have to forget about it alltogether at some point, or * if DMA stalls, we have to forget about it alltogether at some point, or
* the system will almost come to a complete halt.. */ * the system will almost come to a complete halt.. */
while ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET + /* note:
si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]) * it doesn't matter which FIFO channel's DMA registers we access, they are in
!= (si->engine.dma.put << 2)) && * fact all the same set. It also doesn't matter if the channel was assigned a
* command or not. */
while ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET) != (si->engine.dma.put << 2)) &&
(cnt < 10000) && (err < 3)) (cnt < 10000) && (err < 3))
{ {
/* snooze a bit so I do not hammer the bus */ /* snooze a bit so I do not hammer the bus */
@ -710,7 +712,9 @@ status_t nv_acc_init_dma()
/*** init FIFO via DMA command buffer. ***/ /*** init FIFO via DMA command buffer. ***/
/* wait for room in fifo for new FIFO assigment cmds if needed: */ /* wait for room in fifo for new FIFO assigment cmds if needed: */
if (nv_acc_fifofree_dma(16) != B_OK) return B_ERROR; //fixme if CH6 and CH7 are assigned..
// if (nv_acc_fifofree_dma(16) != B_OK) return B_ERROR;
if (nv_acc_fifofree_dma(12) != B_OK) return B_ERROR;
/* program new FIFO assignments */ /* program new FIFO assignments */
/* Raster OPeration: */ /* Raster OPeration: */
@ -726,13 +730,11 @@ status_t nv_acc_init_dma()
/* Bitmap: */ /* Bitmap: */
nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]); nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]);
/* Line: (not used or 3D only?) */ /* Line: (not used or 3D only?) */
//fixme: temporary so there's something valid here.. (maybe needed, don't yet know) //fixme..
// nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]); // nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]);
nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[0]);
/* Textured Triangle: (3D only) */ /* Textured Triangle: (3D only) */
//fixme: temporary so there's something valid here.. (maybe needed, don't yet know) //fixme..
// nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[7]); // nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[7]);
nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH7, si->engine.fifo.handle[0]);
/*** Set pixel width ***/ /*** Set pixel width ***/
switch(si->dm.space) switch(si->dm.space)
@ -795,20 +797,17 @@ static void nv_start_dma(void)
if (si->engine.dma.current != si->engine.dma.put) if (si->engine.dma.current != si->engine.dma.put)
{ {
si->engine.dma.put = si->engine.dma.current; si->engine.dma.put = si->engine.dma.current;
/* fixme: is this actually needed? (force some flush somewhere) */
// ISAWB(0x03d0, 0x00);
/* dummy read the first adress of the framebuffer: flushes MTRR-WC buffers so /* dummy read the first adress of the framebuffer: flushes MTRR-WC buffers so
* we know for sure the DMA command buffer received all data. */ * we know for sure the DMA command buffer received all data. */
dummy = *((char *)(si->framebuffer)); dummy = *((char *)(si->framebuffer));
/* actually start DMA to execute all commands now in buffer */ /* actually start DMA to execute all commands now in buffer */
/* note: /* note:
* the actual FIFO channel that gets activated does not really matter: * it doesn't matter which FIFO channel's DMA registers we access, they are in
* all FIFO fill-level info actually points at the same registers. */ * fact all the same set. It also doesn't matter if the channel was assigned a
* command or not. */
/* note also: /* note also:
* NV_GENERAL_DMAPUT is a write-only register on some cards (confirmed NV11). */ * NV_GENERAL_DMAPUT is a write-only register on some cards (confirmed NV11). */
NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT + NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT) = (si->engine.dma.put << 2);
si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]) =
(si->engine.dma.put << 2);
} }
} }
@ -831,8 +830,11 @@ static status_t nv_acc_fifofree_dma(uint16 cmd_size)
/* see where the engine is currently fetching from the buffer */ /* see where the engine is currently fetching from the buffer */
/* note: /* note:
* read this only once in the code as accessing registers is relatively slow */ * read this only once in the code as accessing registers is relatively slow */
dmaget = ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET + /* note also:
si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])])) >> 2); * it doesn't matter which FIFO channel's DMA registers we access, they are in
* fact all the same set. It also doesn't matter if the channel was assigned a
* command or not. */
dmaget = ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET)) >> 2);
/* update timeout counter: on NV11 on a Pentium4 2.8Ghz max reached count /* update timeout counter: on NV11 on a Pentium4 2.8Ghz max reached count
* using BeRoMeter 1.2.6 was about 600; so counting 10000 before generating * using BeRoMeter 1.2.6 was about 600; so counting 10000 before generating