added via accelerant, a copy of skeleton driver yet.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13599 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
5998579f4b
commit
8ac4b65fe4
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@ -0,0 +1,561 @@
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/* program the DAC */
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/* Author:
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Rudolf Cornelissen 12/2003-10/2004
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*/
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#define MODULE_BIT 0x00010000
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#include "std.h"
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static status_t nv4_nv10_nv20_dac_pix_pll_find(
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display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test);
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/* see if an analog VGA monitor is connected to connector #1 */
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bool eng_dac_crt_connected(void)
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{
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uint32 output, dac;
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bool present;
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/* save output connector setting */
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output = DACR(OUTPUT);
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/* save DAC state */
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dac = DACR(TSTCTRL);
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/* turn on DAC */
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DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff));
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/* select primary head and turn off CRT (and DVI?) outputs */
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DACW(OUTPUT, (output & 0x0000feee));
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/* wait for signal lines to stabilize */
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snooze(1000);
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/* re-enable CRT output */
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DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001));
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/* setup RGB test signal levels to approx 30% of DAC range and enable them */
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DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0)));
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/* route test signals to output */
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DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000));
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/* wait for signal lines to stabilize */
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snooze(1000);
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/* do actual detection: all signals paths high == CRT connected */
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if (DACR(TSTCTRL) & 0x10000000)
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{
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present = true;
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LOG(4,("DAC: CRT detected on connector #1\n"));
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}
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else
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{
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present = false;
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LOG(4,("DAC: no CRT detected on connector #1\n"));
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}
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/* kill test signal routing */
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DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff));
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/* restore output connector setting */
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DACW(OUTPUT, output);
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/* restore DAC state */
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DACW(TSTCTRL, dac);
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return present;
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}
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/*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/
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status_t eng_dac_mode(int mode,float brightness)
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{
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uint8 *r,*g,*b;
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int i, ri;
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/*set colour arrays to point to space reserved in shared info*/
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r = si->color_data;
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g = r + 256;
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b = g + 256;
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LOG(4,("DAC: Setting screen mode %d brightness %f\n", mode, brightness));
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/* init the palette for brightness specified */
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/* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */
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for (i = 0; i < 256; i++)
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{
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ri = i * brightness;
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if (ri > 255) ri = 255;
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b[i] = g[i] = r[i] = ri;
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}
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if (eng_dac_palette(r,g,b) != B_OK) return B_ERROR;
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/* disable palette RAM adressing mask */
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ENG_REG8(RG8_PALMASK) = 0xff;
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LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", ENG_REG8(RG8_PALMASK)));
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return B_OK;
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}
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/*program the DAC palette using the given r,g,b values*/
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status_t eng_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256])
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{
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int i;
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LOG(4,("DAC: setting palette\n"));
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/* select first PAL adress before starting programming */
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ENG_REG8(RG8_PALINDW) = 0x00;
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/* loop through all 256 to program DAC */
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for (i = 0; i < 256; i++)
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{
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/* the 6 implemented bits are on b0-b5 of the bus */
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ENG_REG8(RG8_PALDATA) = r[i];
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ENG_REG8(RG8_PALDATA) = g[i];
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ENG_REG8(RG8_PALDATA) = b[i];
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}
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if (ENG_REG8(RG8_PALINDW) != 0x00)
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{
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LOG(8,("DAC: PAL write index incorrect after programming\n"));
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return B_ERROR;
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}
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if (1)
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{//reread LUT
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uint8 R, G, B;
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/* select first PAL adress to read (modulo 3 counter) */
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ENG_REG8(RG8_PALINDR) = 0x00;
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for (i = 0; i < 256; i++)
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{
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R = ENG_REG8(RG8_PALDATA);
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G = ENG_REG8(RG8_PALDATA);
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B = ENG_REG8(RG8_PALDATA);
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if ((r[i] != R) || (g[i] != G) || (b[i] != B))
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LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed
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}
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}
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return B_OK;
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}
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/*program the pixpll - frequency in kHz*/
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status_t eng_dac_set_pix_pll(display_mode target)
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{
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uint8 m=0,n=0,p=0;
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// uint time = 0;
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float pix_setting, req_pclk;
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status_t result;
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/* we offer this option because some panels have very tight restrictions,
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* and there's no overlapping settings range that makes them all work.
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* note:
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* this assumes the cards BIOS correctly programmed the panel (is likely) */
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//fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
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if (si->ps.tmds1_active && !si->settings.pgm_panel)
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{
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LOG(4,("DAC: Not programming DFP refresh (specified in skel.settings)\n"));
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return B_OK;
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}
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/* fix a DVI or laptop flatpanel to 60Hz refresh! */
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/* Note:
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* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
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if (si->ps.tmds1_active)
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{
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LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n"));
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/* use the panel's modeline to determine the needed pixelclock */
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target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;
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}
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req_pclk = (target.timing.pixel_clock)/1000.0;
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LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));
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/* signal that we actually want to set the mode */
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result = eng_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
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if (result != B_OK)
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{
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return result;
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}
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/*reprogram (disable,select,wait for stability,enable)*/
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// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/
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// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/
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/* program new frequency */
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DACW(PIXPLLC, ((p << 16) | (n << 8) | m));
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/* program 2nd set N and M scalers if they exist (b31=1 enables them) */
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if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);
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/* Wait for the PIXPLL frequency to lock until timeout occurs */
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//fixme: do NV cards have a LOCK indication bit??
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/* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000))
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{
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time++;
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snooze(1);
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}
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if (time > 2000)
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LOG(2,("DAC: PIX PLL frequency not locked!\n"));
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else
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LOG(2,("DAC: PIX PLL frequency locked\n"));
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DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL
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*/
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//for now:
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/* Give the PIXPLL frequency some time to lock... */
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snooze(1000);
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LOG(2,("DAC: PIX PLL frequency should be locked now...\n"));
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return B_OK;
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}
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/* find nearest valid pix pll */
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status_t eng_dac_pix_pll_find
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(display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
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{
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switch (si->ps.card_type) {
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default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test);
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}
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return B_ERROR;
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}
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/* find nearest valid pixel PLL setting */
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static status_t nv4_nv10_nv20_dac_pix_pll_find(
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display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
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{
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int m = 0, n = 0, p = 0/*, m_max*/;
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float error, error_best = 999999999;
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int best[3];
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float f_vco, max_pclk;
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float req_pclk = target.timing.pixel_clock/1000.0;
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/* determine the max. reference-frequency postscaler setting for the
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* current card (see G100, G200 and G400 specs). */
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/* switch(si->ps.card_type)
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{
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case G100:
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LOG(4,("DAC: G100 restrictions apply\n"));
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m_max = 7;
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break;
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case G200:
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LOG(4,("DAC: G200 restrictions apply\n"));
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m_max = 7;
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break;
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default:
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LOG(4,("DAC: G400/G400MAX restrictions apply\n"));
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m_max = 32;
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break;
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}
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*/
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LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n"));
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/* determine the max. pixelclock for the current videomode */
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switch (target.space)
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{
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case B_CMAP8:
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max_pclk = si->ps.max_dac1_clock_8;
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break;
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case B_RGB15_LITTLE:
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case B_RGB16_LITTLE:
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max_pclk = si->ps.max_dac1_clock_16;
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break;
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case B_RGB24_LITTLE:
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max_pclk = si->ps.max_dac1_clock_24;
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break;
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case B_RGB32_LITTLE:
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max_pclk = si->ps.max_dac1_clock_32;
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break;
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default:
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/* use fail-safe value */
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max_pclk = si->ps.max_dac1_clock_32;
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break;
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}
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/* if some dualhead mode is active, an extra restriction might apply */
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if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE))
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max_pclk = si->ps.max_dac1_clock_32dh;
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/* Make sure the requested pixelclock is within the PLL's operational limits */
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/* lower limit is min_pixel_vco divided by highest postscaler-factor */
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if (req_pclk < (si->ps.min_pixel_vco / 16.0))
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{
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LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n",
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req_pclk, (float)(si->ps.min_pixel_vco / 16.0)));
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req_pclk = (si->ps.min_pixel_vco / 16.0);
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}
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/* upper limit is given by pins in combination with current active mode */
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if (req_pclk > max_pclk)
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{
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LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n",
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req_pclk, (float)max_pclk));
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req_pclk = max_pclk;
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}
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/* iterate through all valid PLL postscaler settings */
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for (p=0x01; p < 0x20; p = p<<1)
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{
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/* calculate the needed VCO frequency for this postscaler setting */
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f_vco = req_pclk * p;
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/* check if this is within range of the VCO specs */
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if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))
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{
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/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
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if (si->ps.ext_pll) f_vco /= 4;
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/* iterate trough all valid reference-frequency postscaler settings */
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for (m = 7; m <= 14; m++)
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{
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/* check if phase-discriminator will be within operational limits */
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//fixme: PLL calcs will be resetup/splitup/updated...
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if (si->ps.card_type == NV36)
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{
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if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;
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}
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else
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{
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if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;
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}
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/* calculate VCO postscaler setting for current setup.. */
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n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
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/* ..and check for validity */
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if ((n < 1) || (n > 255)) continue;
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/* find error in frequency this setting gives */
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if (si->ps.ext_pll)
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{
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/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
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error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));
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}
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else
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error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));
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/* note the setting if best yet */
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if (error < error_best)
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{
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error_best = error;
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best[0]=m;
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best[1]=n;
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best[2]=p;
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}
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}
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}
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}
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/* setup the scalers programming values for found optimum setting */
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m = best[0];
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n = best[1];
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p = best[2];
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/* log the VCO frequency found */
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f_vco = ((si->ps.f_ref / m) * n);
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/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
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if (si->ps.ext_pll) f_vco *= 4;
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LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco));
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/* return the results */
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*calc_pclk = (f_vco / p);
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*m_result = m;
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*n_result = n;
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switch(p)
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{
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case 1:
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p = 0x00;
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break;
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case 2:
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p = 0x01;
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break;
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case 4:
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p = 0x02;
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break;
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case 8:
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p = 0x03;
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break;
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case 16:
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p = 0x04;
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break;
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}
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*p_result = p;
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/* display the found pixelclock values */
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LOG(2,("DAC: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n",
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req_pclk, *calc_pclk, *m_result, *n_result, *p_result));
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return B_OK;
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}
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/* find nearest valid system PLL setting */
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status_t eng_dac_sys_pll_find(
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float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, uint8* p_result, uint8 test)
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{
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int m = 0, n = 0, p = 0, m_max, p_max;
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float error, error_best = 999999999;
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int best[3];
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float f_vco, discr_low, discr_high;
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/* determine the max. reference-frequency postscaler setting for the
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* current requested clock */
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switch (si->ps.card_arch)
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{
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case NV04A:
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LOG(4,("DAC: NV04 restrictions apply\n"));
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/* set phase-discriminator frequency range (Mhz) (verified) */
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discr_low = 1.0;
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discr_high = 2.0;
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/* set max. useable reference frequency postscaler divider factor */
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m_max = 14;
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/* set max. useable VCO output postscaler divider factor */
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p_max = 16;
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break;
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default:
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switch (si->ps.card_type)
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{
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case NV28:
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//fixme: how about some other cards???
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LOG(4,("DAC: NV28 restrictions apply\n"));
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/* set max. useable reference frequency postscaler divider factor;
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* apparantly we would get distortions on high PLL output frequencies if
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* we use the phase-discriminator at low frequencies */
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if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */
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else if (req_sclk > 200.0) m_max = 4; /* 200Mhz < Fpll <= 340Mhz */
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else if (req_sclk > 150.0) m_max = 6; /* 150Mhz < Fpll <= 200Mhz */
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else m_max = 14; /* Fpll < 150Mhz */
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/* set max. useable VCO output postscaler divider factor */
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p_max = 32;
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/* set phase-discriminator frequency range (Mhz) (verified) */
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discr_low = 1.0;
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discr_high = 27.0;
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break;
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default:
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LOG(4,("DAC: NV10/NV20/NV30 restrictions apply\n"));
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/* set max. useable reference frequency postscaler divider factor;
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* apparantly we would get distortions on high PLL output frequencies if
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* we use the phase-discriminator at low frequencies */
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if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */
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else if (req_sclk > 250.0) m_max = 6; /* 250Mhz < Fpll <= 340Mhz */
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else m_max = 14; /* Fpll < 250Mhz */
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/* set max. useable VCO output postscaler divider factor */
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p_max = 16;
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/* set phase-discriminator frequency range (Mhz) (verified) */
|
||||
if (si->ps.card_type == NV36) discr_low = 3.2;
|
||||
else discr_low = 1.0;
|
||||
/* (high discriminator spec is failsafe) */
|
||||
discr_high = 14.0;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
LOG(4,("DAC: PLL reference frequency postscaler divider range is 1 - %d\n", m_max));
|
||||
LOG(4,("DAC: PLL VCO output postscaler divider range is 1 - %d\n", p_max));
|
||||
LOG(4,("DAC: PLL discriminator input frequency range is %2.2fMhz - %2.2fMhz\n",
|
||||
discr_low, discr_high));
|
||||
|
||||
/* Make sure the requested clock is within the PLL's operational limits */
|
||||
/* lower limit is min_system_vco divided by highest postscaler-factor */
|
||||
if (req_sclk < (si->ps.min_system_vco / ((float)p_max)))
|
||||
{
|
||||
LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n",
|
||||
req_sclk, (si->ps.min_system_vco / ((float)p_max))));
|
||||
req_sclk = (si->ps.min_system_vco / ((float)p_max));
|
||||
}
|
||||
/* upper limit is given by pins */
|
||||
if (req_sclk > si->ps.max_system_vco)
|
||||
{
|
||||
LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n",
|
||||
req_sclk, (float)si->ps.max_system_vco));
|
||||
req_sclk = si->ps.max_system_vco;
|
||||
}
|
||||
|
||||
/* iterate through all valid PLL postscaler settings */
|
||||
for (p=0x01; p <= p_max; p = p<<1)
|
||||
{
|
||||
/* calculate the needed VCO frequency for this postscaler setting */
|
||||
f_vco = req_sclk * p;
|
||||
|
||||
/* check if this is within range of the VCO specs */
|
||||
if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco))
|
||||
{
|
||||
/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
|
||||
if (si->ps.ext_pll) f_vco /= 4;
|
||||
|
||||
/* iterate trough all valid reference-frequency postscaler settings */
|
||||
for (m = 1; m <= m_max; m++)
|
||||
{
|
||||
/* check if phase-discriminator will be within operational limits */
|
||||
if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high))
|
||||
continue;
|
||||
|
||||
/* calculate VCO postscaler setting for current setup.. */
|
||||
n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
|
||||
|
||||
/* ..and check for validity */
|
||||
if ((n < 1) || (n > 255)) continue;
|
||||
|
||||
/* find error in frequency this setting gives */
|
||||
if (si->ps.ext_pll)
|
||||
{
|
||||
/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
|
||||
error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p));
|
||||
}
|
||||
else
|
||||
error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p));
|
||||
|
||||
/* note the setting if best yet */
|
||||
if (error < error_best)
|
||||
{
|
||||
error_best = error;
|
||||
best[0]=m;
|
||||
best[1]=n;
|
||||
best[2]=p;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* setup the scalers programming values for found optimum setting */
|
||||
m = best[0];
|
||||
n = best[1];
|
||||
p = best[2];
|
||||
|
||||
/* log the VCO frequency found */
|
||||
f_vco = ((si->ps.f_ref / m) * n);
|
||||
/* FX5600 and FX5700 tweak for 2nd set N and M scalers */
|
||||
if (si->ps.ext_pll) f_vco *= 4;
|
||||
|
||||
LOG(2,("DAC: sys VCO frequency found %fMhz\n", f_vco));
|
||||
|
||||
/* return the results */
|
||||
*calc_sclk = (f_vco / p);
|
||||
*m_result = m;
|
||||
*n_result = n;
|
||||
switch(p)
|
||||
{
|
||||
case 1:
|
||||
p = 0x00;
|
||||
break;
|
||||
case 2:
|
||||
p = 0x01;
|
||||
break;
|
||||
case 4:
|
||||
p = 0x02;
|
||||
break;
|
||||
case 8:
|
||||
p = 0x03;
|
||||
break;
|
||||
case 16:
|
||||
p = 0x04;
|
||||
break;
|
||||
case 32:
|
||||
p = 0x05;
|
||||
break;
|
||||
}
|
||||
*p_result = p;
|
||||
|
||||
/* display the found pixelclock values */
|
||||
LOG(2,("DAC: sys PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n",
|
||||
req_sclk, *calc_sclk, *m_result, *n_result, *p_result));
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
Loading…
Reference in New Issue