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Printf format adjustments to get ahci building on x86_64.

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This commit is contained in:
Rene Gollent 2012-08-02 20:29:12 -04:00
parent 81033e260a
commit 886f1456af
3 changed files with 51 additions and 46 deletions
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20
src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
View File

@ -80,7 +80,8 @@ AHCIController::Init()
TRACE("PCI SATA capability found at offset 0x%x\n", capabilityOffset); TRACE("PCI SATA capability found at offset 0x%x\n", capabilityOffset);
satacr0 = fPCI->read_pci_config(fPCIDevice, capabilityOffset, 4); satacr0 = fPCI->read_pci_config(fPCIDevice, capabilityOffset, 4);
satacr1 = fPCI->read_pci_config(fPCIDevice, capabilityOffset + 4, 4); satacr1 = fPCI->read_pci_config(fPCIDevice, capabilityOffset + 4, 4);
TRACE("satacr0 = 0x%08lx, satacr1 = 0x%08lx\n", satacr0, satacr1); TRACE("satacr0 = 0x%08" B_PRIx32 ", satacr1 = 0x%08" B_PRIx32 "\n",
satacr0, satacr1);
} }
uint16 pcicmd = fPCI->read_pci_config(fPCIDevice, PCI_command, 2); uint16 pcicmd = fPCI->read_pci_config(fPCIDevice, PCI_command, 2);
@ -92,10 +93,10 @@ AHCIController::Init()
if (fPCIVendorID == PCI_VENDOR_JMICRON) { if (fPCIVendorID == PCI_VENDOR_JMICRON) {
uint32 ctrl = fPCI->read_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4); uint32 ctrl = fPCI->read_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4);
TRACE("Jmicron controller control 1 old 0x%08lx\n", ctrl); TRACE("Jmicron controller control 1 old 0x%08" B_PRIx32 "\n", ctrl);
ctrl &= ~((1 << 9) | (1 << 12) | (1 << 14)); // disable SFF 8038i emulation ctrl &= ~((1 << 9) | (1 << 12) | (1 << 14)); // disable SFF 8038i emulation
ctrl |= (1 << 8) | (1 << 13) | (1 << 15); // enable AHCI controller ctrl |= (1 << 8) | (1 << 13) | (1 << 15); // enable AHCI controller
TRACE("Jmicron controller control 1 new 0x%08lx\n", ctrl); TRACE("Jmicron controller control 1 new 0x%08" B_PRIx32 "\n", ctrl);
fPCI->write_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4, ctrl); fPCI->write_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4, ctrl);
} }
@ -132,14 +133,15 @@ AHCIController::Init()
fPortImplementedMask = fRegs->pi; fPortImplementedMask = fRegs->pi;
if (fPortImplementedMask == 0) { if (fPortImplementedMask == 0) {
fPortImplementedMask = 0xffffffff >> (32 - fPortCountMax); fPortImplementedMask = 0xffffffff >> (32 - fPortCountMax);
TRACE("ports-implemented mask is zero, using 0x%lx instead.\n", fPortImplementedMask); TRACE("ports-implemented mask is zero, using 0x%" B_PRIx32 " instead.\n",
fPortImplementedMask);
} }
fPortCountAvail = count_bits_set(fPortImplementedMask); fPortCountAvail = count_bits_set(fPortImplementedMask);
TRACE("cap: Interface Speed Support: generation %lu\n", (fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK); TRACE("cap: Interface Speed Support: generation %" B_PRIu32 "\n", (fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK);
TRACE("cap: Number of Command Slots: %d (raw %#lx)\n", fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK); TRACE("cap: Number of Command Slots: %d (raw %#" B_PRIx32 ")\n", fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK);
TRACE("cap: Number of Ports: %d (raw %#lx)\n", fPortCountMax, (fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK); TRACE("cap: Number of Ports: %d (raw %#" B_PRIx32 ")\n", fPortCountMax, (fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK);
TRACE("cap: Supports Port Multiplier: %s\n", (fRegs->cap & CAP_SPM) ? "yes" : "no"); TRACE("cap: Supports Port Multiplier: %s\n", (fRegs->cap & CAP_SPM) ? "yes" : "no");
TRACE("cap: Supports External SATA: %s\n", (fRegs->cap & CAP_SXS) ? "yes" : "no"); TRACE("cap: Supports External SATA: %s\n", (fRegs->cap & CAP_SXS) ? "yes" : "no");
TRACE("cap: Enclosure Management Supported: %s\n", (fRegs->cap & CAP_EMS) ? "yes" : "no"); TRACE("cap: Enclosure Management Supported: %s\n", (fRegs->cap & CAP_EMS) ? "yes" : "no");
@ -156,9 +158,9 @@ AHCIController::Init()
TRACE("cap: Supports AHCI mode only: %s\n", (fRegs->cap & CAP_SAM) ? "yes" : "no"); TRACE("cap: Supports AHCI mode only: %s\n", (fRegs->cap & CAP_SAM) ? "yes" : "no");
TRACE("ghc: AHCI Enable: %s\n", (fRegs->ghc & GHC_AE) ? "yes" : "no"); TRACE("ghc: AHCI Enable: %s\n", (fRegs->ghc & GHC_AE) ? "yes" : "no");
TRACE("Ports Implemented Mask: %#08lx\n", fPortImplementedMask); TRACE("Ports Implemented Mask: %#08" B_PRIx32 "\n", fPortImplementedMask);
TRACE("Number of Available Ports: %d\n", fPortCountAvail); TRACE("Number of Available Ports: %d\n", fPortCountAvail);
TRACE("AHCI Version %lu.%lu\n", fRegs->vs >> 16, fRegs->vs & 0xff); TRACE("AHCI Version %" B_PRIu32 ".%" B_PRIu32 "\n", fRegs->vs >> 16, fRegs->vs & 0xff);
TRACE("Interrupt %u\n", fIRQ); TRACE("Interrupt %u\n", fIRQ);
// setup interrupt handler // setup interrupt handler

65
src/add-ons/kernel/busses/scsi/ahci/ahci_port.cpp
View File

@ -148,14 +148,14 @@ AHCIPort::Init2()
ResetPort(true); ResetPort(true);
TRACE("ie 0x%08lx\n", fRegs->ie); TRACE("ie 0x%08" B_PRIx32 "\n", fRegs->ie);
TRACE("is 0x%08lx\n", fRegs->is); TRACE("is 0x%08" B_PRIx32 "\n", fRegs->is);
TRACE("cmd 0x%08lx\n", fRegs->cmd); TRACE("cmd 0x%08" B_PRIx32 "\n", fRegs->cmd);
TRACE("ssts 0x%08lx\n", fRegs->ssts); TRACE("ssts 0x%08" B_PRIx32 "\n", fRegs->ssts);
TRACE("sctl 0x%08lx\n", fRegs->sctl); TRACE("sctl 0x%08" B_PRIx32 "\n", fRegs->sctl);
TRACE("serr 0x%08lx\n", fRegs->serr); TRACE("serr 0x%08" B_PRIx32 "\n", fRegs->serr);
TRACE("sact 0x%08lx\n", fRegs->sact); TRACE("sact 0x%08" B_PRIx32 "\n", fRegs->sact);
TRACE("tfd 0x%08lx\n", fRegs->tfd); TRACE("tfd 0x%08" B_PRIx32 "\n", fRegs->tfd);
fDevicePresent = (fRegs->ssts & 0xf) == 0x3; fDevicePresent = (fRegs->ssts & 0xf) == 0x3;
@ -300,7 +300,7 @@ AHCIPort::PostReset()
FlushPostedWrites(); FlushPostedWrites();
if (!fTestUnitReadyActive) { if (!fTestUnitReadyActive) {
TRACE("device signature 0x%08lx (%s)\n", fRegs->sig, TRACE("device signature 0x%08" B_PRIx32 " (%s)\n", fRegs->sig,
(fRegs->sig == 0xeb140101) ? "ATAPI" : (fRegs->sig == 0x00000101) ? (fRegs->sig == 0xeb140101) ? "ATAPI" : (fRegs->sig == 0x00000101) ?
"ATA" : "unknown"); "ATA" : "unknown");
} }
@ -339,8 +339,8 @@ AHCIPort::Interrupt()
uint32 ci = fRegs->ci; uint32 ci = fRegs->ci;
RWTRACE("[%lld] %ld AHCIPort::Interrupt port %d, fCommandsActive 0x%08lx, " RWTRACE("[%lld] %ld AHCIPort::Interrupt port %d, fCommandsActive 0x%08" B_PRIx32 ", "
"is 0x%08lx, ci 0x%08lx\n", system_time(), find_thread(NULL), "is 0x%08" B_PRIx32 ", ci 0x%08" B_PRIx32 "\n", system_time(), find_thread(NULL),
fIndex, fCommandsActive, is, ci); fIndex, fCommandsActive, is, ci);
acquire_spinlock(&fSpinlock); acquire_spinlock(&fSpinlock);
@ -359,13 +359,13 @@ AHCIPort::InterruptErrorHandler(uint32 is)
if (!fTestUnitReadyActive) { if (!fTestUnitReadyActive) {
TRACE("AHCIPort::InterruptErrorHandler port %d, " TRACE("AHCIPort::InterruptErrorHandler port %d, "
"fCommandsActive 0x%08lx, is 0x%08lx, ci 0x%08lx\n", fIndex, "fCommandsActive 0x%08" B_PRIx32 ", is 0x%08" B_PRIx32 ", ci 0x%08" B_PRIx32 "\n", fIndex,
fCommandsActive, is, ci); fCommandsActive, is, ci);
TRACE("ssts 0x%08lx\n", fRegs->ssts); TRACE("ssts 0x%08" B_PRIx32 "\n", fRegs->ssts);
TRACE("sctl 0x%08lx\n", fRegs->sctl); TRACE("sctl 0x%08" B_PRIx32 "\n", fRegs->sctl);
TRACE("serr 0x%08lx\n", fRegs->serr); TRACE("serr 0x%08" B_PRIx32 "\n", fRegs->serr);
TRACE("sact 0x%08lx\n", fRegs->sact); TRACE("sact 0x%08" B_PRIx32 "\n", fRegs->sact);
} }
// read and clear SError // read and clear SError
@ -615,8 +615,8 @@ AHCIPort::ScsiInquiry(scsi_ccb *request)
fSectorSize = 512; fSectorSize = 512;
fSectorCount = !(lba || sectors) ? 0 : lba48 ? sectors48 : sectors; fSectorCount = !(lba || sectors) ? 0 : lba48 ? sectors48 : sectors;
fTrim = ataData.data_set_management_support; fTrim = ataData.data_set_management_support;
TRACE("lba %d, lba48 %d, fUse48BitCommands %d, sectors %lu, " TRACE("lba %d, lba48 %d, fUse48BitCommands %d, sectors %" B_PRIu32
"sectors48 %llu, size %llu\n", ", sectors48 %" B_PRIu64 ", size %" B_PRIu64 "\n",
lba, lba48, fUse48BitCommands, sectors, sectors48, lba, lba48, fUse48BitCommands, sectors, sectors48,
fSectorCount * fSectorSize); fSectorCount * fSectorSize);
} }
@ -687,7 +687,8 @@ AHCIPort::ScsiReadCapacity(scsi_ccb *request)
return; return;
} }
TRACE("SectorSize %lu, SectorCount 0x%llx\n", fSectorSize, fSectorCount); TRACE("SectorSize %" B_PRIu32 ", SectorCount 0x%" B_PRIx64 "\n",
fSectorSize, fSectorCount);
if (fSectorCount > 0xffffffff) if (fSectorCount > 0xffffffff)
panic("ahci: SCSI emulation doesn't support harddisks larger than 2TB"); panic("ahci: SCSI emulation doesn't support harddisks larger than 2TB");
@ -814,20 +815,20 @@ AHCIPort::ExecuteSataRequest(sata_request *request, bool isWrite)
FLOW("tfd %#x\n", tfd); FLOW("tfd %#x\n", tfd);
FLOW("prdbc %ld\n", fCommandList->prdbc); FLOW("prdbc %ld\n", fCommandList->prdbc);
FLOW("ci 0x%08lx\n", fRegs->ci); FLOW("ci 0x%08" B_PRIx32 "\n", fRegs->ci);
FLOW("is 0x%08lx\n", fRegs->is); FLOW("is 0x%08" B_PRIx32 "\n", fRegs->is);
FLOW("serr 0x%08lx\n", fRegs->serr); FLOW("serr 0x%08" B_PRIx32 "\n", fRegs->serr);
/* /*
TRACE("ci 0x%08lx\n", fRegs->ci); TRACE("ci 0x%08" B_PRIx32 "\n", fRegs->ci);
TRACE("ie 0x%08lx\n", fRegs->ie); TRACE("ie 0x%08" B_PRIx32 "\n", fRegs->ie);
TRACE("is 0x%08lx\n", fRegs->is); TRACE("is 0x%08" B_PRIx32 "\n", fRegs->is);
TRACE("cmd 0x%08lx\n", fRegs->cmd); TRACE("cmd 0x%08" B_PRIx32 "\n", fRegs->cmd);
TRACE("ssts 0x%08lx\n", fRegs->ssts); TRACE("ssts 0x%08" B_PRIx32 "\n", fRegs->ssts);
TRACE("sctl 0x%08lx\n", fRegs->sctl); TRACE("sctl 0x%08" B_PRIx32 "\n", fRegs->sctl);
TRACE("serr 0x%08lx\n", fRegs->serr); TRACE("serr 0x%08" B_PRIx32 "\n", fRegs->serr);
TRACE("sact 0x%08lx\n", fRegs->sact); TRACE("sact 0x%08" B_PRIx32 "\n", fRegs->sact);
TRACE("tfd 0x%08lx\n", fRegs->tfd); TRACE("tfd 0x%08" B_PRIx32 "\n", fRegs->tfd);
*/ */
if (fResetPort || status == B_TIMED_OUT) { if (fResetPort || status == B_TIMED_OUT) {
@ -1025,5 +1026,5 @@ AHCIPort::ScsiGetRestrictions(bool *isATAPI, bool *noAutoSense,
*noAutoSense = fIsATAPI; // emulated auto sense for ATA, but not ATAPI *noAutoSense = fIsATAPI; // emulated auto sense for ATA, but not ATAPI
*maxBlocks = fUse48BitCommands ? 65536 : 256; *maxBlocks = fUse48BitCommands ? 65536 : 256;
TRACE("AHCIPort::ScsiGetRestrictions port %d: isATAPI %d, noAutoSense %d, " TRACE("AHCIPort::ScsiGetRestrictions port %d: isATAPI %d, noAutoSense %d, "
"maxBlocks %lu\n", fIndex, *isATAPI, *noAutoSense, *maxBlocks); "maxBlocks %" B_PRIu32 "\n", fIndex, *isATAPI, *noAutoSense, *maxBlocks);
} }

12
src/add-ons/kernel/busses/scsi/ahci/util.cpp
View File

@ -49,7 +49,7 @@ alloc_mem(void **virt, phys_addr_t *phy, size_t size, uint32 protection,
*virt = virtadr; *virt = virtadr;
if (phy) if (phy)
*phy = pe.address; *phy = pe.address;
TRACE("area = %ld, size = %ld, virt = %p, phy = %#" B_PRIxPHYSADDR "\n", TRACE("area = %" B_PRId32 ", size = %ld, virt = %p, phy = %#" B_PRIxPHYSADDR "\n",
areaid, size, virtadr, pe.address); areaid, size, virtadr, pe.address);
return areaid; return areaid;
} }
@ -73,15 +73,17 @@ map_mem(void **virt, phys_addr_t phy, size_t size, uint32 protection,
area = map_physical_memory(name, phyadr, size, area = map_physical_memory(name, phyadr, size,
B_ANY_KERNEL_BLOCK_ADDRESS, protection, &mapadr); B_ANY_KERNEL_BLOCK_ADDRESS, protection, &mapadr);
if (area < B_OK) { if (area < B_OK) {
ERROR("mapping '%s' failed, error 0x%lx (%s)\n", name, area, strerror(area)); ERROR("mapping '%s' failed, error 0x%" B_PRIx32 " (%s)\n", name,
area, strerror(area));
return area; return area;
} }
*virt = (char *)mapadr + offset; *virt = (char *)mapadr + offset;
TRACE("physical = %#" B_PRIxPHYSADDR ", virtual = %p, offset = %ld, " TRACE("physical = %#" B_PRIxPHYSADDR ", virtual = %p, offset = %"
"phyadr = %#" B_PRIxPHYSADDR ", mapadr = %p, size = %ld, area = " B_PRId32 ", phyadr = %#" B_PRIxPHYSADDR ", mapadr = %p, size = %"
"0x%08lx\n", phy, *virt, offset, phyadr, mapadr, size, area); B_PRIuSIZE ", area = 0x%08" B_PRIx32 "\n", phy, *virt, offset, phyadr,
mapadr, size, area);
return area; return area;
} }