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driver now at least compiles 

git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9786 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-11-04 14:39:05 +00:00
parent 7b078b3e1c
commit 886dbf812e
24 changed files with 278 additions and 890 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/add-ons/accelerants/skeleton/Acceleration.c
View File

@ -14,13 +14,13 @@ void SCREEN_TO_SCREEN_BLIT(engine_token *et, blit_params *list, uint32 count) {
int i;
/* init acc engine for blit function */
nv_acc_setup_blit();
eng_acc_setup_blit();
/* do each blit */
i=0;
while (count--)
{
nv_acc_blit
eng_acc_blit
(
list[i].src_left,
list[i].src_top,
@ -40,7 +40,7 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT(engine_token *et, scaled_blit_params
i=0;
while (count--)
{
nv_acc_video_blit
eng_acc_video_blit
(
list[i].src_left,
list[i].src_top,
@ -62,7 +62,7 @@ void SCREEN_TO_SCREEN_TRANSPARENT_BLIT(engine_token *et, uint32 transparent_colo
i=0;
while (count--)
{
nv_acc_transparent_blit
eng_acc_transparent_blit
(
list[i].src_left,
list[i].src_top,
@ -80,13 +80,13 @@ void FILL_RECTANGLE(engine_token *et, uint32 colorIndex, fill_rect_params *list,
int i;
/* init acc engine for fill function */
nv_acc_setup_rectangle(colorIndex);
eng_acc_setup_rectangle(colorIndex);
/* draw each rectangle */
i=0;
while (count--)
{
nv_acc_rectangle
eng_acc_rectangle
(
list[i].left,
(list[i].right)+1,
@ -101,13 +101,13 @@ void INVERT_RECTANGLE(engine_token *et, fill_rect_params *list, uint32 count) {
int i;
/* init acc engine for invert function */
nv_acc_setup_rect_invert();
eng_acc_setup_rect_invert();
/* invert each rectangle */
i=0;
while (count--)
{
nv_acc_rectangle_invert
eng_acc_rectangle_invert
(
list[i].left,
(list[i].right)+1,
@ -122,13 +122,13 @@ void FILL_SPAN(engine_token *et, uint32 colorIndex, uint16 *list, uint32 count)
int i;
/* init acc engine for fill function */
nv_acc_setup_rectangle(colorIndex);
eng_acc_setup_rectangle(colorIndex);
/* draw each span */
i=0;
while (count--)
{
nv_acc_rectangle
eng_acc_rectangle
(
list[i+1],
list[i+2]+1,

2
src/add-ons/accelerants/skeleton/Cursor.c
View File

@ -96,7 +96,7 @@ void MOVE_CURSOR(uint16 x, uint16 y)
if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start))
{
MOVE_DISPLAY(hds,vds);
nv_bes_move_overlay();
eng_bes_move_overlay();
}
/* put cursor in correct physical position, so stay onscreen (rel. to CRTC) */

2
src/add-ons/accelerants/skeleton/EngineManagement.c
View File

@ -45,7 +45,7 @@ status_t RELEASE_ENGINE(engine_token *et, sync_token *st)
void WAIT_ENGINE_IDLE(void)
{
/*wait for the engine to be totally idle*/
nv_acc_wait_idle();
eng_acc_wait_idle();
}
status_t GET_SYNC_TOKEN(engine_token *et, sync_token *st)

4
src/add-ons/accelerants/skeleton/InitAccelerant.c
View File

@ -116,7 +116,7 @@ status_t INIT_ACCELERANT(int the_fd) {
// LOG now available: !NULL si
/* call the device specific init code */
result = nv_general_powerup();
result = eng_general_powerup();
/* bail out if it failed */
if (result != B_OK) goto error1;
@ -173,7 +173,7 @@ status_t INIT_ACCELERANT(int the_fd) {
/* make sure overlay unit is 'marked' as being free */
si->overlay.myToken = NULL;
/* note that overlay is not in use (for nv_bes_move_overlay()) */
/* note that overlay is not in use (for eng_bes_move_overlay()) */
si->overlay.active = false;
/* bail out if something failed */

4
src/add-ons/accelerants/skeleton/Jamfile
View File

@ -8,7 +8,7 @@ UseHeaders [ FDirName $(SUBDIR) engine ] ;
Addon skel.accelerant : accelerants :
Acceleration.c
Cursor.c
EngineManagment.c
EngineManagement.c
GetAccelerantHook.c
GetDeviceInfo.c
GetModeInfo.c
@ -17,7 +17,7 @@ Addon skel.accelerant : accelerants :
Overlay.c
ProposeDisplayMode.c
SetDisplayMode.c
: false : libnvidia_engine.a
: false : libskeleton_engine.a
;
Package haiku-skeleton-cvs :

2
src/add-ons/accelerants/skeleton/ProposeDisplayMode.c
View File

@ -290,7 +290,7 @@ status_t PROPOSE_DISPLAY_MODE(display_mode *target, const display_mode *low, con
target->virtual_height = target->timing.v_display;
/* nail virtual size and 'subsequently' calculate rowbytes */
result = nv_general_validate_pic_size (target, &row_bytes, &acc_mode);
result = eng_general_validate_pic_size (target, &row_bytes, &acc_mode);
if (result == B_ERROR)
{
LOG(4, ("PROPOSEMODE: could not validate virtual picture size, aborted.\n"));

20
src/add-ons/accelerants/skeleton/SetDisplayMode.c
View File

@ -89,7 +89,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
/* calculate and set new mode bytes_per_row */
nv_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);
eng_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);
/*Perform the very long mode switch!*/
if (target.flags & DUALHEAD_BITS) /*if some dualhead mode*/
@ -112,8 +112,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* detect which connectors have a CRT connected */
//fixme: 'hot-plugging' for analog monitors removed: remove code as well;
//or make it work with digital panels connected as well.
// crt1 = nv_dac_crt_connected();
// crt2 = nv_dac2_crt_connected();
// crt1 = eng_dac_crt_connected();
// crt2 = eng_dac2_crt_connected();
/* connect outputs 'straight-through' */
// if (crt1)
// {
@ -132,9 +132,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* set output connectors assignment if possible */
if ((target.flags & DUALHEAD_BITS) == DUALHEAD_SWITCH)
/* invert output assignment in switch mode */
nv_general_head_select(true);
eng_general_head_select(true);
else
nv_general_head_select(false);
eng_general_head_select(false);
/* set the pixel clock PLL(s) */
LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
@ -245,8 +245,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* detect which connectors have a CRT connected */
//fixme: 'hot-plugging' for analog monitors removed: remove code as well;
//or make it work with digital panels connected as well.
// crt1 = nv_dac_crt_connected();
// crt2 = nv_dac2_crt_connected();
// crt1 = eng_dac_crt_connected();
// crt2 = eng_dac2_crt_connected();
/* connect outputs 'straight-through' */
// if (crt1)
// {
@ -263,7 +263,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
// cross = false;
// }
/* set output connectors assignment if possible */
nv_general_head_select(false);
eng_general_head_select(false);
}
switch(target.space)
@ -310,9 +310,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
if (target.flags & DUALHEAD_BITS) head2_dpms(display,h,v);
/* set up acceleration for this mode */
nv_acc_init();
eng_acc_init();
/* set up overlay unit for this mode */
nv_bes_init();
eng_bes_init();
LOG(1,("SETMODE: booted since %f mS\n", system_time()/1000.0));

4
src/add-ons/accelerants/skeleton/acc_std.h
View File

@ -9,9 +9,9 @@
#include <stdio.h>
#include <sys/ioctl.h>
#include "DriverInterface.h"
#include "nv_globals.h"
#include "globals.h"
//apsed #include "nv_extern.h"
#include "nv_proto.h"
#include "proto.h"
#include "be_driver_proto.h"
#endif

2
src/add-ons/accelerants/skeleton/engine/Jamfile
View File

@ -6,7 +6,7 @@ UsePrivateHeaders [ FDirName graphics skeleton ] ;
StaticLibrary skeleton_engine :
acc.c
bes.c
brooktreetv.c
tvout.c
crtc.c
crtc2.c
dac.c

22
src/add-ons/accelerants/skeleton/engine/acc.c
View File

@ -7,7 +7,7 @@
#define MODULE_BIT 0x00080000
#include "nv_std.h"
#include "std.h"
/*acceleration notes*/
@ -18,7 +18,7 @@ invert rectangle
blit
*/
status_t nv_acc_wait_idle()
status_t eng_acc_wait_idle()
{
/* wait until engine completely idle */
while (ACCR(STATUS))
@ -32,7 +32,7 @@ status_t nv_acc_wait_idle()
/* AFAIK this must be done for every new screenmode.
* Engine required init. */
status_t nv_acc_init()
status_t eng_acc_init()
{
uint16 cnt;
@ -698,7 +698,7 @@ status_t nv_acc_init()
}
/* screen to screen blit - i.e. move windows around and scroll within them. */
status_t nv_acc_setup_blit()
status_t eng_acc_setup_blit()
{
/* setup solid pattern:
* wait for room in fifo for pattern cmd if needed.
@ -729,7 +729,7 @@ status_t nv_acc_setup_blit()
return B_OK;
}
status_t nv_acc_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h)
status_t eng_acc_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h)
{
/* Note: blit-copy direction is determined inside riva hardware: no setup needed */
@ -751,7 +751,7 @@ status_t nv_acc_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h)
/* rectangle fill - i.e. workspace and window background color */
/* span fill - i.e. (selected) menuitem background color (Dano) */
status_t nv_acc_setup_rectangle(uint32 color)
status_t eng_acc_setup_rectangle(uint32 color)
{
/* setup solid pattern:
* wait for room in fifo for pattern cmd if needed.
@ -793,7 +793,7 @@ status_t nv_acc_setup_rectangle(uint32 color)
return B_OK;
}
status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
status_t eng_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
{
/* instruct engine what to fill:
* wait for room in fifo for bitmap cmd if needed.
@ -811,7 +811,7 @@ status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
}
/* rectangle invert - i.e. text cursor and text selection */
status_t nv_acc_setup_rect_invert()
status_t eng_acc_setup_rect_invert()
{
/* setup solid pattern:
* wait for room in fifo for pattern cmd if needed.
@ -853,7 +853,7 @@ status_t nv_acc_setup_rect_invert()
return B_OK;
}
status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
status_t eng_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
{
/* instruct engine what to invert:
* wait for room in fifo for bitmap cmd if needed.
@ -871,7 +871,7 @@ status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl)
}
/* screen to screen tranparent blit */
status_t nv_acc_transparent_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h,uint32 colour)
status_t eng_acc_transparent_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h,uint32 colour)
{
//fixme: implement.
@ -879,7 +879,7 @@ status_t nv_acc_transparent_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16
}
/* screen to screen scaled filtered blit - i.e. scale video in memory */
status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
status_t eng_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
uint16 xd,uint16 yd,uint16 wd,uint16 hd)
{
//fixme: implement.

18
src/add-ons/accelerants/skeleton/engine/agp.c
View File

@ -5,12 +5,12 @@
#define MODULE_BIT 0x00000100
#include <unistd.h>
#include "nv_std.h"
#include "std.h"
static void nv_agp_list_info(agp_info ai);
static void nv_agp_list_active(uint32 cmd);
static void eng_agp_list_info(agp_info ai);
static void eng_agp_list_active(uint32 cmd);
status_t nv_agp_setup(void)
status_t eng_agp_setup(void)
{
nv_nth_agp_info nai;
nv_cmd_agp nca;
@ -82,7 +82,7 @@ status_t nv_agp_setup(void)
}
/* log capabilities */
nv_agp_list_info(nai.agpi);
eng_agp_list_info(nai.agpi);
}
/* if our card is not an AGP type, abort here */
@ -126,14 +126,14 @@ status_t nv_agp_setup(void)
/* list mode now activated,
* make sure we have the correct speed scheme for logging */
nv_agp_list_active(nca.cmd | (nv_ai.interface.agp_stat & AGP_rate_rev));
eng_agp_list_active(nca.cmd | (nv_ai.interface.agp_stat & AGP_rate_rev));
/* extra check */
LOG(4,("AGP: graphics card AGPCMD register readback $%08x\n", CFGR(AGPCMD)));
return B_OK;
}
static void nv_agp_list_info(agp_info ai)
static void eng_agp_list_info(agp_info ai)
{
/*
list device
@ -181,10 +181,10 @@ static void nv_agp_list_info(agp_info ai)
list current settings,
make sure we have the correct speed scheme for logging
*/
nv_agp_list_active(ai.interface.agp_cmd | (ai.interface.agp_stat & AGP_rate_rev));
eng_agp_list_active(ai.interface.agp_cmd | (ai.interface.agp_stat & AGP_rate_rev));
}
static void nv_agp_list_active(uint32 cmd)
static void eng_agp_list_active(uint32 cmd)
{
LOG(4,("AGP: listing settings now in use:\n"));
if (!(cmd & AGP_rate_rev))

38
src/add-ons/accelerants/skeleton/engine/bes.c
View File

@ -3,7 +3,7 @@
#define MODULE_BIT 0x00000200
#include "nv_std.h"
#include "std.h"
typedef struct move_overlay_info move_overlay_info;
@ -16,25 +16,25 @@ struct move_overlay_info
uint32 a1orgv; /* alternate source clipping via startadress of source buffer */
};
static void nv_bes_calc_move_overlay(move_overlay_info *moi);
static void nv_bes_program_move_overlay(move_overlay_info moi);
static void eng_bes_calc_move_overlay(move_overlay_info *moi);
static void eng_bes_program_move_overlay(move_overlay_info moi);
/* move the overlay output window in virtualscreens */
/* Note:
* si->dm.h_display_start and si->dm.v_display_start determine where the new
* output window is located! */
void nv_bes_move_overlay()
void eng_bes_move_overlay()
{
move_overlay_info moi;
/* abort if overlay is not active */
if (!si->overlay.active) return;
nv_bes_calc_move_overlay(&moi);
nv_bes_program_move_overlay(moi);
eng_bes_calc_move_overlay(&moi);
eng_bes_program_move_overlay(moi);
}
static void nv_bes_calc_move_overlay(move_overlay_info *moi)
static void eng_bes_calc_move_overlay(move_overlay_info *moi)
{
/* misc used variables */
uint16 temp1, temp2;
@ -50,12 +50,12 @@ static void nv_bes_calc_move_overlay(move_overlay_info *moi)
case DUALHEAD_SWITCH:
if ((si->overlay.ow.h_start + (si->overlay.ow.width / 2)) <
(si->dm.h_display_start + si->dm.timing.h_display))
nv_bes_to_crtc(si->crtc_switch_mode);
eng_bes_to_crtc(si->crtc_switch_mode);
else
nv_bes_to_crtc(!si->crtc_switch_mode);
eng_bes_to_crtc(!si->crtc_switch_mode);
break;
default:
nv_bes_to_crtc(si->crtc_switch_mode);
eng_bes_to_crtc(si->crtc_switch_mode);
break;
}
}
@ -289,7 +289,7 @@ static void nv_bes_calc_move_overlay(move_overlay_info *moi)
LOG(4,("Overlay: topleft corner of input bitmap (cardRAM offset) $%08x\n", moi->a1orgv));
}
static void nv_bes_program_move_overlay(move_overlay_info moi)
static void eng_bes_program_move_overlay(move_overlay_info moi)
{
/*************************************
*** sync to BES (Back End Scaler) ***
@ -349,7 +349,7 @@ static void nv_bes_program_move_overlay(move_overlay_info moi)
}
}
status_t nv_bes_to_crtc(bool crtc)
status_t eng_bes_to_crtc(bool crtc)
{
if (si->ps.secondary_head)
{
@ -377,7 +377,7 @@ status_t nv_bes_to_crtc(bool crtc)
}
}
status_t nv_bes_init()
status_t eng_bes_init()
{
if (si->ps.card_arch < NV10A)
{
@ -469,7 +469,7 @@ status_t nv_configure_bes
LOG(4,("Overlay: inputbuffer view (zoom) left %d, top %d, width %d, height %d\n",
my_ov.h_start, my_ov.v_start, my_ov.width, my_ov.height));
/* save for nv_bes_calc_move_overlay() */
/* save for eng_bes_calc_move_overlay() */
si->overlay.ow = *ow;
si->overlay.ob = *ob;
si->overlay.my_ov = my_ov;
@ -518,7 +518,7 @@ status_t nv_configure_bes
/* correct factor to prevent most-right visible 'line' from distorting */
ifactor -= (1 << 2);
hiscalv = ifactor;
/* save for nv_bes_calc_move_overlay() */
/* save for eng_bes_calc_move_overlay() */
si->overlay.h_ifactor = ifactor;
LOG(4,("Overlay: horizontal scaling factor is %f\n", (float)65536 / ifactor));
@ -611,7 +611,7 @@ status_t nv_configure_bes
/* preserve ifactor for source positioning calculations later on */
viscalv = ifactor;
/* save for nv_bes_calc_move_overlay() */
/* save for eng_bes_calc_move_overlay() */
si->overlay.v_ifactor = ifactor;
/* check scaling factor (and modify if needed) to be within scaling limits */
@ -663,7 +663,7 @@ status_t nv_configure_bes
/********************************************************************************
*** setup all edges of output window, setup horizontal and vertical clipping ***
********************************************************************************/
nv_bes_calc_move_overlay(&moi);
eng_bes_calc_move_overlay(&moi);
/*****************************
@ -842,7 +842,7 @@ status_t nv_configure_bes
}
}
/* note that overlay is in use (for nv_bes_move_overlay()) */
/* note that overlay is in use (for eng_bes_move_overlay()) */
si->overlay.active = true;
return B_OK;
@ -861,7 +861,7 @@ status_t nv_release_bes()
BESW(NV10_GENCTRL, 0x00000001);
}
/* note that overlay is not in use (for nv_bes_move_overlay()) */
/* note that overlay is not in use (for eng_bes_move_overlay()) */
si->overlay.active = false;
return B_OK;

28
src/add-ons/accelerants/skeleton/engine/crtc.c
View File

@ -5,10 +5,10 @@
#define MODULE_BIT 0x00040000
#include "nv_std.h"
#include "std.h"
/*Adjust passed parameters to a valid mode line*/
status_t nv_crtc_validate_timing(
status_t eng_crtc_validate_timing(
uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
)
@ -89,7 +89,7 @@ status_t nv_crtc_validate_timing(
}
/*set a mode line - inputs are in pixels*/
status_t nv_crtc_set_timing(display_mode target)
status_t eng_crtc_set_timing(display_mode target)
{
uint8 temp;
@ -429,7 +429,7 @@ status_t nv_crtc_set_timing(display_mode target)
return B_OK;
}
status_t nv_crtc_depth(int mode)
status_t eng_crtc_depth(int mode)
{
uint8 viddelay = 0;
uint32 genctrl = 0;
@ -472,7 +472,7 @@ status_t nv_crtc_depth(int mode)
return B_OK;
}
status_t nv_crtc_dpms(bool display, bool h, bool v)
status_t eng_crtc_dpms(bool display, bool h, bool v)
{
uint8 temp;
@ -556,7 +556,7 @@ status_t nv_crtc_dpms(bool display, bool h, bool v)
return B_OK;
}
status_t nv_crtc_dpms_fetch(bool *display, bool *h, bool *v)
status_t eng_crtc_dpms_fetch(bool *display, bool *h, bool *v)
{
/* enable access to primary head */
set_crtc_owner(0);
@ -576,7 +576,7 @@ status_t nv_crtc_dpms_fetch(bool *display, bool *h, bool *v)
return B_OK;
}
status_t nv_crtc_set_display_pitch()
status_t eng_crtc_set_display_pitch()
{
uint32 offset;
@ -597,7 +597,7 @@ status_t nv_crtc_set_display_pitch()
return B_OK;
}
status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp)
status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp)
{
uint8 temp;
uint32 timeout = 0;
@ -655,7 +655,7 @@ status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp)
return B_OK;
}
status_t nv_crtc_cursor_init()
status_t eng_crtc_cursor_init()
{
int i;
uint32 * fb;
@ -702,12 +702,12 @@ status_t nv_crtc_cursor_init()
NV_REG32(NV32_CURCONF) = 0x02000100;
/* activate hardware cursor */
nv_crtc_cursor_show();
eng_crtc_cursor_show();
return B_OK;
}
status_t nv_crtc_cursor_show()
status_t eng_crtc_cursor_show()
{
LOG(4,("CRTC: enabling cursor\n"));
@ -720,7 +720,7 @@ status_t nv_crtc_cursor_show()
return B_OK;
}
status_t nv_crtc_cursor_hide()
status_t eng_crtc_cursor_hide()
{
LOG(4,("CRTC: disabling cursor\n"));
@ -734,7 +734,7 @@ status_t nv_crtc_cursor_hide()
}
/*set up cursor shape*/
status_t nv_crtc_cursor_define(uint8* andMask,uint8* xorMask)
status_t eng_crtc_cursor_define(uint8* andMask,uint8* xorMask)
{
int x, y;
uint8 b;
@ -788,7 +788,7 @@ status_t nv_crtc_cursor_define(uint8* andMask,uint8* xorMask)
}
/* position the cursor */
status_t nv_crtc_cursor_position(uint16 x, uint16 y)
status_t eng_crtc_cursor_position(uint16 x, uint16 y)
{
uint16 yhigh;

28
src/add-ons/accelerants/skeleton/engine/crtc2.c
View File

@ -5,10 +5,10 @@
#define MODULE_BIT 0x00020000
#include "nv_std.h"
#include "std.h"
/*Adjust passed parameters to a valid mode line*/
status_t nv_crtc2_validate_timing(
status_t eng_crtc2_validate_timing(
uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
)
@ -75,7 +75,7 @@ status_t nv_crtc2_validate_timing(
}
/*set a mode line - inputs are in pixels*/
status_t nv_crtc2_set_timing(display_mode target)
status_t eng_crtc2_set_timing(display_mode target)
{
uint8 temp;
@ -412,7 +412,7 @@ status_t nv_crtc2_set_timing(display_mode target)
return B_OK;
}
status_t nv_crtc2_depth(int mode)
status_t eng_crtc2_depth(int mode)
{
uint8 viddelay = 0;
uint32 genctrl = 0;
@ -455,7 +455,7 @@ status_t nv_crtc2_depth(int mode)
return B_OK;
}
status_t nv_crtc2_dpms(bool display, bool h, bool v)
status_t eng_crtc2_dpms(bool display, bool h, bool v)
{
uint8 temp;
@ -539,7 +539,7 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v)
return B_OK;
}
status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v)
status_t eng_crtc2_dpms_fetch(bool *display, bool *h, bool *v)
{
/* enable access to secondary head */
set_crtc_owner(1);
@ -559,7 +559,7 @@ status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v)
return B_OK;
}
status_t nv_crtc2_set_display_pitch()
status_t eng_crtc2_set_display_pitch()
{
uint32 offset;
@ -580,7 +580,7 @@ status_t nv_crtc2_set_display_pitch()
return B_OK;
}
status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp)
status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
{
uint32 timeout = 0;
@ -617,7 +617,7 @@ status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp)
return B_OK;
}
status_t nv_crtc2_cursor_init()
status_t eng_crtc2_cursor_init()
{
int i;
uint32 * fb;
@ -664,12 +664,12 @@ status_t nv_crtc2_cursor_init()
NV_REG32(NV32_2CURCONF) = 0x02000100;
/* activate hardware cursor */
nv_crtc2_cursor_show();
eng_crtc2_cursor_show();
return B_OK;
}
status_t nv_crtc2_cursor_show()
status_t eng_crtc2_cursor_show()
{
LOG(4,("CRTC2: enabling cursor\n"));
@ -682,7 +682,7 @@ status_t nv_crtc2_cursor_show()
return B_OK;
}
status_t nv_crtc2_cursor_hide()
status_t eng_crtc2_cursor_hide()
{
LOG(4,("CRTC2: disabling cursor\n"));
@ -696,7 +696,7 @@ status_t nv_crtc2_cursor_hide()
}
/*set up cursor shape*/
status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask)
status_t eng_crtc2_cursor_define(uint8* andMask,uint8* xorMask)
{
int x, y;
uint8 b;
@ -750,7 +750,7 @@ status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask)
}
/* position the cursor */
status_t nv_crtc2_cursor_position(uint16 x, uint16 y)
status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
{
uint16 yhigh;

18
src/add-ons/accelerants/skeleton/engine/dac.c
View File

@ -5,13 +5,13 @@
#define MODULE_BIT 0x00010000
#include "nv_std.h"
#include "std.h"
static status_t nv4_nv10_nv20_dac_pix_pll_find(
display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test);
/* see if an analog VGA monitor is connected to connector #1 */
bool nv_dac_crt_connected(void)
bool eng_dac_crt_connected(void)
{
uint32 output, dac;
bool present;
@ -61,7 +61,7 @@ bool nv_dac_crt_connected(void)
}
/*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/
status_t nv_dac_mode(int mode,float brightness)
status_t eng_dac_mode(int mode,float brightness)
{
uint8 *r,*g,*b;
int i, ri;
@ -81,7 +81,7 @@ status_t nv_dac_mode(int mode,float brightness)
b[i] = g[i] = r[i] = ri;
}
if (nv_dac_palette(r,g,b) != B_OK) return B_ERROR;
if (eng_dac_palette(r,g,b) != B_OK) return B_ERROR;
/* disable palette RAM adressing mask */
NV_REG8(NV8_PALMASK) = 0xff;
@ -91,7 +91,7 @@ status_t nv_dac_mode(int mode,float brightness)
}
/*program the DAC palette using the given r,g,b values*/
status_t nv_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256])
status_t eng_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256])
{
int i;
@ -133,7 +133,7 @@ if (1)
}
/*program the pixpll - frequency in kHz*/
status_t nv_dac_set_pix_pll(display_mode target)
status_t eng_dac_set_pix_pll(display_mode target)
{
uint8 m=0,n=0,p=0;
// uint time = 0;
@ -167,7 +167,7 @@ status_t nv_dac_set_pix_pll(display_mode target)
LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));
/* signal that we actually want to set the mode */
result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
result = eng_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
if (result != B_OK)
{
return result;
@ -207,7 +207,7 @@ status_t nv_dac_set_pix_pll(display_mode target)
}
/* find nearest valid pix pll */
status_t nv_dac_pix_pll_find
status_t eng_dac_pix_pll_find
(display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
{
switch (si->ps.card_type) {
@ -384,7 +384,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
}
/* find nearest valid system PLL setting */
status_t nv_dac_sys_pll_find(
status_t eng_dac_sys_pll_find(
float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, uint8* p_result, uint8 test)
{
int m = 0, n = 0, p = 0, m_max, p_max;

16
src/add-ons/accelerants/skeleton/engine/dac2.c
View File

@ -5,13 +5,13 @@
#define MODULE_BIT 0x00001000
#include "nv_std.h"
#include "std.h"
static status_t nv10_nv20_dac2_pix_pll_find(
display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test);
/* see if an analog VGA monitor is connected to connector #2 */
bool nv_dac2_crt_connected()
bool eng_dac2_crt_connected()
{
uint32 output, dac;
bool present;
@ -69,7 +69,7 @@ bool nv_dac2_crt_connected()
}
/*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/
status_t nv_dac2_mode(int mode,float brightness)
status_t eng_dac2_mode(int mode,float brightness)
{
uint8 *r,*g,*b;
int i, ri;
@ -89,7 +89,7 @@ status_t nv_dac2_mode(int mode,float brightness)
b[i] = g[i] = r[i] = ri;
}
if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR;
if (eng_dac2_palette(r,g,b) != B_OK) return B_ERROR;
/* disable palette RAM adressing mask */
NV_REG8(NV8_PAL2MASK) = 0xff;
@ -99,7 +99,7 @@ status_t nv_dac2_mode(int mode,float brightness)
}
/*program the DAC palette using the given r,g,b values*/
status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256])
status_t eng_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256])
{
int i;
@ -141,7 +141,7 @@ if (1)
}
/*program the pixpll - frequency in kHz*/
status_t nv_dac2_set_pix_pll(display_mode target)
status_t eng_dac2_set_pix_pll(display_mode target)
{
uint8 m=0,n=0,p=0;
// uint time = 0;
@ -175,7 +175,7 @@ status_t nv_dac2_set_pix_pll(display_mode target)
LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk));
/* signal that we actually want to set the mode */
result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
result = eng_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
if (result != B_OK)
{
return result;
@ -215,7 +215,7 @@ status_t nv_dac2_set_pix_pll(display_mode target)
}
/* find nearest valid pix pll */
status_t nv_dac2_pix_pll_find
status_t eng_dac2_pix_pll_find
(display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
{
switch (si->ps.card_type) {

764
src/add-ons/accelerants/skeleton/engine/general.c
View File

@ -1,16 +1,16 @@
/* Authors:
Mark Watson 12/1999,
Apsed,
Rudolf Cornelissen 10/2002-9/2004
Rudolf Cornelissen 10/2002-11/2004
*/
#define MODULE_BIT 0x00008000
#include "nv_std.h"
#include "std.h"
static status_t test_ram(void);
static status_t nvxx_general_powerup (void);
static status_t nv_general_bios_to_powergraphics(void);
static status_t eng_general_bios_to_powergraphics(void);
static void nv_dump_configuration_space (void)
{
@ -76,11 +76,11 @@ static void nv_dump_configuration_space (void)
#undef DUMP_CFG
}
status_t nv_general_powerup()
status_t eng_general_powerup()
{
status_t status;
LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.30 running.\n"));
LOG(1,("POWERUP: Haiku-OS skeleton Accelerant 0.00 running.\n"));
/* preset no laptop */
si->ps.laptop = false;
@ -89,624 +89,12 @@ status_t nv_general_powerup()
switch(CFGR(DEVID))
{
/* Vendor Nvidia */
case 0x002010de: /* Nvidia TNT1 */
case 0x000010de: /* non-existing card */
si->ps.card_type = NV04;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia TNT1 (NV04)\n"));
status = nvxx_general_powerup();
break;
case 0x002810de: /* Nvidia TNT2 (pro) */
case 0x002910de: /* Nvidia TNT2 Ultra */
case 0x002a10de: /* Nvidia TNT2 */
case 0x002b10de: /* Nvidia TNT2 */
si->ps.card_type = NV05;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia TNT2 (NV05)\n"));
status = nvxx_general_powerup();
break;
case 0x002c10de: /* Nvidia Vanta (Lt) */
si->ps.card_type = NV05;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia Vanta (Lt) (NV05)\n"));
status = nvxx_general_powerup();
break;
case 0x002d10de: /* Nvidia TNT2-M64 (Pro) */
si->ps.card_type = NV05M64;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia TNT2-M64 (Pro) (NV05M64)\n"));
status = nvxx_general_powerup();
break;
case 0x002e10de: /* Nvidia NV06 Vanta */
case 0x002f10de: /* Nvidia NV06 Vanta */
si->ps.card_type = NV06;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia Vanta (NV06)\n"));
status = nvxx_general_powerup();
break;
case 0x004010de: /* Nvidia GeForce FX 6800 Ultra */
case 0x004110de: /* Nvidia GeForce FX 6800 */
case 0x004210de: /* Nvidia GeForce FX 6800LE */
case 0x004510de: /* Nvidia GeForce FX 6800 GT */
si->ps.card_type = NV40;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 6800 (NV40)\n"));
status = nvxx_general_powerup();
break;
case 0x004310de: /* Nvidia unknown FX */
si->ps.card_type = NV40;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia unknown FX (NV40)\n"));
status = nvxx_general_powerup();
break;
case 0x004e10de: /* Nvidia Quadro FX 4000 */
si->ps.card_type = NV40;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 4000 (NV40)\n"));
status = nvxx_general_powerup();
break;
case 0x00a010de: /* Nvidia Aladdin TNT2 */
si->ps.card_type = NV05;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia Aladdin TNT2 (NV05)\n"));
status = nvxx_general_powerup();
break;
case 0x00c010de: /* Nvidia unknown FX */
case 0x00c110de: /* Nvidia unknown FX */
si->ps.card_type = NV41;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia unknown FX (NV41)\n"));
status = nvxx_general_powerup();
break;
case 0x00f810de: /* Nvidia Quadro FX 3400 PCIe(?) */
si->ps.card_type = NV35;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 3400 PCIe(?) (NV35(?))\n"));
status = nvxx_general_powerup();
break;
case 0x00f910de: /* Nvidia GeForce PCX 6800 PCIe */
si->ps.card_type = NV45;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia GeForce PCX 6800 PCIe (NV45)\n"));
status = nvxx_general_powerup();
break;
case 0x00fa10de: /* Nvidia GeForce PCX 5750 PCIe */
si->ps.card_type = NV36;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce PCX 5750 PCIe (NV36(?))\n"));
status = nvxx_general_powerup();
break;
case 0x00fb10de: /* Nvidia GeForce PCX 5900 PCIe */
si->ps.card_type = NV35;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce PCX 5900 PCIe (NV35(?))\n"));
status = nvxx_general_powerup();
break;
case 0x00fc10de: /* Nvidia GeForce PCX 5300 PCIe */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce PCX 5300 PCIe (NV34(?))\n"));
status = nvxx_general_powerup();
break;
case 0x00fd10de: /* Nvidia Quadro PCX PCIe */
si->ps.card_type = NV45;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia Quadro PCX PCIe (NV45)\n"));
status = nvxx_general_powerup();
break;
case 0x00fe10de: /* Nvidia Quadro FX 1300 PCIe(?) */
si->ps.card_type = NV36;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 1300 PCIe(?) (NV36(?))\n"));
status = nvxx_general_powerup();
break;
case 0x010010de: /* Nvidia GeForce256 SDR */
case 0x010110de: /* Nvidia GeForce256 DDR */
case 0x010210de: /* Nvidia GeForce256 Ultra */
si->ps.card_type = NV10;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce256 (NV10)\n"));
status = nvxx_general_powerup();
break;
case 0x010310de: /* Nvidia Quadro */
si->ps.card_type = NV10;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia Quadro (NV10)\n"));
status = nvxx_general_powerup();
break;
case 0x011010de: /* Nvidia GeForce2 MX/MX400 */
case 0x011110de: /* Nvidia GeForce2 MX100/MX200 DDR */
si->ps.card_type = NV11;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce2 MX (NV11)\n"));
status = nvxx_general_powerup();
break;
case 0x011210de: /* Nvidia GeForce2 Go */
si->ps.card_type = NV11;
si->ps.card_arch = NV10A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce2 Go (NV11)\n"));
status = nvxx_general_powerup();
break;
case 0x011310de: /* Nvidia Quadro2 MXR/EX/Go */
si->ps.card_type = NV11;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia Quadro2 MXR/EX/Go (NV11)\n"));
status = nvxx_general_powerup();
break;
case 0x014010de: /* Nvidia GeForce FX 6600 GT */
case 0x014110de: /* Nvidia GeForce FX 6600 */
si->ps.card_type = NV43;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 6600 (NV43)\n"));
status = nvxx_general_powerup();
break;
case 0x014510de: /* Nvidia GeForce FX 6610 XL */
si->ps.card_type = NV43;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 6610 XL (NV43)\n"));
status = nvxx_general_powerup();
break;
case 0x014e10de: /* Nvidia Quadro FX 540 */
si->ps.card_type = NV43;
si->ps.card_arch = NV40A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 540 (NV43)\n"));
status = nvxx_general_powerup();
break;
case 0x015010de: /* Nvidia GeForce2 GTS/Pro */
case 0x015110de: /* Nvidia GeForce2 Ti DDR */
case 0x015210de: /* Nvidia GeForce2 Ultra */
si->ps.card_type = NV15;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce2 (NV15)\n"));
status = nvxx_general_powerup();
break;
case 0x015310de: /* Nvidia Quadro2 Pro */
si->ps.card_type = NV15;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia Quadro2 Pro (NV15)\n"));
status = nvxx_general_powerup();
break;
case 0x017010de: /* Nvidia GeForce4 MX 460 */
case 0x017110de: /* Nvidia GeForce4 MX 440 */
case 0x017210de: /* Nvidia GeForce4 MX 420 */
case 0x017310de: /* Nvidia GeForce4 MX 440SE */
si->ps.card_type = NV17;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce4 MX (NV17)\n"));
status = nvxx_general_powerup();
break;
case 0x017410de: /* Nvidia GeForce4 440 Go */
case 0x017510de: /* Nvidia GeForce4 420 Go */
case 0x017610de: /* Nvidia GeForce4 420 Go 32M */
case 0x017710de: /* Nvidia GeForce4 460 Go */
case 0x017910de: /* Nvidia GeForce4 440 Go 64M (on PPC GeForce4 MX) */
si->ps.card_type = NV17;
si->ps.card_arch = NV10A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce4 Go (NV17)\n"));
status = nvxx_general_powerup();
break;
case 0x017810de: /* Nvidia Quadro4 500 XGL/550 XGL */
case 0x017a10de: /* Nvidia Quadro4 200 NVS/400 NVS */
si->ps.card_type = NV17;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia Quadro4 (NV17)\n"));
status = nvxx_general_powerup();
break;
case 0x017c10de: /* Nvidia Quadro4 500 GoGL */
si->ps.card_type = NV17;
si->ps.card_arch = NV10A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia Quadro4 500 GoGL (NV17)\n"));
status = nvxx_general_powerup();
break;
case 0x017d10de: /* Nvidia GeForce4 410 Go 16M*/
si->ps.card_type = NV17;
si->ps.card_arch = NV10A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce4 410 Go (NV17)\n"));
status = nvxx_general_powerup();
break;
case 0x018110de: /* Nvidia GeForce4 MX 440 AGP8X */
case 0x018210de: /* Nvidia GeForce4 MX 440SE AGP8X */
case 0x018310de: /* Nvidia GeForce4 MX 420 AGP8X */
case 0x018510de: /* Nvidia GeForce4 MX 4000 AGP8X */
si->ps.card_type = NV18;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce4 MX AGP8X (NV18)\n"));
status = nvxx_general_powerup();
break;
case 0x018610de: /* Nvidia GeForce4 448 Go */
case 0x018710de: /* Nvidia GeForce4 488 Go */
si->ps.card_type = NV18;
si->ps.card_arch = NV10A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce4 Go (NV18)\n"));
status = nvxx_general_powerup();
break;
case 0x018810de: /* Nvidia Quadro4 580 XGL */
si->ps.card_type = NV18;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia Quadro4 (NV18)\n"));
status = nvxx_general_powerup();
break;
case 0x018910de: /* Nvidia GeForce4 MX AGP8X */
si->ps.card_type = NV18;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce4 MX AGP8X (NV18)\n"));
status = nvxx_general_powerup();
break;
case 0x018a10de: /* Nvidia Quadro4 280 NVS AGP8X */
case 0x018b10de: /* Nvidia Quadro4 380 XGL */
si->ps.card_type = NV18;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia Quadro4 (NV18)\n"));
status = nvxx_general_powerup();
break;
case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */
si->ps.card_type = NV11;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce2 Integrated GPU (CRUSH, NV11)\n"));
status = nvxx_general_powerup();
break;
case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */
si->ps.card_type = NV17;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Nvidia GeForce4 MX Integrated GPU (NFORCE2, NV17)\n"));
status = nvxx_general_powerup();
break;
case 0x020010de: /* Nvidia GeForce3 */
case 0x020110de: /* Nvidia GeForce3 Ti 200 */
case 0x020210de: /* Nvidia GeForce3 Ti 500 */
si->ps.card_type = NV20;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia GeForce3 (NV20)\n"));
status = nvxx_general_powerup();
break;
case 0x020310de: /* Nvidia Quadro DCC */
si->ps.card_type = NV20;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia Quadro DCC (NV20)\n"));
status = nvxx_general_powerup();
break;
case 0x025010de: /* Nvidia GeForce4 Ti 4600 */
case 0x025110de: /* Nvidia GeForce4 Ti 4400 */
case 0x025210de: /* Nvidia GeForce4 Ti 4600 */
case 0x025310de: /* Nvidia GeForce4 Ti 4200 */
si->ps.card_type = NV25;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia GeForce4 Ti (NV25)\n"));
status = nvxx_general_powerup();
break;
case 0x025810de: /* Nvidia Quadro4 900 XGL */
case 0x025910de: /* Nvidia Quadro4 750 XGL */
case 0x025b10de: /* Nvidia Quadro4 700 XGL */
si->ps.card_type = NV25;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia Quadro4 XGL (NV25)\n"));
status = nvxx_general_powerup();
break;
case 0x028010de: /* Nvidia GeForce4 Ti 4800 AGP8X */
case 0x028110de: /* Nvidia GeForce4 Ti 4200 AGP8X */
si->ps.card_type = NV28;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia GeForce4 Ti AGP8X (NV28)\n"));
status = nvxx_general_powerup();
break;
case 0x028210de: /* Nvidia GeForce4 Ti 4800SE */
si->ps.card_type = NV28;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia GeForce4 Ti 4800SE (NV28)\n"));
status = nvxx_general_powerup();
break;
case 0x028610de: /* Nvidia GeForce4 4200 Go */
si->ps.card_type = NV28;
si->ps.card_arch = NV20A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce4 4200 Go (NV28)\n"));
status = nvxx_general_powerup();
break;
case 0x028810de: /* Nvidia Quadro4 980 XGL */
case 0x028910de: /* Nvidia Quadro4 780 XGL */
si->ps.card_type = NV28;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia Quadro4 XGL (NV28)\n"));
status = nvxx_general_powerup();
break;
case 0x028c10de: /* Nvidia Quadro4 700 GoGL */
si->ps.card_type = NV28;
si->ps.card_arch = NV20A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia Quadro4 700 GoGL (NV28)\n"));
status = nvxx_general_powerup();
break;
case 0x02a010de: /* Nvidia GeForce3 Integrated GPU */
si->ps.card_type = NV20;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Nvidia GeForce3 Integrated GPU (XBOX, NV20)\n"));
status = nvxx_general_powerup();
break;
case 0x030110de: /* Nvidia GeForce FX 5800 Ultra */
case 0x030210de: /* Nvidia GeForce FX 5800 */
si->ps.card_type = NV30;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5800 (NV30)\n"));
status = nvxx_general_powerup();
break;
case 0x030810de: /* Nvidia Quadro FX 2000 */
case 0x030910de: /* Nvidia Quadro FX 1000 */
si->ps.card_type = NV30;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX (NV30)\n"));
status = nvxx_general_powerup();
break;
case 0x031110de: /* Nvidia GeForce FX 5600 Ultra */
case 0x031210de: /* Nvidia GeForce FX 5600 */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5600 (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x031310de: /* Nvidia unknown FX */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia unknown FX (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x031410de: /* Nvidia GeForce FX 5600XT */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5600XT (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x031610de: /* Nvidia unknown FX Go */
case 0x031710de: /* Nvidia unknown FX Go */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x031a10de: /* Nvidia GeForce FX 5600 Go */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5600 Go (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x031b10de: /* Nvidia GeForce FX 5650 Go */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5650 Go (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x031c10de: /* Nvidia Quadro FX 700 Go */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 700 Go (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x031d10de: /* Nvidia unknown FX Go */
case 0x031e10de: /* Nvidia unknown FX Go */
case 0x031f10de: /* Nvidia unknown FX Go */
si->ps.card_type = NV31;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV31)\n"));
status = nvxx_general_powerup();
break;
case 0x032010de: /* Nvidia GeForce FX 5200 */
case 0x032110de: /* Nvidia GeForce FX 5200 Ultra */
case 0x032210de: /* Nvidia GeForce FX 5200 */
case 0x032310de: /* Nvidia GeForce FX 5200SE */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5200 (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032410de: /* Nvidia GeForce FX 5200 Go */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5200 Go (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032510de: /* Nvidia GeForce FX 5250 Go */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5250 Go (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032610de: /* Nvidia GeForce FX 5500 */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5500 (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032710de: /* Nvidia GeForce FX 5100 */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5100 (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032810de: /* Nvidia GeForce FX 5200 Go 32M/64M */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5200 Go (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032910de: /* Nvidia GeForce FX 5200 (PPC) */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5200 (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032a10de: /* Nvidia Quadro NVS 280 PCI */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro NVS 280 PCI (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032b10de: /* Nvidia Quadro FX 500/600 PCI */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 500/600 PCI (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032c10de: /* Nvidia GeForce FX 5300 Go */
case 0x032d10de: /* Nvidia GeForce FX 5100 Go */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce FX Go (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x032e10de: /* Nvidia unknown FX Go */
case 0x032f10de: /* Nvidia unknown FX Go */
si->ps.card_type = NV34;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV34)\n"));
status = nvxx_general_powerup();
break;
case 0x033010de: /* Nvidia GeForce FX 5900 Ultra */
case 0x033110de: /* Nvidia GeForce FX 5900 */
si->ps.card_type = NV35;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5900 (NV35)\n"));
status = nvxx_general_powerup();
break;
case 0x033210de: /* Nvidia GeForce FX 5900 XT */
si->ps.card_type = NV35;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5900 XT (NV35)\n"));
status = nvxx_general_powerup();
break;
case 0x033310de: /* Nvidia GeForce FX 5950 Ultra */
si->ps.card_type = NV38;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5950 Ultra (NV38)\n"));
status = nvxx_general_powerup();
break;
case 0x033410de: /* Nvidia GeForce FX 5900 ZT */
si->ps.card_type = NV38;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5900 ZT (NV38(?))\n"));
status = nvxx_general_powerup();
break;
case 0x033810de: /* Nvidia Quadro FX 3000 */
si->ps.card_type = NV35;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 3000 (NV35)\n"));
status = nvxx_general_powerup();
break;
case 0x033f10de: /* Nvidia Quadro FX 700 */
si->ps.card_type = NV35;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 700 (NV35)\n"));
status = nvxx_general_powerup();
break;
case 0x034110de: /* Nvidia GeForce FX 5700 Ultra */
case 0x034210de: /* Nvidia GeForce FX 5700 */
case 0x034310de: /* Nvidia GeForce FX 5700LE */
case 0x034410de: /* Nvidia GeForce FX 5700VE */
si->ps.card_type = NV36;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5700 (NV36)\n"));
status = nvxx_general_powerup();
break;
case 0x034710de: /* Nvidia GeForce FX 5700 Go */
case 0x034810de: /* Nvidia GeForce FX 5700 Go */
si->ps.card_type = NV36;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia GeForce FX 5700 Go (NV36)\n"));
status = nvxx_general_powerup();
break;
case 0x034c10de: /* Nvidia Quadro FX 1000 Go */
si->ps.card_type = NV36;
si->ps.card_arch = NV30A;
si->ps.laptop = true;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 1000 Go (NV36)\n"));
status = nvxx_general_powerup();
break;
case 0x034e10de: /* Nvidia Quadro FX 1100 */
si->ps.card_type = NV36;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia Quadro FX 1100 (NV36)\n"));
status = nvxx_general_powerup();
break;
case 0x034f10de: /* Nvidia unknown FX */
si->ps.card_type = NV36;
si->ps.card_arch = NV30A;
LOG(4,("POWERUP: Detected Nvidia unknown FX (NV36(?))\n"));
status = nvxx_general_powerup();
break;
/* Vendor Elsa GmbH */
case 0x0c601048: /* Elsa Gladiac Geforce2 MX */
si->ps.card_type = NV11;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Elsa Gladiac Geforce2 MX (NV11)\n"));
status = nvxx_general_powerup();
break;
/* Vendor Nvidia STB/SGS-Thompson */
case 0x002012d2: /* Nvidia STB/SGS-Thompson TNT1 */
si->ps.card_type = NV04;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia STB/SGS-Thompson TNT1 (NV04)\n"));
status = nvxx_general_powerup();
break;
case 0x002812d2: /* Nvidia STB/SGS-Thompson TNT2 (pro) */
case 0x002912d2: /* Nvidia STB/SGS-Thompson TNT2 Ultra */
case 0x002a12d2: /* Nvidia STB/SGS-Thompson TNT2 */
case 0x002b12d2: /* Nvidia STB/SGS-Thompson TNT2 */
si->ps.card_type = NV05;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia STB/SGS-Thompson TNT2 (NV05)\n"));
status = nvxx_general_powerup();
break;
case 0x002c12d2: /* Nvidia STB/SGS-Thompson Vanta (Lt) */
si->ps.card_type = NV05;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia STB/SGS-Thompson Vanta (Lt) (NV05)\n"));
status = nvxx_general_powerup();
break;
case 0x002d12d2: /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */
si->ps.card_type = NV05M64;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia STB/SGS-Thompson TNT2-M64 (Pro) (NV05M64)\n"));
status = nvxx_general_powerup();
break;
case 0x002e12d2: /* Nvidia STB/SGS-Thompson NV06 Vanta */
case 0x002f12d2: /* Nvidia STB/SGS-Thompson NV06 Vanta */
si->ps.card_type = NV06;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia STB/SGS-Thompson Vanta (NV06)\n"));
status = nvxx_general_powerup();
break;
case 0x00a012d2: /* Nvidia STB/SGS-Thompson Aladdin TNT2 */
si->ps.card_type = NV05;
si->ps.card_arch = NV04A;
LOG(4,("POWERUP: Detected Nvidia STB/SGS-Thompson Aladdin TNT2 (NV05)\n"));
status = nvxx_general_powerup();
break;
/* Vendor Varisys Limited */
case 0x35031888: /* Varisys GeForce4 MX440 */
si->ps.card_type = NV17;
si->ps.card_arch = NV10A;
LOG(4,("POWERUP: Detected Varisys GeForce4 MX440 (NV17)\n"));
status = nvxx_general_powerup();
break;
case 0x35051888: /* Varisys GeForce4 Ti 4200 */
si->ps.card_type = NV25;
si->ps.card_arch = NV20A;
LOG(4,("POWERUP: Detected Varisys GeForce4 Ti 4200 (NV25)\n"));
status = nvxx_general_powerup();
break;
default:
LOG(8,("POWERUP: Failed to detect valid card 0x%08x\n",CFGR(DEVID)));
return B_ERROR;
@ -790,79 +178,79 @@ void setup_virtualized_heads(bool cross)
{
if (cross)
{
head1_validate_timing = (crtc_validate_timing) nv_crtc2_validate_timing;
head1_set_timing = (crtc_set_timing) nv_crtc2_set_timing;
head1_depth = (crtc_depth) nv_crtc2_depth;
head1_dpms = (crtc_dpms) nv_crtc2_dpms;
head1_dpms_fetch = (crtc_dpms_fetch) nv_crtc2_dpms_fetch;
head1_set_display_pitch = (crtc_set_display_pitch) nv_crtc2_set_display_pitch;
head1_set_display_start = (crtc_set_display_start) nv_crtc2_set_display_start;
head1_cursor_init = (crtc_cursor_init) nv_crtc2_cursor_init;
head1_cursor_show = (crtc_cursor_show) nv_crtc2_cursor_show;
head1_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide;
head1_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define;
head1_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position;
head1_validate_timing = (crtc_validate_timing) eng_crtc2_validate_timing;
head1_set_timing = (crtc_set_timing) eng_crtc2_set_timing;
head1_depth = (crtc_depth) eng_crtc2_depth;
head1_dpms = (crtc_dpms) eng_crtc2_dpms;
head1_dpms_fetch = (crtc_dpms_fetch) eng_crtc2_dpms_fetch;
head1_set_display_pitch = (crtc_set_display_pitch) eng_crtc2_set_display_pitch;
head1_set_display_start = (crtc_set_display_start) eng_crtc2_set_display_start;
head1_cursor_init = (crtc_cursor_init) eng_crtc2_cursor_init;
head1_cursor_show = (crtc_cursor_show) eng_crtc2_cursor_show;
head1_cursor_hide = (crtc_cursor_hide) eng_crtc2_cursor_hide;
head1_cursor_define = (crtc_cursor_define) eng_crtc2_cursor_define;
head1_cursor_position = (crtc_cursor_position) eng_crtc2_cursor_position;
head1_mode = (dac_mode) nv_dac2_mode;
head1_palette = (dac_palette) nv_dac2_palette;
head1_set_pix_pll = (dac_set_pix_pll) nv_dac2_set_pix_pll;
head1_pix_pll_find = (dac_pix_pll_find) nv_dac2_pix_pll_find;
head1_mode = (dac_mode) eng_dac2_mode;
head1_palette = (dac_palette) eng_dac2_palette;
head1_set_pix_pll = (dac_set_pix_pll) eng_dac2_set_pix_pll;
head1_pix_pll_find = (dac_pix_pll_find) eng_dac2_pix_pll_find;
head2_validate_timing = (crtc_validate_timing) nv_crtc_validate_timing;
head2_set_timing = (crtc_set_timing) nv_crtc_set_timing;
head2_depth = (crtc_depth) nv_crtc_depth;
head2_dpms = (crtc_dpms) nv_crtc_dpms;
head2_dpms_fetch = (crtc_dpms_fetch) nv_crtc_dpms_fetch;
head2_set_display_pitch = (crtc_set_display_pitch) nv_crtc_set_display_pitch;
head2_set_display_start = (crtc_set_display_start) nv_crtc_set_display_start;
head2_cursor_init = (crtc_cursor_init) nv_crtc_cursor_init;
head2_cursor_show = (crtc_cursor_show) nv_crtc_cursor_show;
head2_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide;
head2_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define;
head2_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position;
head2_validate_timing = (crtc_validate_timing) eng_crtc_validate_timing;
head2_set_timing = (crtc_set_timing) eng_crtc_set_timing;
head2_depth = (crtc_depth) eng_crtc_depth;
head2_dpms = (crtc_dpms) eng_crtc_dpms;
head2_dpms_fetch = (crtc_dpms_fetch) eng_crtc_dpms_fetch;
head2_set_display_pitch = (crtc_set_display_pitch) eng_crtc_set_display_pitch;
head2_set_display_start = (crtc_set_display_start) eng_crtc_set_display_start;
head2_cursor_init = (crtc_cursor_init) eng_crtc_cursor_init;
head2_cursor_show = (crtc_cursor_show) eng_crtc_cursor_show;
head2_cursor_hide = (crtc_cursor_hide) eng_crtc_cursor_hide;
head2_cursor_define = (crtc_cursor_define) eng_crtc_cursor_define;
head2_cursor_position = (crtc_cursor_position) eng_crtc_cursor_position;
head2_mode = (dac_mode) nv_dac_mode;
head2_palette = (dac_palette) nv_dac_palette;
head2_set_pix_pll = (dac_set_pix_pll) nv_dac_set_pix_pll;
head2_pix_pll_find = (dac_pix_pll_find) nv_dac_pix_pll_find;
head2_mode = (dac_mode) eng_dac_mode;
head2_palette = (dac_palette) eng_dac_palette;
head2_set_pix_pll = (dac_set_pix_pll) eng_dac_set_pix_pll;
head2_pix_pll_find = (dac_pix_pll_find) eng_dac_pix_pll_find;
}
else
{
head1_validate_timing = (crtc_validate_timing) nv_crtc_validate_timing;
head1_set_timing = (crtc_set_timing) nv_crtc_set_timing;
head1_depth = (crtc_depth) nv_crtc_depth;
head1_dpms = (crtc_dpms) nv_crtc_dpms;
head1_dpms_fetch = (crtc_dpms_fetch) nv_crtc_dpms_fetch;
head1_set_display_pitch = (crtc_set_display_pitch) nv_crtc_set_display_pitch;
head1_set_display_start = (crtc_set_display_start) nv_crtc_set_display_start;
head1_cursor_init = (crtc_cursor_init) nv_crtc_cursor_init;
head1_cursor_show = (crtc_cursor_show) nv_crtc_cursor_show;
head1_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide;
head1_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define;
head1_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position;
head1_validate_timing = (crtc_validate_timing) eng_crtc_validate_timing;
head1_set_timing = (crtc_set_timing) eng_crtc_set_timing;
head1_depth = (crtc_depth) eng_crtc_depth;
head1_dpms = (crtc_dpms) eng_crtc_dpms;
head1_dpms_fetch = (crtc_dpms_fetch) eng_crtc_dpms_fetch;
head1_set_display_pitch = (crtc_set_display_pitch) eng_crtc_set_display_pitch;
head1_set_display_start = (crtc_set_display_start) eng_crtc_set_display_start;
head1_cursor_init = (crtc_cursor_init) eng_crtc_cursor_init;
head1_cursor_show = (crtc_cursor_show) eng_crtc_cursor_show;
head1_cursor_hide = (crtc_cursor_hide) eng_crtc_cursor_hide;
head1_cursor_define = (crtc_cursor_define) eng_crtc_cursor_define;
head1_cursor_position = (crtc_cursor_position) eng_crtc_cursor_position;
head1_mode = (dac_mode) nv_dac_mode;
head1_palette = (dac_palette) nv_dac_palette;
head1_set_pix_pll = (dac_set_pix_pll) nv_dac_set_pix_pll;
head1_pix_pll_find = (dac_pix_pll_find) nv_dac_pix_pll_find;
head1_mode = (dac_mode) eng_dac_mode;
head1_palette = (dac_palette) eng_dac_palette;
head1_set_pix_pll = (dac_set_pix_pll) eng_dac_set_pix_pll;
head1_pix_pll_find = (dac_pix_pll_find) eng_dac_pix_pll_find;
head2_validate_timing = (crtc_validate_timing) nv_crtc2_validate_timing;
head2_set_timing = (crtc_set_timing) nv_crtc2_set_timing;
head2_depth = (crtc_depth) nv_crtc2_depth;
head2_dpms = (crtc_dpms) nv_crtc2_dpms;
head2_dpms_fetch = (crtc_dpms_fetch) nv_crtc2_dpms_fetch;
head2_set_display_pitch = (crtc_set_display_pitch) nv_crtc2_set_display_pitch;
head2_set_display_start = (crtc_set_display_start) nv_crtc2_set_display_start;
head2_cursor_init = (crtc_cursor_init) nv_crtc2_cursor_init;
head2_cursor_show = (crtc_cursor_show) nv_crtc2_cursor_show;
head2_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide;
head2_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define;
head2_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position;
head2_validate_timing = (crtc_validate_timing) eng_crtc2_validate_timing;
head2_set_timing = (crtc_set_timing) eng_crtc2_set_timing;
head2_depth = (crtc_depth) eng_crtc2_depth;
head2_dpms = (crtc_dpms) eng_crtc2_dpms;
head2_dpms_fetch = (crtc_dpms_fetch) eng_crtc2_dpms_fetch;
head2_set_display_pitch = (crtc_set_display_pitch) eng_crtc2_set_display_pitch;
head2_set_display_start = (crtc_set_display_start) eng_crtc2_set_display_start;
head2_cursor_init = (crtc_cursor_init) eng_crtc2_cursor_init;
head2_cursor_show = (crtc_cursor_show) eng_crtc2_cursor_show;
head2_cursor_hide = (crtc_cursor_hide) eng_crtc2_cursor_hide;
head2_cursor_define = (crtc_cursor_define) eng_crtc2_cursor_define;
head2_cursor_position = (crtc_cursor_position) eng_crtc2_cursor_position;
head2_mode = (dac_mode) nv_dac2_mode;
head2_palette = (dac_palette) nv_dac2_palette;
head2_set_pix_pll = (dac_set_pix_pll) nv_dac2_set_pix_pll;
head2_pix_pll_find = (dac_pix_pll_find) nv_dac2_pix_pll_find;
head2_mode = (dac_mode) eng_dac2_mode;
head2_palette = (dac_palette) eng_dac2_palette;
head2_set_pix_pll = (dac_set_pix_pll) eng_dac2_set_pix_pll;
head2_pix_pll_find = (dac_pix_pll_find) eng_dac2_pix_pll_find;
}
}
@ -936,13 +324,13 @@ static status_t nvxx_general_powerup()
/* do powerup needed from pre-inited card state as done by system POST cardBIOS
* execution or driver coldstart above */
return nv_general_bios_to_powergraphics();
return eng_general_bios_to_powergraphics();
}
/* this routine switches the CRTC/DAC sets to 'connectors', but only for analog
* outputs. We need this to make sure the analog 'switch' is set in the same way the
* digital 'switch' is set by the BIOS or we might not be able to use dualhead. */
status_t nv_general_output_select(bool cross)
status_t eng_general_output_select(bool cross)
{
/* make sure this call is warranted */
if (si->ps.secondary_head)
@ -986,7 +374,7 @@ status_t nv_general_output_select(bool cross)
/* this routine switches CRTC/DAC set use. We need this because it's unknown howto
* switch digital panels to/from a specific CRTC/DAC set. */
status_t nv_general_head_select(bool cross)
status_t eng_general_head_select(bool cross)
{
/* make sure this call is warranted */
if (si->ps.secondary_head)
@ -1015,7 +403,7 @@ status_t nv_general_head_select(bool cross)
/* basic change of card state from VGA to enhanced mode:
* Should work from VGA BIOS POST init state. */
static status_t nv_general_bios_to_powergraphics()
static status_t eng_general_bios_to_powergraphics()
{
/* let acc engine make power off/power on cycle to start 'fresh' */
NV_REG32(NV32_PWRUPCTRL) = 0x13110011;
@ -1158,7 +546,7 @@ static status_t nv_general_bios_to_powergraphics()
* Note:
* This may only be done when no transfers are in progress on the bus, so now
* is probably a good time.. */
nv_agp_setup();
eng_agp_setup();
/* turn screen one on */
head1_dpms(true, true, true);
@ -1173,7 +561,7 @@ static status_t nv_general_bios_to_powergraphics()
* We use acc or crtc granularity constraints based on the 'worst case' scenario.
*
* Mode slopspace is reflected in fbc->bytes_per_row BTW. */
status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode)
status_t eng_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode)
{
uint32 video_pitch;
uint32 acc_mask, crtc_mask;

2
src/add-ons/accelerants/skeleton/engine/globals.c
View File

@ -7,7 +7,7 @@
Rudolf Cornelissen 8/2004
*/
#include "nv_std.h"
#include "std.h"
int fd;
shared_info *si;

2
src/add-ons/accelerants/skeleton/engine/i2c.c
View File

@ -14,7 +14,7 @@
#define MODULE_BIT 0x00004000
#include "nv_std.h"
#include "std.h"
int i2c_set_lines(int clock, int data);
int i2c_get_data(void);

48
src/add-ons/accelerants/skeleton/engine/info.c
View File

@ -6,7 +6,7 @@
#define MODULE_BIT 0x00002000
#include "nv_std.h"
#include "std.h"
/* pins V5.16 and up ROM infoblock stuff */
typedef struct {
@ -44,7 +44,7 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab);
static void setup_ram_config_nv10_up(uint8* rom);
static void setup_ram_config_nv28(uint8* rom);
static status_t translate_ISA_PCI(uint32* reg);
static status_t nv_crtc_setup_fifo(void);
static status_t eng_crtc_setup_fifo(void);
/* Parse the BIOS PINS structure if there */
status_t parse_pins ()
@ -263,12 +263,12 @@ static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 in
}
/* turn off both displays and the hardcursors (also disables transfers) */
nv_crtc_dpms(false, false, false);
nv_crtc_cursor_hide();
eng_crtc_dpms(false, false, false);
eng_crtc_cursor_hide();
if (si->ps.secondary_head)
{
nv_crtc2_dpms(false, false, false);
nv_crtc2_cursor_hide();
eng_crtc2_dpms(false, false, false);
eng_crtc2_cursor_hide();
}
/* execute BIOS coldstart script(s) */
@ -283,7 +283,7 @@ static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 in
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001));
//temporary: should be called from setmode probably..
nv_crtc_setup_fifo();
eng_crtc_setup_fifo();
}
else
{
@ -341,12 +341,12 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
}
/* turn off both displays and the hardcursors (also disables transfers) */
nv_crtc_dpms(false, false, false);
nv_crtc_cursor_hide();
eng_crtc_dpms(false, false, false);
eng_crtc_cursor_hide();
if (si->ps.secondary_head)
{
nv_crtc2_dpms(false, false, false);
nv_crtc2_cursor_hide();
eng_crtc2_dpms(false, false, false);
eng_crtc2_cursor_hide();
}
/* execute all BIOS coldstart script(s) */
@ -389,7 +389,7 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001));
//temporary: should be called from setmode probably..
nv_crtc_setup_fifo();
eng_crtc_setup_fifo();
}
else
{
@ -447,7 +447,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
{
float calced_clk;
uint8 m, n, p;
nv_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0);
eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0);
NV_REG32(reg) = ((p << 16) | (n << 8) | m);
}
log_pll(reg, data2);
@ -746,7 +746,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16
{
float calced_clk;
uint8 m, n, p;
nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
NV_REG32(reg) = ((p << 16) | (n << 8) | m);
}
log_pll(reg, (data / 100));
@ -1100,7 +1100,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
{
float calced_clk;
uint8 m, n, p;
nv_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0);
eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0);
/* programming the PLL needs to be done in steps! (confirmed NV28) */
data = NV_REG32(reg2);
NV_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m);
@ -1699,7 +1699,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
{
float calced_clk;
uint8 m, n, p;
nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0);
/* programming the PLL needs to be done in steps! (confirmed NV28) */
data2 = NV_REG32(reg);
NV_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m);
@ -1964,7 +1964,7 @@ static status_t translate_ISA_PCI(uint32* reg)
}
//fixme: move to crtc sourcefile, also setup for crtc2(?)
static status_t nv_crtc_setup_fifo()
static status_t eng_crtc_setup_fifo()
{
/* enable access to primary head */
set_crtc_owner(0);
@ -2409,16 +2409,16 @@ static void setup_output_matrix()
{
/* setup defaults: */
/* connect analog outputs straight through */
nv_general_output_select(false);
eng_general_output_select(false);
/* presetup by the card's BIOS, we can't change this (lack of info) */
if (si->ps.tmds1_active) si->ps.monitors |= 0x01;
if (si->ps.tmds2_active) si->ps.monitors |= 0x10;
/* detect analog monitors (confirmed working OK on NV18, NV28 and NV34): */
/* sense analog monitor on primary connector */
if (nv_dac_crt_connected()) si->ps.monitors |= 0x02;
if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;
/* sense analog monitor on secondary connector */
if (nv_dac2_crt_connected()) si->ps.monitors |= 0x20;
if (eng_dac2_crt_connected()) si->ps.monitors |= 0x20;
/* setup correct output and head use */
//fixme? add TVout (only, so no CRT(s) connected) support...
@ -2444,7 +2444,7 @@ static void setup_output_matrix()
LOG(2,("INFO: head 2 has nothing connected:\n"));
LOG(2,("INFO: correcting...\n"));
/* cross connect analog outputs so analog panel or CRT gets head 2 */
nv_general_output_select(true);
eng_general_output_select(true);
LOG(2,("INFO: head 1 has a digital panel;\n"));
LOG(2,("INFO: head 2 has an analog panel or CRT:\n"));
LOG(2,("INFO: defaulting to head 1 for primary use.\n"));
@ -2466,7 +2466,7 @@ static void setup_output_matrix()
LOG(2,("INFO: head 2 has a digital panel AND an analog panel or CRT:\n"));
LOG(2,("INFO: correcting...\n"));
/* cross connect analog outputs so analog panel or CRT gets head 1 */
nv_general_output_select(true);
eng_general_output_select(true);
LOG(2,("INFO: head 1 has an analog panel or CRT;\n"));
LOG(2,("INFO: head 2 has a digital panel:\n"));
LOG(2,("INFO: defaulting to head 2 for primary use.\n"));
@ -2509,7 +2509,7 @@ static void setup_output_matrix()
if (si->ps.tmds2_active) si->ps.monitors |= 0x10;
/* detect analog monitor (confirmed working OK on NV11): */
/* sense analog monitor on primary connector */
if (nv_dac_crt_connected()) si->ps.monitors |= 0x02;
if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;
/* (sense analog monitor on secondary connector is impossible on NV11) */
/* setup correct output and head use */
@ -2567,7 +2567,7 @@ static void setup_output_matrix()
if (si->ps.tmds1_active) si->ps.monitors |= 0x01;
/* detect analog monitor (confirmed working OK on all cards): */
/* sense analog monitor on primary connector */
if (nv_dac_crt_connected()) si->ps.monitors |= 0x02;
if (eng_dac_crt_connected()) si->ps.monitors |= 0x02;
//fixme? add TVout (only, so no CRT connected) support...
}

112
src/add-ons/accelerants/skeleton/engine/proto.h
View File

@ -1,15 +1,15 @@
/* general card functions */
status_t nv_general_powerup(void);
status_t eng_general_powerup(void);
status_t nv_set_cas_latency(void);
void setup_virtualized_heads(bool);
void set_crtc_owner(bool);
status_t nv_general_output_select(bool);
status_t nv_general_head_select(bool);
status_t nv_general_wait_retrace(void);
status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode);
status_t eng_general_output_select(bool);
status_t eng_general_head_select(bool);
status_t eng_general_wait_retrace(void);
status_t eng_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode);
/* AGP functions */
status_t nv_agp_setup(void);
status_t eng_agp_setup(void);
/* apsed: logging macros */
#define MSG(args) do { /* if needed or si->settings with si NULL */ \
@ -39,19 +39,19 @@ void set_specs(void);
void dump_pins(void);
/* DAC functions */
bool nv_dac_crt_connected(void);
status_t nv_dac_mode(int,float);
status_t nv_dac_palette(uint8*,uint8*,uint8*);
status_t nv_dac_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
status_t nv_dac_set_pix_pll(display_mode target);
status_t nv_dac_sys_pll_find(float, float*, uint8*, uint8*, uint8*, uint8);
bool eng_dac_crt_connected(void);
status_t eng_dac_mode(int,float);
status_t eng_dac_palette(uint8*,uint8*,uint8*);
status_t eng_dac_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
status_t eng_dac_set_pix_pll(display_mode target);
status_t eng_dac_sys_pll_find(float, float*, uint8*, uint8*, uint8*, uint8);
/* DAC2 functions */
bool nv_dac2_crt_connected(void);
status_t nv_dac2_mode(int,float);
status_t nv_dac2_palette(uint8*,uint8*,uint8*);
status_t nv_dac2_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
status_t nv_dac2_set_pix_pll(display_mode target);
bool eng_dac2_crt_connected(void);
status_t eng_dac2_mode(int,float);
status_t eng_dac2_palette(uint8*,uint8*,uint8*);
status_t eng_dac2_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
status_t eng_dac2_set_pix_pll(display_mode target);
/*MAVENTV functions*/
status_t g100_g400max_maventv_vid_pll_find(
@ -60,64 +60,64 @@ status_t g100_g400max_maventv_vid_pll_find(
int maventv_init(display_mode target);
/* CRTC1 functions */
status_t nv_crtc_validate_timing(
status_t eng_crtc_validate_timing(
uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
);
status_t nv_crtc_set_timing(display_mode target);
status_t nv_crtc_depth(int mode);
status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp);
status_t nv_crtc_set_display_pitch(void);
status_t eng_crtc_set_timing(display_mode target);
status_t eng_crtc_depth(int mode);
status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp);
status_t eng_crtc_set_display_pitch(void);
status_t nv_crtc_dpms(bool, bool, bool);
status_t nv_crtc_dpms_fetch(bool*, bool*, bool*);
status_t nv_crtc_mem_priority(uint8);
status_t eng_crtc_dpms(bool, bool, bool);
status_t eng_crtc_dpms_fetch(bool*, bool*, bool*);
status_t eng_crtc_mem_priority(uint8);
status_t nv_crtc_cursor_init(void); /*Yes, cursor follows CRTC1 - not the DAC!*/
status_t nv_crtc_cursor_define(uint8*,uint8*);
status_t nv_crtc_cursor_position(uint16 x ,uint16 y);
status_t nv_crtc_cursor_show(void);
status_t nv_crtc_cursor_hide(void);
status_t eng_crtc_cursor_init(void); /*Yes, cursor follows CRTC1 - not the DAC!*/
status_t eng_crtc_cursor_define(uint8*,uint8*);
status_t eng_crtc_cursor_position(uint16 x ,uint16 y);
status_t eng_crtc_cursor_show(void);
status_t eng_crtc_cursor_hide(void);
/* CRTC2 functions */
status_t nv_crtc2_validate_timing(
status_t eng_crtc2_validate_timing(
uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
);
status_t nv_crtc2_set_timing(display_mode target);
status_t nv_crtc2_depth(int mode);
status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp);
status_t nv_crtc2_set_display_pitch(void);
status_t eng_crtc2_set_timing(display_mode target);
status_t eng_crtc2_depth(int mode);
status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp);
status_t eng_crtc2_set_display_pitch(void);
status_t nv_crtc2_dpms(bool, bool, bool);
status_t nv_crtc2_dpms_fetch(bool*, bool*, bool*);
status_t nv_crtc2_mem_priority(uint8);
status_t eng_crtc2_dpms(bool, bool, bool);
status_t eng_crtc2_dpms_fetch(bool*, bool*, bool*);
status_t eng_crtc2_mem_priority(uint8);
status_t nv_crtc2_cursor_init(void);
status_t nv_crtc2_cursor_define(uint8*,uint8*);
status_t nv_crtc2_cursor_position(uint16 x ,uint16 y);
status_t nv_crtc2_cursor_show(void);
status_t nv_crtc2_cursor_hide(void);
status_t eng_crtc2_cursor_init(void);
status_t eng_crtc2_cursor_define(uint8*,uint8*);
status_t eng_crtc2_cursor_position(uint16 x ,uint16 y);
status_t eng_crtc2_cursor_show(void);
status_t eng_crtc2_cursor_hide(void);
/* acceleration functions */
status_t check_acc_capability(uint32 feature);
status_t nv_acc_init(void);
status_t nv_acc_setup_blit(void);
status_t nv_acc_blit(uint16,uint16,uint16, uint16,uint16,uint16 );
status_t nv_acc_setup_rectangle(uint32 color);
status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
status_t nv_acc_setup_rect_invert(void);
status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
status_t nv_acc_transparent_blit(uint16,uint16,uint16, uint16,uint16,uint16, uint32);
status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
status_t eng_acc_init(void);
status_t eng_acc_setup_blit(void);
status_t eng_acc_blit(uint16,uint16,uint16, uint16,uint16,uint16 );
status_t eng_acc_setup_rectangle(uint32 color);
status_t eng_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
status_t eng_acc_setup_rect_invert(void);
status_t eng_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
status_t eng_acc_transparent_blit(uint16,uint16,uint16, uint16,uint16,uint16, uint32);
status_t eng_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
uint16 xd,uint16 yd,uint16 wd,uint16 hd);
status_t nv_acc_wait_idle(void);
status_t eng_acc_wait_idle(void);
/* backend scaler functions */
status_t check_overlay_capability(uint32 feature);
void nv_bes_move_overlay(void);
status_t nv_bes_to_crtc(bool crtc);
status_t nv_bes_init(void);
void eng_bes_move_overlay(void);
status_t eng_bes_to_crtc(bool crtc);
status_t eng_bes_init(void);
status_t nv_configure_bes
(const overlay_buffer *ob, const overlay_window *ow,const overlay_view *ov, int offset);
status_t nv_release_bes(void);

8
src/add-ons/accelerants/skeleton/engine/std.h
View File

@ -3,7 +3,7 @@
#include <math.h>
#include <OS.h>
#include "DriverInterface.h"
#include "nv_globals.h"
//apsed #include "nv_extern.h"
#include "nv_proto.h"
#include "nv_macros.h"
#include "globals.h"
//apsed #include "extern.h"
#include "proto.h"
#include "macros.h"

2
src/add-ons/accelerants/skeleton/engine/support.c
View File

@ -5,7 +5,7 @@
#define MODULE_BIT 0x00000800
#include <stdarg.h>
#include "nv_std.h"
#include "std.h"
/*delays in multiple of microseconds*/
void delay(bigtime_t i)

2
src/add-ons/accelerants/skeleton/engine/tvout.c
View File

@ -7,7 +7,7 @@
#define MODULE_BIT 0x00100000
#include "nv_std.h"
#include "std.h"
typedef struct {
uint32 h_total;