sysinfo: Refactor CPU feature flag display
* Remove duplicated code * Add new feature flag field introduced with Ryzen * Add a few missing Intel cache descriptors * Don't show 80000007 on Intel. Reserved. * Clean up language to not show "AMD" flags on Intel
This commit is contained in:
Alexander von Gluck IV
parent
e4e6315ff4
commit
85f64f9049
@ -73,17 +73,19 @@ struct cache_description {
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{0x55, "Inst TLB: 2M/4M-bytes pages, fully associative, 7 entries"},
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{0x56, "L1 Data TLB: 4M-bytes pages, 4-way set associative, 16 entries"},
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{0x57, "L1 Data TLB: 4K-bytes pages, 4-way set associative, 16 entries"},
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{0x59, "L0 Data TLB, 4K-bytes pages, fully associative, 16 entries"},
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{0x5A, "Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries"},
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{0x59, "L0 Data TLB: 4K-bytes pages, fully associative, 16 entries"},
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{0x5A, "L0 Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries"},
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{0x5B, "Data TLB: 4K/4M-bytes pages, fully associative, 64 entries"},
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{0x5C, "Data TLB: 4K/4M-bytes pages, fully associative, 128 entries"},
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{0x5D, "Data TLB: 4K/4M-bytes pages, fully associative, 256 entries"},
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{0x63, "Data TLB: 2M/4M-bytes pages, 4-way set associative, 32 entries"},
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{0x66, "L1 data cache: 8 KB, 4-way set associative, 64 bytes/line, sectored"},
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{0x67, "L1 data cache: 16 KB, 4-way set associative, 64 bytes/line, sectored"},
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{0x68, "L1 data cache: 32 KB, 4-way set associative, 64 bytes/line, sectored"},
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{0x70, "Inst trace cache: 12K µOPs, 8-way set associative"},
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{0x71, "Inst trace cache: 16K µOPs, 8-way set associative"},
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{0x72, "Inst trace cache: 32K µOPs, 8-way set associative"},
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{0x76, "Code TLB: 2M/4M pages, fully, 8 entries"},
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{0x77, /* IA-64 */ "L1 inst cache: 16 KB, 4-way set associative, 64 bytes/line, sectored"},
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{0x79, "L2 cache: 128 KB, 8-way set associative, 64 bytes/line, dual-sectored"},
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{0x7A, "L2 cache: 256 KB, 8-way set associative, 64 bytes/line, dual-sectored"},
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@ -119,8 +121,11 @@ struct cache_description {
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{0xB2, "Inst TLB: 4K-bytes pages, 4-way set associative, 64 entries"},
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{0xB3, "Data TLB: 4K-bytes pages, 4-way set associative, 128 entries"},
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{0xB4, "Data TLB: 4K-bytes pages, 4-way set associative, 256 entries"},
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{0xB5, "Code TLB: 4K-bytes pages, 8-way set associative, 64 entries"},
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{0xB6, "Code TLB: 4K-bytes pages, 8-way set associative, 128 entries"},
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{0xBA, "Data TLB, 4K-bytes pages, 4-way set associative, 64 entries"},
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{0xC0, "Data TLB, 4K-4M bytes pages, 4-way set associative, 8 entries"},
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{0xC3, "Shared 2nd-level TLB: 4K/2M, 6-way set associative, 1536 entries"},
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{0xCA, "Shared 2nd-level TLB: 4K, 4-way set associative, 512 entries"},
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{0xD0, "L3 cache: 512 KB, 4-way set associative, 64-bytes/line"},
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{0xD1, "L3 cache: 1024 KB, 4-way set associative, 64-bytes/line"},
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@ -136,10 +141,60 @@ struct cache_description {
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{0xE4, "L3 cache: 8192 KB, 16-way set associative, 64-bytes/line"},
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{0xF0, "64-byte Prefetching"},
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{0xF1, "128-byte Prefetching"},
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{0xFF, "TODO: Query standard level 0000_0004h instead"},
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{0, NULL}
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};
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/* CPU Features */
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static const char *kFeatures[32] = {
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"FPU", "VME", "DE", "PSE",
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"TSC", "MSR", "PAE", "MCE",
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"CX8", "APIC", NULL, "SEP",
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"MTRR", "PGE", "MCA", "CMOV",
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"PAT", "PSE36", "PSN", "CFLUSH",
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NULL, "DS", "ACPI", "MMX",
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"FXSTR", "SSE", "SSE2", "SS",
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"HTT", "TM", NULL, "PBE",
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};
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/* CPU Extended features */
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static const char *kExtendedFeatures[32] = {
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"SSE3", "PCLMULDQ", "DTES64", "MONITOR", "DS-CPL", "VMX", "SMX", "EST",
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"TM2", "SSSE3", "CNTXT-ID", NULL, "FMA", "CX16", "xTPR", "PDCM",
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NULL, "PCID", "DCA", "SSE4.1", "SSE4.2", "x2APIC", "MOVEB", "POPCNT",
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"TSC-DEADLINE", "AES", "XSAVE", "OSXSAVE", "AVX", "F16C", "RDRND",
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"HYPERVISOR"
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};
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/* AMD Extended features leaf 0x80000001 */
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static const char *kAMDExtFeatures[32] = {
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, "SCE", NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, "NX", NULL, "AMD-MMX", NULL,
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"FXSR", "FFXSR", NULL, "RDTSCP", NULL, "64", "3DNow+", "3DNow!"
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};
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/* AMD Extended features leaf 0x80000007 */
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static const char *kAMDExtFeaturesPower[32] = {
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"TS", "FID", "VID", "TTP", "TM", "STC", "MUL100", "HWPS",
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"ITSC", "CPB", "EFRO", "PFI", "PA", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
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};
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/* AMD Extended features leaf 0x80000008 */
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static const char *kAMDExtFeaturesTwo[32] = {
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"CLZERO", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
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};
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static void
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print_intel_cache_descriptors(enum cpu_vendor vendor, uint32 model,
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cpuid_info *info)
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@ -353,104 +408,13 @@ print_transmeta_features(uint32 features)
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static void
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print_amd_power_management_features(uint32 features)
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print_features(const char** table, uint32 features)
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{
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static const char *kFeatures[6] = {
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"TS", "FID", "VID", "TTP", "TM", "STC",
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};
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int32 found = 4;
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printf("\tPower Management Features:");
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for (int32 i = 0; i < 6; i++) {
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if ((features & (1UL << i)) && kFeatures[i] != NULL) {
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printf("%s%s", found == 0 ? "\t\t" : " ", kFeatures[i]);
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found++;
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if (found > 0 && (found % 16) == 0) {
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putchar('\n');
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found = 0;
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}
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}
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}
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if (found != 0)
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putchar('\n');
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}
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static void
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print_amd_features(uint32 features)
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{
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static const char *kFeatures[32] = {
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, "SCE", NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, "NX", NULL, "AMD-MMX", NULL,
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NULL, "FFXSTR", NULL, "RDTSCP", NULL, "64", "3DNow+", "3DNow!"
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};
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int32 found = 0;
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for (int32 i = 0; i < 32; i++) {
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if ((features & (1UL << i)) && kFeatures[i] != NULL) {
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printf("%s%s", found == 0 ? "\t\t" : " ", kFeatures[i]);
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found++;
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if (found > 0 && (found % 16) == 0) {
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putchar('\n');
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found = 0;
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}
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}
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}
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if (found != 0)
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putchar('\n');
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}
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static void
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print_extended_features(uint32 features)
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{
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static const char *kFeatures[32] = {
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"SSE3", "PCLMULDQ", "DTES64", "MONITOR", "DS-CPL", "VMX", "SMX", "EST",
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"TM2", "SSSE3", "CNTXT-ID", NULL, "FMA", "CX16", "xTPR", "PDCM",
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NULL, "PCID", "DCA", "SSE4.1", "SSE4.2", "x2APIC", "MOVEB", "POPCNT",
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"TSC-DEADLINE", "AES", "XSAVE", "OSXSAVE", "AVX", "F16C", "RDRND",
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"HYPERVISOR"
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};
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int32 found = 0;
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for (int32 i = 0; i < 32; i++) {
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if ((features & (1UL << i)) && kFeatures[i] != NULL) {
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printf("%s%s", found == 0 ? "\t\t" : " ", kFeatures[i]);
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found++;
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if (found > 0 && (found % 16) == 0) {
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putchar('\n');
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found = 0;
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}
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}
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}
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if (found != 0)
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putchar('\n');
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}
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static void
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print_features(uint32 features)
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{
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static const char *kFeatures[32] = {
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"FPU", "VME", "DE", "PSE",
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"TSC", "MSR", "PAE", "MCE",
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"CX8", "APIC", NULL, "SEP",
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"MTRR", "PGE", "MCA", "CMOV",
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"PAT", "PSE36", "PSN", "CFLUSH",
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NULL, "DS", "ACPI", "MMX",
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"FXSTR", "SSE", "SSE2", "SS",
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"HTT", "TM", NULL, "PBE",
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};
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int32 found = 0;
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for (int32 i = 0; i < 32; i++) {
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if ((features & (1UL << i)) && kFeatures[i] != NULL) {
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printf("%s%s", found == 0 ? "\t\t" : " ", kFeatures[i]);
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if ((features & (1UL << i)) && table[i] != NULL) {
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printf("%s%s", found == 0 ? "\t\t" : " ", table[i]);
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found++;
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if (found > 0 && (found % 16) == 0) {
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putchar('\n');
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@ -467,34 +431,32 @@ print_features(uint32 features)
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#if defined(__INTEL__) || defined(__x86_64__)
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static void
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print_processor_signature(enum cpu_vendor vendor, cpuid_info *info,
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const char *prefix)
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print_processor_signature(enum cpu_vendor vendor, cpuid_info *info)
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{
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printf("\tSignature: 0x%1" B_PRIx32 "%1" B_PRIx32 "0%1" B_PRIx32
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"%1" B_PRIx32 "%1" B_PRIx32 "; ", info->eax_1.extended_family,
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info->eax_1.extended_model, info->eax_1.family,
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info->eax_1.model, info->eax_1.stepping);
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if (vendor == B_CPU_VENDOR_AMD) {
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printf("\t%s%sype %" B_PRIu32 ", family %" B_PRIu32 ", model %" B_PRIu32
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", stepping %" B_PRIu32 ", features 0x%08" B_PRIx32 "\n",
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prefix ? prefix : "", prefix && prefix[0] ? "t" : "T",
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printf("Type %" B_PRIu32 ", family %" B_PRIu32 ", model %" B_PRIu32
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", stepping %" B_PRIu32 "\n",
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info->eax_1.type,
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info->eax_1.family + (info->eax_1.family == 0xf
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? info->eax_1.extended_family : 0),
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info->eax_1.model + (info->eax_1.model == 0xf
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? info->eax_1.extended_model << 4 : 0),
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info->eax_1.stepping,
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info->eax_1.features);
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info->eax_1.stepping);
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} else if (vendor == B_CPU_VENDOR_INTEL) {
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// model calculation is different for INTEL
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printf("\t%s%sype %" B_PRIu32 ", family %" B_PRIu32 ", model %" B_PRIu32
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", stepping %" B_PRIu32 ", features 0x%08" B_PRIx32 "\n",
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prefix ? prefix : "", prefix && prefix[0] ? "t" : "T",
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printf("Type %" B_PRIu32 ", family %" B_PRIu32 ", model %" B_PRIu32
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", stepping %" B_PRIu32 "\n",
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info->eax_1.type,
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info->eax_1.family + (info->eax_1.family == 0xf
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? info->eax_1.extended_family : 0),
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info->eax_1.model
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+ ((info->eax_1.family == 0xf || info->eax_1.family == 0x6)
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? info->eax_1.extended_model << 4 : 0),
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info->eax_1.stepping,
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info->eax_1.features);
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info->eax_1.stepping);
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}
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}
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@ -535,6 +497,7 @@ dump_cpu(enum cpu_vendor vendor, uint32 model, int32 cpu)
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// References:
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// http://grafi.ii.pw.edu.pl/gbm/x86/cpuid.html
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// http://www.sandpile.org/ia32/cpuid.htm
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// http://www.sandpile.org/x86/cpuid.htm
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// http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/TN13.pdf (Duron erratum)
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cpuid_info baseInfo;
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@ -598,31 +561,39 @@ dump_cpu(enum cpu_vendor vendor, uint32 model, int32 cpu)
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}
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get_cpuid(&cpuInfo, 1, cpu);
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// Dump Raw CPUID
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printf("\tRaw CPUID: 0x%1" B_PRIx32 "%1" B_PRIx32 "0%1" B_PRIx32
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"%1" B_PRIx32 "%1" B_PRIx32 ", ", cpuInfo.eax_1.extended_family,
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cpuInfo.eax_1.extended_model, cpuInfo.eax_1.family,
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cpuInfo.eax_1.model, cpuInfo.eax_1.stepping);
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print_processor_signature(vendor, &cpuInfo, NULL);
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print_features(cpuInfo.eax_1.features);
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print_processor_signature(vendor, &cpuInfo);
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printf("\tFeatures: 0x%08" B_PRIx32 "\n", cpuInfo.eax_1.features);
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print_features(kFeatures, cpuInfo.eax_1.features);
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if (maxStandardFunction >= 1) {
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/* Extended features */
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printf("\tExtended Intel: 0x%08" B_PRIx32 "\n", cpuInfo.eax_1.extended_features);
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print_extended_features(cpuInfo.eax_1.extended_features);
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printf("\tExtended Features (0x00000001): 0x%08" B_PRIx32 "\n",
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cpuInfo.eax_1.extended_features);
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print_features(kExtendedFeatures, cpuInfo.eax_1.extended_features);
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}
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/* Extended CPUID */
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/* Extended CPUID Information */
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if (maxExtendedFunction >= 1) {
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get_cpuid(&cpuInfo, 0x80000001, cpu);
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print_processor_signature(vendor, &cpuInfo, "Extended AMD: ");
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if (vendor == B_CPU_VENDOR_INTEL || vendor == B_CPU_VENDOR_AMD) {
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// 0x80000001 EDX has overlap of 64,ED,SY/SE between amd and intel
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printf("\tExtended Features (0x80000001): 0x%08" B_PRIx32 "\n",
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cpuInfo.eax_1.features);
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print_features(kAMDExtFeatures, cpuInfo.regs.edx);
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}
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if (vendor == B_CPU_VENDOR_AMD || vendor == B_CPU_VENDOR_INTEL) {
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print_amd_features(cpuInfo.regs.edx);
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if (vendor == B_CPU_VENDOR_AMD) {
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if (maxExtendedFunction >= 7) {
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get_cpuid(&cpuInfo, 0x80000007, cpu);
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print_amd_power_management_features(cpuInfo.regs.edx);
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printf("\tExtended Features (0x80000007): 0x%08" B_PRIx32 "\n",
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cpuInfo.regs.edx);
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print_features(kAMDExtFeaturesPower, cpuInfo.regs.edx);
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}
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if (maxExtendedFunction >= 8) {
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get_cpuid(&cpuInfo, 0x80000008, cpu);
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printf("\tExtended Features (0x80000008): 0x%08" B_PRIx32 "\n",
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cpuInfo.regs.ebx);
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print_features(kAMDExtFeaturesTwo, cpuInfo.regs.ebx);
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}
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} else if (vendor == B_CPU_VENDOR_TRANSMETA)
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print_transmeta_features(cpuInfo.regs.edx);
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