From 85344c112ca7a226e2ada0f2887db9d6334292bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Duval?= Date: Sat, 4 Jun 2022 21:31:36 +0200 Subject: [PATCH] intel_extreme: also set hw_cdclk on Broadwell this needed for dp aux before skylake, only for DP A (eDP). should help with #17771 Change-Id: I4bdcca1fdc05294fb5b56c5c96164b6936a5881e Reviewed-on: https://review.haiku-os.org/c/haiku/+/5355 Tested-by: Commit checker robot Reviewed-by: Adrien Destugues --- .../private/graphics/intel_extreme/intel_extreme.h | 2 ++ .../graphics/intel_extreme/intel_extreme.cpp | 14 +++++++++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index 933e239e5a..cad0f7dc3a 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -923,6 +923,8 @@ struct intel_brightness_legacy { #define LCPLL_CTL 0x130040 #define LCPLL_CLK_FREQ_MASK (3 << 26) #define LCPLL_CLK_FREQ_450 (0 << 26) +#define LCPLL_CLK_FREQ_54O_BDW (1 << 26) +#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) #define LCPLL_CD_SOURCE_FCLK (1 << 21) // display diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index 2220305175..1e541a9b86 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp @@ -879,7 +879,19 @@ intel_extreme_init(intel_info &info) info.shared_info->fdi_link_frequency = 0; } - if (info.device_type.InGroup(INTEL_GROUP_HAS)) { + if (info.device_type.InGroup(INTEL_GROUP_BDW)) { + uint32 lcpll = read32(info, LCPLL_CTL); + if ((lcpll & LCPLL_CD_SOURCE_FCLK) != 0) + info.shared_info->hw_cdclk = 800000; + else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450) + info.shared_info->hw_cdclk = 450000; + else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_54O_BDW) + info.shared_info->hw_cdclk = 540000; + else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_337_5_BDW) + info.shared_info->hw_cdclk = 337500; + else + info.shared_info->hw_cdclk = 675000; + } else if (info.device_type.InGroup(INTEL_GROUP_HAS)) { uint32 lcpll = read32(info, LCPLL_CTL); if ((lcpll & LCPLL_CD_SOURCE_FCLK) != 0) info.shared_info->hw_cdclk = 800000;