diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h
index c20c0e1763..ca9904bbd5 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -1,9 +1,10 @@
 /*
- * Copyright 2006-2014, Haiku, Inc. All Rights Reserved.
+ * Copyright 2006-2015, Haiku, Inc. All Rights Reserved.
  * Distributed under the terms of the MIT License.
  *
  * Authors:
  *		Axel Dörfler, axeld@pinc-software.de
+ *		Alexander von Gluck, kallisti5@unixzen.com
  */
 #ifndef INTEL_EXTREME_H
 #define INTEL_EXTREME_H
@@ -20,51 +21,60 @@
 
 #define VENDOR_ID_INTEL			0x8086
 
-#define INTEL_TYPE_FAMILY_MASK	0x00f00000
-#define INTEL_TYPE_GROUP_MASK	0x00fffff0
-#define INTEL_TYPE_MODEL_MASK	0x00ffffff
+#define INTEL_FAMILY_MASK	0x00ff0000
+#define INTEL_GROUP_MASK	0x00fffff0
+#define INTEL_MODEL_MASK	0x00ffffff
 // families
-#define INTEL_TYPE_7xx			0x00100000	// First Gen
-#define INTEL_TYPE_8xx			0x00200000	// Second Gen
-#define INTEL_TYPE_9xx			0x00400000	// Third Gen +
+#define INTEL_FAMILY_7xx	0x00010000	// First Gen
+#define INTEL_FAMILY_8xx	0x00020000	// Second Gen
+#define INTEL_FAMILY_9xx	0x00040000	// Third Gen +
+#define INTEL_FAMILY_SER5	0x00080000	// Intel5 Series
+#define INTEL_FAMILY_POVR	0x00100000	// PowerVR (uugh)
+#define INTEL_FAMILY_SOC0	0x00200000  // Atom SOC
 // groups
-#define INTEL_TYPE_83x			(INTEL_TYPE_8xx | 0x00010)
-#define INTEL_TYPE_85x			(INTEL_TYPE_8xx | 0x00020)
-#define INTEL_TYPE_91x			(INTEL_TYPE_9xx | 0x00040)
-#define INTEL_TYPE_94x			(INTEL_TYPE_9xx | 0x00080)
-#define INTEL_TYPE_96x			(INTEL_TYPE_9xx | 0x00100)
-#define INTEL_TYPE_Gxx			(INTEL_TYPE_9xx | 0x00200)
-#define INTEL_TYPE_G4x			(INTEL_TYPE_9xx | 0x00400)
-#define INTEL_TYPE_IGD			(INTEL_TYPE_9xx | 0x00800)
-#define INTEL_TYPE_ILK			(INTEL_TYPE_9xx | 0x01000)
-#define INTEL_TYPE_SNB			(INTEL_TYPE_9xx | 0x02000)
-#define INTEL_TYPE_IVB			(INTEL_TYPE_9xx | 0x04000)
-#define INTEL_TYPE_HAS			(INTEL_TYPE_9xx | 0x08000)
-#define INTEL_TYPE_VLV			(INTEL_TYPE_9xx | 0x10000)
+#define INTEL_GROUP_83x		(INTEL_FAMILY_8xx  | 0x0010)
+#define INTEL_GROUP_85x		(INTEL_FAMILY_8xx  | 0x0020)
+#define INTEL_GROUP_91x		(INTEL_FAMILY_9xx  | 0x0010)
+#define INTEL_GROUP_94x		(INTEL_FAMILY_9xx  | 0x0020)
+#define INTEL_GROUP_96x		(INTEL_FAMILY_9xx  | 0x0040)
+#define INTEL_GROUP_Gxx		(INTEL_FAMILY_9xx  | 0x0080)
+#define INTEL_GROUP_G4x		(INTEL_FAMILY_9xx  | 0x0100)
+#define INTEL_GROUP_IGD		(INTEL_FAMILY_9xx  | 0x0200)
+#define INTEL_GROUP_ILK		(INTEL_FAMILY_9xx  | 0x0400)  // IronLake
+#define INTEL_GROUP_SNB		(INTEL_FAMILY_SER5 | 0x0010)  // SandyBridge
+#define INTEL_GROUP_IVB		(INTEL_FAMILY_SER5 | 0x0020)  // IvyBridge
+#define INTEL_GROUP_HAS		(INTEL_FAMILY_SER5 | 0x0040)  // Haswell
+#define INTEL_GROUP_SLT		(INTEL_FAMILY_POVR | 0x0010)  // Saltwell
+#define INTEL_GROUP_FSM		(INTEL_FAMILY_POVR | 0x0020)  // Fu.Silvermont
+#define INTEL_GROUP_SLV		(INTEL_FAMILY_SOC0 | 0x0010)  // Silvermont
+#define INTEL_GROUP_AIR		(INTEL_FAMILY_SOC0 | 0x0020)  // Airmont
+#define INTEL_GROUP_GOL		(INTEL_FAMILY_SOC0 | 0x0040)  // Goldmont
 // models
-#define INTEL_TYPE_SERVER		0x0004
-#define INTEL_TYPE_MOBILE		0x0008
-#define INTEL_TYPE_915			(INTEL_TYPE_91x)
-#define INTEL_TYPE_915M			(INTEL_TYPE_91x | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_945			(INTEL_TYPE_94x)
-#define INTEL_TYPE_945M			(INTEL_TYPE_94x | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_965			(INTEL_TYPE_96x)
-#define INTEL_TYPE_965M			(INTEL_TYPE_96x | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_G33			(INTEL_TYPE_Gxx)
-#define INTEL_TYPE_G45			(INTEL_TYPE_G4x)
-#define INTEL_TYPE_GM45			(INTEL_TYPE_G4x | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_IGDG			(INTEL_TYPE_IGD)
-#define INTEL_TYPE_IGDGM		(INTEL_TYPE_IGD | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_ILKG			(INTEL_TYPE_ILK)
-#define INTEL_TYPE_ILKGM		(INTEL_TYPE_ILK | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_SNBG			(INTEL_TYPE_SNB)
-#define INTEL_TYPE_SNBGM		(INTEL_TYPE_SNB | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_SNBGS		(INTEL_TYPE_SNB | INTEL_TYPE_SERVER)
-#define INTEL_TYPE_IVBG			(INTEL_TYPE_IVB)
-#define INTEL_TYPE_IVBGM		(INTEL_TYPE_IVB | INTEL_TYPE_MOBILE)
-#define INTEL_TYPE_IVBGS		(INTEL_TYPE_IVB | INTEL_TYPE_SERVER)
-#define INTEL_TYPE_VLVG			(INTEL_TYPE_VLV)
-#define INTEL_TYPE_VLVGM		(INTEL_TYPE_VLV | INTEL_TYPE_MOBILE)
+#define INTEL_TYPE_SERVER	0x0004
+#define INTEL_TYPE_MOBILE	0x0008
+#define INTEL_MODEL_915		(INTEL_GROUP_91x)
+#define INTEL_MODEL_915M	(INTEL_GROUP_91x | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_945		(INTEL_GROUP_94x)
+#define INTEL_MODEL_945M	(INTEL_GROUP_94x | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_965		(INTEL_GROUP_96x)
+#define INTEL_MODEL_965M	(INTEL_GROUP_96x | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_G33		(INTEL_GROUP_Gxx)
+#define INTEL_MODEL_G45		(INTEL_GROUP_G4x)
+#define INTEL_MODEL_GM45	(INTEL_GROUP_G4x | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_IGDG	(INTEL_GROUP_IGD)
+#define INTEL_MODEL_IGDGM	(INTEL_GROUP_IGD | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_ILKG	(INTEL_GROUP_ILK)
+#define INTEL_MODEL_ILKGM	(INTEL_GROUP_ILK | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_SNBG	(INTEL_GROUP_SNB)
+#define INTEL_MODEL_SNBGM	(INTEL_GROUP_SNB | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_SNBGS	(INTEL_GROUP_SNB | INTEL_TYPE_SERVER)
+#define INTEL_MODEL_IVBG	(INTEL_GROUP_IVB)
+#define INTEL_MODEL_IVBGM	(INTEL_GROUP_IVB | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_IVBGS	(INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
+#define INTEL_MODEL_HAS		(INTEL_GROUP_HAS)
+#define INTEL_MODEL_HASM	(INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_VLV		(INTEL_GROUP_SLV)
+#define INTEL_MODEL_VLVM	(INTEL_GROUP_SLV | INTEL_TYPE_MOBILE)
 
 // ValleyView MMIO offset
 #define VLV_DISPLAY_BASE		0x180000
@@ -122,35 +132,34 @@ struct DeviceType {
 
 	bool InFamily(uint32 family) const
 	{
-		return (type & INTEL_TYPE_FAMILY_MASK) == family;
+		return (type & INTEL_FAMILY_MASK) == family;
 	}
 
 	bool InGroup(uint32 group) const
 	{
-		return (type & INTEL_TYPE_GROUP_MASK) == group;
+		return (type & INTEL_GROUP_MASK) == group;
 	}
 
 	bool IsModel(uint32 model) const
 	{
-		return (type & INTEL_TYPE_MODEL_MASK) == model;
+		return (type & INTEL_MODEL_MASK) == model;
 	}
 
 	bool IsMobile() const
 	{
-		return (type & INTEL_TYPE_MODEL_MASK) == INTEL_TYPE_MOBILE;
+		return (type & INTEL_MODEL_MASK) == INTEL_TYPE_MOBILE;
 	}
 
 	bool SupportsHDMI() const
 	{
-		return InGroup(INTEL_TYPE_G4x) || InGroup(INTEL_TYPE_ILK)
-			|| InGroup(INTEL_TYPE_SNB) || InGroup(INTEL_TYPE_IVBG)
-			|| InGroup(INTEL_TYPE_HAS) || InGroup(INTEL_TYPE_VLV);
+		return InGroup(INTEL_GROUP_G4x) || InGroup(INTEL_GROUP_ILK)
+			|| InFamily(INTEL_FAMILY_SER5) || InFamily(INTEL_FAMILY_SOC0);
 	}
 
 	bool HasPlatformControlHub() const
 	{
-		return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB)
-			|| InGroup(INTEL_TYPE_IVB) || InGroup(INTEL_TYPE_HAS);
+		return InGroup(INTEL_GROUP_ILK) || InGroup(INTEL_GROUP_SNB)
+			|| InGroup(INTEL_GROUP_IVB) || InGroup(INTEL_GROUP_HAS);
 	}
 };
 
@@ -842,7 +851,7 @@ struct overlay_registers {
 inline bool
 intel_uses_physical_overlay(intel_shared_info &info)
 {
-	return !info.device_type.InGroup(INTEL_TYPE_Gxx);
+	return !info.device_type.InGroup(INTEL_GROUP_Gxx);
 }
 
 
diff --git a/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp b/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
index 8b237b8a24..63226436c2 100644
--- a/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
+++ b/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp
@@ -61,7 +61,7 @@ DisplayPipe::Disable()
 void
 DisplayPipe::ConfigureTimings(const pll_divisors& divisors)
 {
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 			write32(INTEL_DISPLAY_A_PLL_DIVISOR_0,
 				(((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
 					& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
@@ -78,8 +78,8 @@ DisplayPipe::ConfigureTimings(const pll_divisors& divisors)
 		}
 
 		uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL;
-		if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
-			if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+		if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)) {
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 				pll |= ((1 << (divisors.post1 - 1))
 						<< DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT)
 					& DISPLAY_PLL_IGD_POST1_DIVISOR_MASK;
@@ -95,7 +95,7 @@ DisplayPipe::ConfigureTimings(const pll_divisors& divisors)
 
 			pll |= DISPLAY_PLL_MODE_ANALOG;
 
-			if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x))
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x))
 				pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT;
 		} else {
 			if (!divisors.post2_high)
diff --git a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
index d8e56a802e..2e526498ec 100644
--- a/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
+++ b/src/add-ons/accelerants/intel_extreme/FlexibleDisplayInterface.cpp
@@ -62,7 +62,7 @@ FDITransmitter::EnablePLL()
 void
 FDITransmitter::DisablePLL()
 {
-	if (gInfo->shared_info->device_type.IsGroup(INTEL_TYPE_ILK)) {
+	if (gInfo->shared_info->device_type.IsGroup(INTEL_GROUP_ILK)) {
 		// on IronLake the FDI PLL is alaways enabled, so no point in trying...
 		return;
 	}
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp
index 53913ee582..4bfd7a54fb 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -139,7 +139,7 @@ Port::_SetI2CSignals(void* cookie, int clock, int data)
 	addr_t ioRegister = (addr_t)cookie;
 	uint32 value;
 
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_83x)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_83x)) {
 		// on these chips, the reserved values are fixed
 		value = 0;
 	} else {
@@ -203,7 +203,7 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 	pll_divisors divisors;
 	compute_pll_divisors(target, &divisors, false);
 
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 		write32(INTEL_DISPLAY_A_PLL_DIVISOR_0,
 			(((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
 				& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
@@ -220,8 +220,10 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 	}
 
 	uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL;
-	if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
-		if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+	if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)
+		|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
+		|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
+		if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 			pll |= ((1 << (divisors.post1 - 1))
 					<< DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT)
 				& DISPLAY_PLL_IGD_POST1_DIVISOR_MASK;
@@ -237,7 +239,7 @@ AnalogPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 
 		pll |= DISPLAY_PLL_MODE_ANALOG;
 
-		if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x))
+		if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x))
 			pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT;
 	} else {
 		if (!divisors.post2_high)
@@ -400,13 +402,15 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 		compute_pll_divisors(target, &divisors, true);
 
 	uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL | DISPLAY_PLL_ENABLED;
-	if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
+	if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)
+		|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
+		|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
 		dpll |= LVDS_PLL_MODE_LVDS;
 			// DPLL mode LVDS for i915+
 	}
 
 	// Compute bitmask from p1 value
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 		dpll |= (1 << (divisors.post1 - 1))
 			<< DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT;
 	} else {
@@ -426,7 +430,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 		// (I don't know how to detect that)
 
 	if ((dpll & DISPLAY_PLL_ENABLED) != 0) {
-		if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+		if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 			write32(INTEL_DISPLAY_B_PLL_DIVISOR_0,
 				(((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
 					& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
@@ -466,7 +470,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 	write32(INTEL_DIGITAL_LVDS_PORT, lvds);
 	read32(INTEL_DIGITAL_LVDS_PORT);
 
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 		write32(INTEL_DISPLAY_B_PLL_DIVISOR_0,
 			(((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
 				& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
@@ -488,7 +492,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
 	// Wait for the clocks to stabilize
 	spin(150);
 
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) {
 		float adjusted = ((referenceClock * divisors.m) / divisors.n)
 			/ divisors.post;
 		uint32 pixelMultiply;
@@ -682,7 +686,7 @@ HDMIPort::_PortRegister()
 {
 	// on PCH there's an additional port sandwiched in
 	bool hasPCH = gInfo->shared_info->device_type.HasPlatformControlHub();
-	bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV);
+	bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_SLV);
 
 	switch (PortIndex()) {
 		case INTEL_PORT_B:
@@ -694,7 +698,8 @@ HDMIPort::_PortRegister()
 				return GEN4_HDMI_PORT_C;
 			return hasPCH ? PCH_HDMI_PORT_C : INTEL_HDMI_PORT_C;
 		case INTEL_PORT_D:
-			// TODO: Is CherryView? GEN4_HDMI_PORT_D
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_AIR))
+				return CHV_HDMI_PORT_D;
 			return hasPCH ? PCH_HDMI_PORT_D : 0;
 		default:
 			return 0;
diff --git a/src/add-ons/accelerants/intel_extreme/accelerant.cpp b/src/add-ons/accelerants/intel_extreme/accelerant.cpp
index 3c2897eea5..f55f818129 100644
--- a/src/add-ons/accelerants/intel_extreme/accelerant.cpp
+++ b/src/add-ons/accelerants/intel_extreme/accelerant.cpp
@@ -149,7 +149,7 @@ init_common(int device, bool isClone)
 			+ gInfo->shared_info->overlay_offset);
 	}
 
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) {
 		// allocate some extra memory for the 3D context
 		if (intel_allocate_memory(INTEL_i965_3D_CONTEXT_SIZE,
 				B_APERTURE_NON_RESERVED, gInfo->context_base) == B_OK) {
@@ -234,6 +234,12 @@ probe_ports()
 	//   otherwise the assumed presence is confirmed by reading EDID in
 	//   IsConnected().
 
+	TRACE("adpa: %08" B_PRIx32 "\n", read32(INTEL_ANALOG_PORT));
+	TRACE("dova: %08" B_PRIx32 ", dovb: %08" B_PRIx32
+		", dovc: %08" B_PRIx32 "\n", read32(INTEL_DIGITAL_PORT_A),
+		read32(INTEL_DIGITAL_PORT_B), read32(INTEL_DIGITAL_PORT_C));
+	TRACE("lvds: %08" B_PRIx32 "\n", read32(INTEL_DIGITAL_LVDS_PORT));
+
 	gInfo->port_count = 0;
 	for (int i = INTEL_PORT_B; i <= INTEL_PORT_D; i++) {
 		Port* displayPort = new(std::nothrow) DisplayPort((port_index)i);
@@ -442,7 +448,7 @@ intel_get_accelerant_device_info(accelerant_device_info* info)
 	CALLED();
 
 	info->version = B_ACCELERANT_VERSION;
-	strcpy(info->name, gInfo->shared_info->device_type.InFamily(INTEL_TYPE_7xx)
+	strcpy(info->name, gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_7xx)
 		? "Intel Extreme Graphics 1" : "Intel Extreme Graphics 2");
 	strcpy(info->chipset, gInfo->shared_info->device_identifier);
 	strcpy(info->serial_no, "None");
diff --git a/src/add-ons/accelerants/intel_extreme/hooks.cpp b/src/add-ons/accelerants/intel_extreme/hooks.cpp
index 975551b644..72a48a4b84 100644
--- a/src/add-ons/accelerants/intel_extreme/hooks.cpp
+++ b/src/add-ons/accelerants/intel_extreme/hooks.cpp
@@ -111,15 +111,15 @@ get_accelerant_hook(uint32 feature, void* data)
 			return (void*)intel_overlay_supported_features;
 		case B_ALLOCATE_OVERLAY_BUFFER:
 			// TODO: overlay doesn't seem to work on these chips
-			if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_91x)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_94x)
-				|| gInfo->shared_info->device_type.IsModel(INTEL_TYPE_965M)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_G4x)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
-				|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV))
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_91x)
+				|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_94x)
+				|| gInfo->shared_info->device_type.IsModel(INTEL_MODEL_965M)
+				|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_G4x)
+				|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)
+				|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_ILK)
+				|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
+				|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_POVR)
+				|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0))
 				return NULL;
 
 			return (void*)intel_allocate_overlay_buffer;
diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp
index 536ebf1e07..736e8ab05a 100644
--- a/src/add-ons/accelerants/intel_extreme/mode.cpp
+++ b/src/add-ons/accelerants/intel_extreme/mode.cpp
@@ -82,7 +82,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
 	}
 
 	pll_divisors divisors;
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 		divisors.m1 = 0;
 		divisors.m2 = (pllDivisor & DISPLAY_PLL_IGD_M2_DIVISOR_MASK)
 			>> DISPLAY_PLL_M2_DIVISOR_SHIFT;
@@ -100,8 +100,10 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
 	pll_limits limits;
 	get_pll_limits(&limits);
 
-	if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
-		if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+	if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)
+		|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
+		|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
+		if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 			divisors.post1 = (pll & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK)
 				>> DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT;
 		} else {
@@ -110,7 +112,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
 		}
 
 		if (pllRegister == INTEL_DISPLAY_B_PLL
-			&& !gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) {
+			&& !gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) {
 			// TODO: Fix this? Need to support dual channel LVDS.
 			divisors.post2 = LVDS_POST2_RATE_SLOW;
 		} else {
@@ -242,12 +244,12 @@ sanitize_display_mode(display_mode& mode)
 	// Some cards only support even pixel counts, while others require an odd
 	// one.
 	uint16 pixelCount = 1;
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_Gxx)
-			|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)
-			|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_94x)
-			|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_91x)
-			|| gInfo->shared_info->device_type.InFamily(INTEL_TYPE_8xx)
-			|| gInfo->shared_info->device_type.InFamily(INTEL_TYPE_7xx)) {
+	if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_Gxx)
+			|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)
+			|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_94x)
+			|| gInfo->shared_info->device_type.InGroup(INTEL_GROUP_91x)
+			|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_8xx)
+			|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_7xx)) {
 		pixelCount = 2;
 	}
 
@@ -288,12 +290,11 @@ set_frame_buffer_base()
 		surfaceRegister = INTEL_DISPLAY_B_SURFACE;
 	}
 
-	if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x)
-		|| sharedInfo.device_type.InGroup(INTEL_TYPE_G4x)
-		|| sharedInfo.device_type.InGroup(INTEL_TYPE_ILK)
-		|| sharedInfo.device_type.InGroup(INTEL_TYPE_SNB)
-		|| sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)
-		|| sharedInfo.device_type.InGroup(INTEL_TYPE_VLV)) {
+	if (sharedInfo.device_type.InGroup(INTEL_GROUP_96x)
+		|| sharedInfo.device_type.InGroup(INTEL_GROUP_G4x)
+		|| sharedInfo.device_type.InGroup(INTEL_GROUP_ILK)
+		|| sharedInfo.device_type.InFamily(INTEL_FAMILY_SER5)
+		|| sharedInfo.device_type.InFamily(INTEL_FAMILY_SOC0)) {
 		write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
 			+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
 		read32(baseRegister);
@@ -625,7 +626,7 @@ if (first) {
 		pll_divisors divisors;
 		compute_pll_divisors(&target, &divisors, false);
 
-		if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+		if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 			write32(INTEL_DISPLAY_B_PLL_DIVISOR_0,
 				(((1 << divisors.n) << DISPLAY_PLL_N_DIVISOR_SHIFT)
 					& DISPLAY_PLL_IGD_N_DIVISOR_MASK)
@@ -642,8 +643,10 @@ if (first) {
 		}
 
 		uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL;
-		if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
-			if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
+		if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)
+			|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
+			|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
 				pll |= ((1 << (divisors.post1 - 1))
 						<< DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT)
 					& DISPLAY_PLL_IGD_POST1_DIVISOR_MASK;
@@ -657,7 +660,7 @@ if (first) {
 			if (divisors.post2_high)
 				pll |= DISPLAY_PLL_DIVIDE_HIGH;
 
-			if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x))
+			if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x))
 				pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT;
 		} else {
 			if (!divisors.post2_high)
diff --git a/src/add-ons/accelerants/intel_extreme/overlay.cpp b/src/add-ons/accelerants/intel_extreme/overlay.cpp
index 84c1677289..5716577e0c 100644
--- a/src/add-ons/accelerants/intel_extreme/overlay.cpp
+++ b/src/add-ons/accelerants/intel_extreme/overlay.cpp
@@ -235,7 +235,7 @@ static void
 update_overlay(bool updateCoefficients)
 {
 	if (!gInfo->shared_info->overlay_active
-		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
+		|| gInfo->shared_info->device_type.IsModel(INTEL_MODEL_965))
 		return;
 
 	QueueCommands queue(gInfo->shared_info->primary_ring_buffer);
@@ -259,7 +259,7 @@ static void
 show_overlay(void)
 {
 	if (gInfo->shared_info->overlay_active
-		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
+		|| gInfo->shared_info->device_type.IsModel(INTEL_MODEL_965))
 		return;
 
 	gInfo->shared_info->overlay_active = true;
@@ -281,7 +281,7 @@ static void
 hide_overlay(void)
 {
 	if (!gInfo->shared_info->overlay_active
-		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
+		|| gInfo->shared_info->device_type.IsModel(INTEL_MODEL_965))
 		return;
 
 	overlay_registers* registers = gInfo->overlay_registers;
@@ -327,7 +327,7 @@ intel_overlay_supported_spaces(const display_mode* mode)
 	static const uint32 kSupportedi965Spaces[] = {B_YCbCr422, 0};
 	intel_shared_info &sharedInfo = *gInfo->shared_info;
 
-	if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x))
+	if (sharedInfo.device_type.InGroup(INTEL_GROUP_96x))
 		return kSupportedi965Spaces;
 
 	return kSupportedSpaces;
@@ -380,7 +380,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
 	// alloc graphics mem
 
 	int32 alignment = 0x3f;
-	if (sharedInfo.device_type.InGroup(INTEL_TYPE_965))
+	if (sharedInfo.device_type.IsModel(INTEL_MODEL_965))
 		alignment = 0xff;
 
 	overlay_buffer* buffer = &overlay->buffer;
@@ -396,7 +396,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
 		return NULL;
 	}
 
-	if (sharedInfo.device_type.InGroup(INTEL_TYPE_965)) {
+	if (sharedInfo.device_type.IsModel(INTEL_MODEL_965)) {
 		status = intel_allocate_memory(INTEL_i965_OVERLAY_STATE_SIZE,
 			B_APERTURE_NON_RESERVED, overlay->state_base);
 		if (status < B_OK) {
@@ -437,7 +437,7 @@ intel_release_overlay_buffer(const overlay_buffer* buffer)
 		hide_overlay();
 
 	intel_free_memory(overlay->buffer_base);
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
+	if (gInfo->shared_info->device_type.IsModel(INTEL_MODEL_965))
 		intel_free_memory(overlay->state_base);
 	free(overlay);
 
@@ -630,7 +630,7 @@ intel_configure_overlay(overlay_token overlayToken,
 		// the result will be wrong, too.
 		registers->source_width_rgb = right - left;
 		registers->source_height_rgb = bottom - top;
-		if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_8xx)) {
+		if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_8xx)) {
 			registers->source_bytes_per_row_rgb = (((overlay->buffer_offset
 				+ (view->width << 1) + 0x1f) >> 5)
 				- (overlay->buffer_offset >> 5) - 1) << 2;
diff --git a/src/add-ons/accelerants/intel_extreme/pll.cpp b/src/add-ons/accelerants/intel_extreme/pll.cpp
index e70129a8c7..9777a89b95 100644
--- a/src/add-ons/accelerants/intel_extreme/pll.cpp
+++ b/src/add-ons/accelerants/intel_extreme/pll.cpp
@@ -44,10 +44,8 @@ get_pll_limits(pll_limits* limits)
 	// Note, the limits are taken from the X driver; they have not yet been
 	// tested
 
-	if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
-		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
-		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
-		|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV)) {
+	if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
+		|| gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
 		// TODO: support LVDS output limits as well
 		pll_limits kLimits = {
 			// p, p1, p2, high,   n,   m, m1, m2
@@ -56,26 +54,7 @@ get_pll_limits(pll_limits* limits)
 			225000, 1760000, 3510000
 		};
 		memcpy(limits, &kLimits, sizeof(pll_limits));
-	} else if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_G4x)) {
-		// TODO: support LVDS output limits as well
-		pll_limits kLimits = {
-			// p, p1, p2, high,   n,   m, m1, m2
-			{ 10,  1, 10, false,  1, 104, 17,  5},	// min
-			{ 30,  3, 10, true,   4, 138, 23, 11},	// max
-			270000, 1750000, 3500000
-		};
-		memcpy(limits, &kLimits, sizeof(pll_limits));
-	} else if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)) {
-		// TODO: support LVDS output limits as well
-		// m1 is reserved and must be 0
-		pll_limits kLimits = {
-			// p, p1, p2, high,   n,   m, m1,  m2
-			{  5,  1, 10, false,  3,   2,  0,   2},	// min
-			{ 80,  8,  5, true,   6, 256,  0, 256},	// max
-			200000, 1700000, 3500000
-		};
-		memcpy(limits, &kLimits, sizeof(pll_limits));
-	} else if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
+	} else if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)) {
 		// TODO: support LVDS output limits as well
 		// (Update: Output limits are adjusted in the computation (post2=7/14))
 		// Should move them here!
@@ -86,6 +65,25 @@ get_pll_limits(pll_limits* limits)
 			200000, 1400000, 2800000
 		};
 		memcpy(limits, &kLimits, sizeof(pll_limits));
+	} else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_G4x)) {
+		// TODO: support LVDS output limits as well
+		pll_limits kLimits = {
+			// p, p1, p2, high,   n,   m, m1, m2
+			{ 10,  1, 10, false,  1, 104, 17,  5},	// min
+			{ 30,  3, 10, true,   4, 138, 23, 11},	// max
+			270000, 1750000, 3500000
+		};
+		memcpy(limits, &kLimits, sizeof(pll_limits));
+	} else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD)) {
+		// TODO: support LVDS output limits as well
+		// m1 is reserved and must be 0
+		pll_limits kLimits = {
+			// p, p1, p2, high,   n,   m, m1,  m2
+			{  5,  1, 10, false,  3,   2,  0,   2},	// min
+			{ 80,  8,  5, true,   6, 256,  0, 256},	// max
+			200000, 1700000, 3500000
+		};
+		memcpy(limits, &kLimits, sizeof(pll_limits));
 	} else {
 		// TODO: support LVDS output limits as well
 		static pll_limits kLimits = {
@@ -160,7 +158,7 @@ compute_pll_divisors(display_mode* current, pll_divisors* divisors,
 	float best = requestedPixelClock;
 	pll_divisors bestDivisors;
 
-	bool is_igd = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD);
+	bool is_igd = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_IGD);
 	for (divisors->m1 = limits.min.m1; divisors->m1 <= limits.max.m1;
 			divisors->m1++) {
 		for (divisors->m2 = limits.min.m2; divisors->m2 <= limits.max.m2
diff --git a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
index a2611151c4..12c9ac5cd9 100644
--- a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
+++ b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
@@ -54,74 +54,74 @@ const struct supported_device {
 	uint32		type;
 	const char	*name;
 } kSupportedDevices[] = {
-	{0x3575, 0x3577, INTEL_TYPE_83x, "i830GM"},
-	{0x2560, 0x2562, INTEL_TYPE_83x, "i845G"},
-	{0x3580, 0x3582, INTEL_TYPE_85x, "i855G"},
-	{0x358c, 0x358e, INTEL_TYPE_85x, "i855G"},
-	{0x2570, 0x2572, INTEL_TYPE_85x, "i865G"},
+	{0x3575, 0x3577, INTEL_GROUP_83x, "i830GM"},
+	{0x2560, 0x2562, INTEL_GROUP_83x, "i845G"},
+	{0x3580, 0x3582, INTEL_GROUP_85x, "i855G"},
+	{0x358c, 0x358e, INTEL_GROUP_85x, "i855G"},
+	{0x2570, 0x2572, INTEL_GROUP_85x, "i865G"},
 
-//	{0x2792, INTEL_TYPE_91x, "i910"},
-//	{0x258a, INTEL_TYPE_91x, "i915"},
-	{0x2580, 0x2582, INTEL_TYPE_915, "i915G"},
-	{0x2590, 0x2592, INTEL_TYPE_915M, "i915GM"},
-	{0x2770, 0x2772, INTEL_TYPE_945, "i945G"},
-	{0x27a0, 0x27a2, INTEL_TYPE_945M, "i945GM"},
-	{0x27ac, 0x27ae, INTEL_TYPE_945M, "i945GME"},
+//	{0x2792, INTEL_GROUP_91x, "i910"},
+//	{0x258a, INTEL_GROUP_91x, "i915"},
+	{0x2580, 0x2582, INTEL_MODEL_915, "i915G"},
+	{0x2590, 0x2592, INTEL_MODEL_915M, "i915GM"},
+	{0x2770, 0x2772, INTEL_MODEL_945, "i945G"},
+	{0x27a0, 0x27a2, INTEL_MODEL_945M, "i945GM"},
+	{0x27ac, 0x27ae, INTEL_MODEL_945M, "i945GME"},
 
-	{0x2970, 0x2972, INTEL_TYPE_965, "i946GZ"},
-	{0x2980, 0x2982, INTEL_TYPE_965, "G35"},
-	{0x2990, 0x2992, INTEL_TYPE_965, "i965Q"},
-	{0x29a0, 0x29a2, INTEL_TYPE_965, "i965G"},
-	{0x2a00, 0x2a02, INTEL_TYPE_965, "i965GM"},
-	{0x2a10, 0x2a12, INTEL_TYPE_965, "i965GME"},
+	{0x2970, 0x2972, INTEL_MODEL_965, "i946GZ"},
+	{0x2980, 0x2982, INTEL_MODEL_965, "G35"},
+	{0x2990, 0x2992, INTEL_MODEL_965, "i965Q"},
+	{0x29a0, 0x29a2, INTEL_MODEL_965, "i965G"},
+	{0x2a00, 0x2a02, INTEL_MODEL_965, "i965GM"},
+	{0x2a10, 0x2a12, INTEL_MODEL_965, "i965GME"},
 
-	{0x29b0, 0x29b2, INTEL_TYPE_G33, "G33"},
-	{0x29c0, 0x29c2, INTEL_TYPE_G33, "Q35"},
-	{0x29d0, 0x29d2, INTEL_TYPE_G33, "Q33"},
+	{0x29b0, 0x29b2, INTEL_MODEL_G33, "G33"},
+	{0x29c0, 0x29c2, INTEL_MODEL_G33, "Q35"},
+	{0x29d0, 0x29d2, INTEL_MODEL_G33, "Q33"},
 
-	{0x2a40, 0x2a42, INTEL_TYPE_GM45, "GM45"},
-	{0x2e00, 0x2e02, INTEL_TYPE_G45, "IGD"},
-	{0x2e10, 0x2e12, INTEL_TYPE_G45, "Q45"},
-	{0x2e20, 0x2e22, INTEL_TYPE_G45, "G45"},
-	{0x2e30, 0x2e32, INTEL_TYPE_G45, "G41"},
-	{0x2e40, 0x2e42, INTEL_TYPE_G45, "B43"},
-	{0x2e90, 0x2e92, INTEL_TYPE_G45, "B43"},
+	{0x2a40, 0x2a42, INTEL_MODEL_GM45, "GM45"},
+	{0x2e00, 0x2e02, INTEL_MODEL_G45, "IGD"},
+	{0x2e10, 0x2e12, INTEL_MODEL_G45, "Q45"},
+	{0x2e20, 0x2e22, INTEL_MODEL_G45, "G45"},
+	{0x2e30, 0x2e32, INTEL_MODEL_G45, "G41"},
+	{0x2e40, 0x2e42, INTEL_MODEL_G45, "B43"},
+	{0x2e90, 0x2e92, INTEL_MODEL_G45, "B43"},
 
-	{0xa000, 0xa001, INTEL_TYPE_IGDG, "Atom_Dx10"},
-	{0xa010, 0xa011, INTEL_TYPE_IGDGM, "Atom_N4x0"},
+	{0xa000, 0xa001, INTEL_MODEL_IGDG, "Atom_Dx10"},
+	{0xa010, 0xa011, INTEL_MODEL_IGDGM, "Atom_N4x0"},
 
-	{0x0040, 0x0042, INTEL_TYPE_ILKG, "IronLake Desktop"},
-	{0x0044, 0x0046, INTEL_TYPE_ILKGM, "IronLake Mobile"},
-	{0x0062, 0x0046, INTEL_TYPE_ILKGM, "IronLake Mobile"},
-	{0x006a, 0x0046, INTEL_TYPE_ILKGM, "IronLake Mobile"},
+	{0x0040, 0x0042, INTEL_MODEL_ILKG, "IronLake Desktop"},
+	{0x0044, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},
+	{0x0062, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},
+	{0x006a, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},
 
-	{0x0100, 0x0102, INTEL_TYPE_SNBG, "SandyBridge Desktop GT1"},
-	{0x0100, 0x0112, INTEL_TYPE_SNBG, "SandyBridge Desktop GT2"},
-	{0x0100, 0x0122, INTEL_TYPE_SNBG, "SandyBridge Desktop GT2+"},
-	{0x0104, 0x0106, INTEL_TYPE_SNBGM, "SandyBridge Mobile GT1"},
-	{0x0104, 0x0116, INTEL_TYPE_SNBGM, "SandyBridge Mobile GT2"},
-	{0x0104, 0x0126, INTEL_TYPE_SNBGM, "SandyBridge Mobile GT2+"},
-	{0x0108, 0x010a, INTEL_TYPE_SNBGS, "SandyBridge Server"},
+	{0x0100, 0x0102, INTEL_MODEL_SNBG, "SandyBridge Desktop GT1"},
+	{0x0100, 0x0112, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2"},
+	{0x0100, 0x0122, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2+"},
+	{0x0104, 0x0106, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT1"},
+	{0x0104, 0x0116, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2"},
+	{0x0104, 0x0126, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2+"},
+	{0x0108, 0x010a, INTEL_MODEL_SNBGS, "SandyBridge Server"},
 
-	{0x0150, 0x0152, INTEL_TYPE_IVBG, "IvyBridge Desktop GT1"},
-	{0x0150, 0x0162, INTEL_TYPE_IVBG, "IvyBridge Desktop GT2"},
-	{0x0154, 0x0156, INTEL_TYPE_IVBGM, "IvyBridge Mobile GT1"},
-	{0x0154, 0x0166, INTEL_TYPE_IVBGM, "IvyBridge Mobile GT2"},
-	{0x0158, 0x015a, INTEL_TYPE_IVBGS, "IvyBridge Server GT1"},
-	{0x0158, 0x016a, INTEL_TYPE_IVBGS, "IvyBridge Server GT2"},
+	{0x0150, 0x0152, INTEL_MODEL_IVBG, "IvyBridge Desktop GT1"},
+	{0x0150, 0x0162, INTEL_MODEL_IVBG, "IvyBridge Desktop GT2"},
+	{0x0154, 0x0156, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT1"},
+	{0x0154, 0x0166, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT2"},
+	{0x0158, 0x015a, INTEL_MODEL_IVBGS, "IvyBridge Server GT1"},
+	{0x0158, 0x016a, INTEL_MODEL_IVBGS, "IvyBridge Server GT2"},
 
-	{0x0c00, 0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
-	{0x0c04, 0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
-	{0x0d04, 0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
-	{0x0a04, 0x0a16, INTEL_TYPE_IVBGM, "Haswell Mobile"},
+	{0x0c00, 0x0412, INTEL_MODEL_HAS, "Haswell Desktop"},
+	{0x0c04, 0x0416, INTEL_MODEL_HASM, "Haswell Mobile"},
+	{0x0d04, 0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"},
+	{0x0a04, 0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"},
 
 	// XXX: 0x0f00 only confirmed on 0x0f30, 0x0f31
-	{0x0f00, 0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
-	{0x0f00, 0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0f00, 0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0f00, 0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0f00, 0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0f00, 0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0f00, 0x0155, INTEL_MODEL_VLV, "ValleyView Desktop"},
+	{0x0f00, 0x0f30, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0f00, 0x0f31, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0f00, 0x0f32, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0f00, 0x0f33, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0f00, 0x0157, INTEL_MODEL_VLVM, "ValleyView Mobile"},
 };
 
 struct intel_info {
@@ -174,7 +174,7 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 {
 	// read stolen memory from the PCI configuration of the PCI bridge
 	uint8 controlRegister = INTEL_GRAPHICS_MEMORY_CONTROL;
-	if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_SNB)
+	if ((info.type & INTEL_GROUP_MASK) == INTEL_GROUP_SNB)
 		controlRegister = SNB_GRAPHICS_MEMORY_CONTROL;
 
 	uint16 memoryConfig = get_pci_config(info.bridge, controlRegister, 2);
@@ -182,7 +182,7 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 	gttSize = 0;
 	stolenSize = 0;
 
-	if (info.type == INTEL_TYPE_965) {
+	if (info.type == INTEL_MODEL_965) {
 		switch (memoryConfig & i965_GTT_MASK) {
 			case i965_GTT_128K:
 				gttSize = 128 << 10;
@@ -194,8 +194,8 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 				gttSize = 512 << 10;
 				break;
 		}
-	} else if (info.type == INTEL_TYPE_G33
-	           || (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_IGD) {
+	} else if (info.type == INTEL_MODEL_G33
+	           || (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_IGD) {
 		switch (memoryConfig & G33_GTT_MASK) {
 			case G33_GTT_1M:
 				gttSize = 1 << 20;
@@ -204,8 +204,8 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 				gttSize = 2 << 20;
 				break;
 		}
-	} else if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x
-			|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_ILK) {
+	} else if ((info.type & INTEL_GROUP_MASK) == INTEL_GROUP_G4x
+			|| (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_ILK) {
 		switch (memoryConfig & G4X_GTT_MASK) {
 			case G4X_GTT_NONE:
 				gttSize = 0;
@@ -224,7 +224,7 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 				gttSize = 4 << 20;
 				break;
 		}
-	} else if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_SNB) {
+	} else if ((info.type & INTEL_GROUP_MASK) == INTEL_GROUP_SNB) {
 		switch (memoryConfig & SNB_GTT_SIZE_MASK) {
 			case SNB_GTT_SIZE_NONE:
 				gttSize = 0;
@@ -240,13 +240,13 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 		// older models have the GTT as large as their frame buffer mapping
 		// TODO: check if the i9xx version works with the i8xx chips as well
 		size_t frameBufferSize = 0;
-		if ((info.type & INTEL_TYPE_8xx) != 0) {
-			if (info.type == INTEL_TYPE_83x
+		if ((info.type & INTEL_FAMILY_8xx) != 0) {
+			if (info.type == INTEL_GROUP_83x
 				&& (memoryConfig & MEMORY_MASK) == i830_FRAME_BUFFER_64M)
 				frameBufferSize = 64 << 20;
 			else
 				frameBufferSize = 128 << 20;
-		} else if ((info.type & INTEL_TYPE_9xx) != 0)
+		} else if ((info.type & INTEL_FAMILY_9xx) != 0)
 			frameBufferSize = info.display.u.h0.base_register_sizes[2];
 
 		TRACE("frame buffer size %lu MB\n", frameBufferSize >> 20);
@@ -255,7 +255,7 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 
 	// TODO: test with different models!
 
-	if (info.type == INTEL_TYPE_83x) {
+	if (info.type == INTEL_GROUP_83x) {
 		// Older chips
 		switch (memoryConfig & STOLEN_MEMORY_MASK) {
 			case i830_LOCAL_MEMORY_ONLY:
@@ -273,7 +273,7 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 				memorySize *= 8;
 				break;
 		}
-	} else if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_SNB) {
+	} else if ((info.type & INTEL_GROUP_MASK) == INTEL_GROUP_SNB) {
 		switch (memoryConfig & SNB_STOLEN_MEMORY_MASK) {
 			case SNB_STOLEN_MEMORY_32MB:
 				memorySize *= 32;
@@ -324,8 +324,8 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 				memorySize *= 512;
 				break;
 		}
-	} else if (info.type == INTEL_TYPE_85x
-		|| (info.type & INTEL_TYPE_9xx) == INTEL_TYPE_9xx) {
+	} else if (info.type == INTEL_GROUP_85x
+		|| (info.type & INTEL_FAMILY_9xx) == INTEL_FAMILY_9xx) {
 		switch (memoryConfig & STOLEN_MEMORY_MASK) {
 			case i855_STOLEN_MEMORY_4M:
 				memorySize *= 4;
@@ -376,15 +376,14 @@ determine_memory_sizes(intel_info &info, size_t &gttSize, size_t &stolenSize)
 static void
 set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress)
 {
-	if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_96x
-		|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_Gxx
-		|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x
-		|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_IGD
-		|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_ILK
-		|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_VLV) {
+	if ((info.type & INTEL_GROUP_MASK) == INTEL_GROUP_96x
+		|| (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_Gxx
+		|| (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_G4x
+		|| (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_IGD
+		|| (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_ILK) {
 		// possible high bits are stored in the lower end
 		physicalAddress |= (physicalAddress >> 28) & 0x00f0;
-	} else if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_SNB) {
+	} else if ((info.type & INTEL_GROUP_MASK) == INTEL_GROUP_SNB) {
 		physicalAddress |= (physicalAddress >> 28) & 0x0ff0;
 		physicalAddress |= 0x02; // cache control, l3 cacheable
 	}
@@ -411,7 +410,7 @@ intel_map(intel_info &info)
 {
 	int fbIndex = 0;
 	int mmioIndex = 1;
-	if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
+	if ((info.type & INTEL_FAMILY_MASK) == INTEL_FAMILY_9xx) {
 		// for some reason Intel saw the need to change the order of the
 		// mappings with the introduction of the i9xx family
 		mmioIndex = 0;
@@ -448,10 +447,10 @@ intel_map(intel_info &info)
 	if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK)
 		return B_ERROR;
 
-	if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
-		if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x
-			|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_ILK
-			|| (info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_SNB) {
+	if ((info.type & INTEL_FAMILY_MASK) == INTEL_FAMILY_9xx) {
+		if ((info.type & INTEL_GROUP_MASK) == INTEL_GROUP_G4x
+			|| (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_ILK
+			|| (info.type & INTEL_GROUP_MASK) == INTEL_GROUP_SNB) {
 			info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
 					+ (2UL << 20);
 		} else
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
index 251f3ee2dc..858f39ad44 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
@@ -42,72 +42,72 @@ const struct supported_device {
 	int32		type;
 	const char*	name;
 } kSupportedDevices[] = {
-	{0x3577, INTEL_TYPE_83x, "i830GM"},
-	{0x2562, INTEL_TYPE_83x, "i845G"},
+	{0x3577, INTEL_GROUP_83x, "i830GM"},
+	{0x2562, INTEL_GROUP_83x, "i845G"},
 
-	{0x2572, INTEL_TYPE_85x, "i865G"},
-	{0x3582, INTEL_TYPE_85x, "i855G"},
-	{0x358e, INTEL_TYPE_85x, "i855G"},
+	{0x2572, INTEL_GROUP_85x, "i865G"},
+	{0x3582, INTEL_GROUP_85x, "i855G"},
+	{0x358e, INTEL_GROUP_85x, "i855G"},
 
-	{0x2582, INTEL_TYPE_915, "i915G"},
-	{0x258a, INTEL_TYPE_915, "i915"},
-	{0x2592, INTEL_TYPE_915M, "i915GM"},
-	{0x2792, INTEL_TYPE_915, "i910"},
-	{0x2772, INTEL_TYPE_945, "i945G"},
-	{0x27a2, INTEL_TYPE_945M, "i945GM"},
-	{0x27ae, INTEL_TYPE_945M, "i945GME"},
-	{0x2972, INTEL_TYPE_965, "i946G"},
-	{0x2982, INTEL_TYPE_965, "G35"},
-	{0x2992, INTEL_TYPE_965, "i965Q"},
-	{0x29a2, INTEL_TYPE_965, "i965G"},
-	{0x2a02, INTEL_TYPE_965M, "i965GM"},
-	{0x2a12, INTEL_TYPE_965M, "i965GME"},
-	{0x29b2, INTEL_TYPE_G33, "G33G"},
-	{0x29c2, INTEL_TYPE_G33, "Q35G"},
-	{0x29d2, INTEL_TYPE_G33, "Q33G"},
+	{0x2582, INTEL_MODEL_915, "i915G"},
+	{0x258a, INTEL_MODEL_915, "i915"},
+	{0x2592, INTEL_MODEL_915M, "i915GM"},
+	{0x2792, INTEL_MODEL_915, "i910"},
+	{0x2772, INTEL_MODEL_945, "i945G"},
+	{0x27a2, INTEL_MODEL_945M, "i945GM"},
+	{0x27ae, INTEL_MODEL_945M, "i945GME"},
+	{0x2972, INTEL_MODEL_965, "i946G"},
+	{0x2982, INTEL_MODEL_965, "G35"},
+	{0x2992, INTEL_MODEL_965, "i965Q"},
+	{0x29a2, INTEL_MODEL_965, "i965G"},
+	{0x2a02, INTEL_MODEL_965M, "i965GM"},
+	{0x2a12, INTEL_MODEL_965M, "i965GME"},
+	{0x29b2, INTEL_MODEL_G33, "G33G"},
+	{0x29c2, INTEL_MODEL_G33, "Q35G"},
+	{0x29d2, INTEL_MODEL_G33, "Q33G"},
 
-	{0x2a42, INTEL_TYPE_GM45, "GM45"},
-	{0x2e02, INTEL_TYPE_G45, "IGD"},
-	{0x2e12, INTEL_TYPE_G45, "Q45"},
-	{0x2e22, INTEL_TYPE_G45, "G45"},
-	{0x2e32, INTEL_TYPE_G45, "G41"},
-	{0x2e42, INTEL_TYPE_G45, "B43"},
-	{0x2e92, INTEL_TYPE_G45, "B43"},
+	{0x2a42, INTEL_MODEL_GM45, "GM45"},
+	{0x2e02, INTEL_MODEL_G45, "IGD"},
+	{0x2e12, INTEL_MODEL_G45, "Q45"},
+	{0x2e22, INTEL_MODEL_G45, "G45"},
+	{0x2e32, INTEL_MODEL_G45, "G41"},
+	{0x2e42, INTEL_MODEL_G45, "B43"},
+	{0x2e92, INTEL_MODEL_G45, "B43"},
 
-	{0xa001, INTEL_TYPE_IGDG, "Atom_Dx10"},
-	{0xa011, INTEL_TYPE_IGDGM, "Atom_N4x0"},
+	{0xa001, INTEL_MODEL_IGDG, "Atom_Dx10"},
+	{0xa011, INTEL_MODEL_IGDGM, "Atom_N4x0"},
 
-	{0x0042, INTEL_TYPE_ILKG, "IronLake Desktop"},
-	{0x0046, INTEL_TYPE_ILKGM, "IronLake Mobile"},
-	{0x0046, INTEL_TYPE_ILKGM, "IronLake Mobile"},
-	{0x0046, INTEL_TYPE_ILKGM, "IronLake Mobile"},
+	{0x0042, INTEL_MODEL_ILKG, "IronLake Desktop"},
+	{0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},
+	{0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},
+	{0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"},
 
-	{0x0102, INTEL_TYPE_SNBG, "SandyBridge Desktop GT1"},
-	{0x0112, INTEL_TYPE_SNBG, "SandyBridge Desktop GT2"},
-	{0x0122, INTEL_TYPE_SNBG, "SandyBridge Desktop GT2+"},
-	{0x0106, INTEL_TYPE_SNBGM, "SandyBridge Mobile GT1"},
-	{0x0116, INTEL_TYPE_SNBGM, "SandyBridge Mobile GT2"},
-	{0x0126, INTEL_TYPE_SNBGM, "SandyBridge Mobile GT2+"},
-	{0x010a, INTEL_TYPE_SNBGS, "SandyBridge Server"},
+	{0x0102, INTEL_MODEL_SNBG, "SandyBridge Desktop GT1"},
+	{0x0112, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2"},
+	{0x0122, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2+"},
+	{0x0106, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT1"},
+	{0x0116, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2"},
+	{0x0126, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2+"},
+	{0x010a, INTEL_MODEL_SNBGS, "SandyBridge Server"},
 
-	{0x0152, INTEL_TYPE_IVBG, "IvyBridge Desktop GT1"},
-	{0x0162, INTEL_TYPE_IVBG, "IvyBridge Desktop GT2"},
-	{0x0156, INTEL_TYPE_IVBGM, "IvyBridge Mobile GT1"},
-	{0x0166, INTEL_TYPE_IVBGM, "IvyBridge Mobile GT2"},
-	{0x015a, INTEL_TYPE_IVBGS, "IvyBridge Server GT1"},
-	{0x016a, INTEL_TYPE_IVBGS, "IvyBridge Server GT2"},
+	{0x0152, INTEL_MODEL_IVBG, "IvyBridge Desktop GT1"},
+	{0x0162, INTEL_MODEL_IVBG, "IvyBridge Desktop GT2"},
+	{0x0156, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT1"},
+	{0x0166, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT2"},
+	{0x015a, INTEL_MODEL_IVBGS, "IvyBridge Server GT1"},
+	{0x016a, INTEL_MODEL_IVBGS, "IvyBridge Server GT2"},
 
-	{0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
-	{0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
-	{0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
-	{0x0a16, INTEL_TYPE_IVBGM, "Haswell Mobile"},
+	{0x0412, INTEL_MODEL_HAS, "Haswell Desktop"},
+	{0x0416, INTEL_MODEL_HASM, "Haswell Mobile"},
+	{0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"},
+	{0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"},
 
-	{0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
-	{0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
-	{0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+	{0x0155, INTEL_MODEL_VLV, "ValleyView Desktop"},
+	{0x0f30, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0f31, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0f32, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0f33, INTEL_MODEL_VLVM, "ValleyView Mobile"},
+	{0x0157, INTEL_MODEL_VLVM, "ValleyView Mobile"},
 };
 
 int32 api_version = B_CUR_DRIVER_API_VERSION;
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
index f0a8f9422e..6b54d834ab 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
@@ -98,7 +98,7 @@ intel_interrupt_handler(void* data)
 
 		// Intel changed the PCH register mapping between Sandy Bridge and the
 		// later generations (Ivy Bridge and up).
-		if (info.device_type.InGroup(INTEL_TYPE_SNB)) {
+		if (info.device_type.InGroup(INTEL_GROUP_SNB)) {
 			mask = hasPCH ? PCH_INTERRUPT_VBLANK_PIPEA_SNB
 				: INTERRUPT_VBLANK_PIPEA;
 			if ((identity & mask) != 0) {
@@ -287,7 +287,8 @@ intel_extreme_init(intel_info &info)
 
 	int fbIndex = 0;
 	int mmioIndex = 1;
-	if (info.device_type.InFamily(INTEL_TYPE_9xx)) {
+	if (info.device_type.InFamily(INTEL_FAMILY_9xx)
+		| info.device_type.InFamily(INTEL_FAMILY_SER5)) {
 		// For some reason Intel saw the need to change the order of the
 		// mappings with the introduction of the i9xx family
 		mmioIndex = 0;
@@ -346,7 +347,7 @@ intel_extreme_init(intel_info &info)
 			= ICH_PORT_REGISTER_BASE;
 	}
 
-	if (info.device_type.InGroup(INTEL_TYPE_VLV)) {
+	if (info.device_type.InGroup(INTEL_GROUP_SLV)) {
 		// "I nearly got violent with the hw guys when they told me..."
 		blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] += VLV_DISPLAY_BASE;
 		blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE;
@@ -403,10 +404,11 @@ intel_extreme_init(intel_info &info)
 	info.shared_info->got_vbt = get_lvds_mode_from_bios(
 		&info.shared_info->current_mode);
 	/* at least 855gm can't drive more than one head at time */
-	if (info.device_type.InFamily(INTEL_TYPE_8xx))
+	if (info.device_type.InFamily(INTEL_FAMILY_8xx))
 		info.shared_info->single_head_locked = 1;
 
-	if (info.device_type.InFamily(INTEL_TYPE_9xx)) {
+	if (info.device_type.InFamily(INTEL_FAMILY_9xx)
+		| info.device_type.InFamily(INTEL_FAMILY_SER5)) {
 		info.shared_info->pll_info.reference_frequency = 96000;	// 96 kHz
 		info.shared_info->pll_info.max_frequency = 400000;
 			// 400 MHz RAM DAC speed
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
index 5864504b8f..f3756a4111 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
@@ -31,19 +31,19 @@ intel_en_gating(intel_info &info)
 	if (info.pci->device_id == 0x2a02 || info.pci->device_id == 0x2a12) {
 		TRACE("i965GM/i965GME quirk\n");
 		write32(info, 0x6204, (1L << 29));
-	} else if (info.device_type.InGroup(INTEL_TYPE_SNB)) {
+	} else if (info.device_type.InGroup(INTEL_GROUP_SNB)) {
 		TRACE("SandyBridge clock gating\n");
 		write32(info, 0x42020, (1L << 28) | (1L << 7) | (1L << 5));
-	} else if (info.device_type.InGroup(INTEL_TYPE_IVB)) {
+	} else if (info.device_type.InGroup(INTEL_GROUP_IVB)) {
 		TRACE("IvyBridge clock gating\n");
 		write32(info, 0x42020, (1L << 28));
-	} else if (info.device_type.InGroup(INTEL_TYPE_VLV)) {
+	} else if (info.device_type.InGroup(INTEL_GROUP_SLV)) {
 		TRACE("ValleyView clock gating\n");
 		write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28));
-	} else if (info.device_type.InGroup(INTEL_TYPE_ILK)) {
+	} else if (info.device_type.InGroup(INTEL_GROUP_ILK)) {
 		TRACE("IronLake clock gating\n");
 		write32(info, 0x42020, (1L << 7) | (1L << 5));
-	} else if (info.device_type.InGroup(INTEL_TYPE_G4x)) {
+	} else if (info.device_type.InGroup(INTEL_GROUP_G4x)) {
 		TRACE("G4x clock gating\n");
 		write32(info, 0x6204, 0);
 		write32(info, 0x6208, (1L << 9) | (1L << 7) | (1L << 6));
@@ -70,8 +70,8 @@ intel_en_downclock(intel_info &info)
 {
 	CALLED();
 
-	if (!info.device_type.InGroup(INTEL_TYPE_SNB)
-		&& !info.device_type.InGroup(INTEL_TYPE_IVB)) {
+	if (!info.device_type.InGroup(INTEL_GROUP_SNB)
+		&& !info.device_type.InGroup(INTEL_GROUP_IVB)) {
 		TRACE("%s: Downclocking not supported on this chipset.\n", __func__);
 		return B_NOT_ALLOWED;
 	}