* Implement inbound isochronous transfer for EHCI, based on UHCI implementation.
* changes next_log to their actual type instead of void* * the field this_phy now includes the item type, it simplifies things. * isochronous transfer descriptors are linked in the periodic frame list first, and points to existing interrupt transfer descriptors. This is still work in progress. Yet it's worth committing as it doesn't seem to have impacts, and is required for the UVC SoC project. Tested basically with usb_webcam to receive UVC stream headers. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41424 a95241bf-73f2-0310-859d-f6bbb57e9c96
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Jérôme Duval
parent
16d113f9e5
commit
7df33d912b
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@ -27,6 +27,26 @@ typedef struct transfer_data {
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} transfer_data;
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// This structure is used to create a list of
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// descriptors per isochronous transfer
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typedef struct isochronous_transfer_data {
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Transfer * transfer;
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// The next field is used to keep track
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// of every isochronous descriptor as they are NOT
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// linked to each other in a queue like in every other
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// transfer type
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ehci_itd ** descriptors;
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uint16 last_to_process;
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bool incoming;
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bool is_active;
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isochronous_transfer_data * link;
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size_t buffer_size;
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void * buffer_log;
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addr_t buffer_phy;
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} isochronous_transfer_data;
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class EHCI : public BusManager {
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public:
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EHCI(pci_info *info, Stack *stack);
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@ -35,7 +55,9 @@ public:
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status_t Start();
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virtual status_t SubmitTransfer(Transfer *transfer);
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virtual status_t CancelQueuedTransfers(Pipe *pipe, bool force);
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status_t CancelQueuedIsochronousTransfers(Pipe *pipe, bool force);
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status_t SubmitIsochronous(Transfer *transfer);
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virtual status_t NotifyPipeChange(Pipe *pipe,
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usb_change change);
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@ -66,13 +88,32 @@ static int32 InterruptHandler(void *data);
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ehci_qh *queueHead,
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ehci_qtd *dataDescriptor,
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bool directionIn);
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status_t AddPendingIsochronousTransfer(
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Transfer *transfer,
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ehci_itd **isoRequest, uint32 lastIndex,
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bool directionIn, addr_t bufferPhy,
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void *bufferLog, size_t bufferSize);
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status_t CancelAllPendingTransfers();
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static int32 FinishThread(void *data);
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void FinishTransfers();
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static int32 CleanupThread(void *data);
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void Cleanup();
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// Isochronous transfer functions
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static int32 FinishIsochronousThread(void *data);
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void FinishIsochronousTransfers();
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isochronous_transfer_data * FindIsochronousTransfer(ehci_itd *itd);
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void LinkITDescriptors(ehci_itd *itd,
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ehci_itd **last);
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void LinkSITDescriptors(ehci_sitd *sitd,
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ehci_sitd **last);
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void UnlinkITDescriptors(ehci_itd *itd,
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ehci_itd **last);
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void UnlinkSITDescriptors(ehci_sitd *sitd,
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ehci_sitd **last);
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// Queue Head functions
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ehci_qh * CreateQueueHead();
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status_t InitQueueHead(ehci_qh *queueHead,
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@ -95,6 +136,9 @@ static int32 CleanupThread(void *data);
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ehci_qtd **dataDescriptor,
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bool *directionIn);
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bool LockIsochronous();
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void UnlockIsochronous();
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// Descriptor functions
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ehci_qtd * CreateDescriptor(
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size_t bufferSizeToAllocate,
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@ -105,9 +149,15 @@ static int32 CleanupThread(void *data);
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ehci_qtd *strayDescriptor,
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size_t bufferSizeToAllocate,
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uint8 pid);
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ehci_itd* CreateItdDescriptor();
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ehci_sitd* CreateSitdDescriptor();
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void FreeDescriptor(ehci_qtd *descriptor);
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void FreeDescriptorChain(ehci_qtd *topDescriptor);
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void FreeDescriptor(ehci_itd *descriptor);
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void FreeDescriptor(ehci_sitd *descriptor);
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void FreeIsochronousData(
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isochronous_transfer_data *data);
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void LinkDescriptors(ehci_qtd *first,
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ehci_qtd *last, ehci_qtd *alt);
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@ -120,6 +170,12 @@ static int32 CleanupThread(void *data);
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bool *nextDataToggle);
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size_t ReadActualLength(ehci_qtd *topDescriptor,
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bool *nextDataToggle);
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size_t WriteIsochronousDescriptorChain(
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isochronous_transfer_data *transfer,
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uint32 packetCount,
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iovec *vector);
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size_t ReadIsochronousDescriptorChain(
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isochronous_transfer_data *transfer);
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// Operational register functions
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inline void WriteOpReg(uint32 reg, uint32 value);
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@ -143,6 +199,8 @@ static pci_module_info * sPCIModule;
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area_id fPeriodicFrameListArea;
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addr_t * fPeriodicFrameList;
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interrupt_entry * fInterruptEntries;
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ehci_itd ** fItdEntries;
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ehci_sitd ** fSitdEntries;
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// Async transfer queue management
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ehci_qh * fAsyncQueueHead;
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@ -153,12 +211,24 @@ static pci_module_info * sPCIModule;
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transfer_data * fLastTransfer;
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sem_id fFinishTransfersSem;
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thread_id fFinishThread;
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Pipe * fProcessingPipe;
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ehci_qh * fFreeListHead;
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sem_id fCleanupSem;
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thread_id fCleanupThread;
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bool fStopThreads;
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ehci_qh * fFreeListHead;
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Pipe * fProcessingPipe;
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// fFrameBandwidth[n] holds the available bandwidth
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// of the nth frame in microseconds
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uint16 * fFrameBandwidth;
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// Maintain a linked list of isochronous transfers
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isochronous_transfer_data * fFirstIsochronousTransfer;
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isochronous_transfer_data * fLastIsochronousTransfer;
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sem_id fFinishIsochronousTransfersSem;
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thread_id fFinishIsochronousThread;
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mutex fIsochronousLock;
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// Root Hub
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EHCIRootHub * fRootHub;
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uint8 fRootHubAddress;
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@ -16,7 +16,6 @@
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#define EHCI_HCCPARAMS 0x08 // Capability Parameters
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#define EHCI_HCSP_PORTROUTE 0x0c // Companion Port Route Description
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// Host Controller Operational Registers (EHCI Spec 2.3)
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#define EHCI_USBCMD 0x00 // USB Command
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#define EHCI_USBSTS 0x04 // USB Status
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@ -105,22 +104,89 @@
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#define EHCI_LEGSUP_OSOWNED (1 << 24) // OS Owned Semaphore
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#define EHCI_LEGSUP_BIOSOWNED (1 << 16) // BIOS Owned Semaphore
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#define EHCI_HCCPARAMS_IPT_SHIFT 4 // Isochronous Periodic Threshold
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#define EHCI_HCCPARAMS_IPT_MASK 0xf
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// Data Structures (EHCI Spec 3)
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// Periodic Frame List Element Flags (EHCI Spec 3.1)
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#define EHCI_PFRAMELIST_TERM (1 << 0) // Terminate
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#define EHCI_PFRAMELIST_ITD (0 << 1) // Isochronous Transfer Descriptor
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#define EHCI_PFRAMELIST_QH (1 << 1) // Queue Head
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#define EHCI_PFRAMELIST_SITD (2 << 1) // Split Transaction Isochronous TD
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#define EHCI_PFRAMELIST_FSTN (3 << 1) // Frame Span Traversal Node
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// Applies to ehci_qh.next_phy, ehci_sitd.next_phy, ehci_itd.next_phy
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#define EHCI_ITEM_TYPE_ITD (0 << 1) // Isochronous Transfer Descriptor
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#define EHCI_ITEM_TYPE_QH (1 << 1) // Queue Head
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#define EHCI_ITEM_TYPE_SITD (2 << 1) // Split Transaction Isochronous TD
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#define EHCI_ITEM_TYPE_FSTN (3 << 1) // Frame Span Traversal Node
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#define EHCI_ITEM_TERMINATE (1 << 0) // Terminate
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// ToDo: Isochronous (High-Speed) Transfer Descriptors (iTD, EHCI Spec 3.2)
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// ToDo: Split Transaction Isochronous Transfer Descriptors (siTD, EHCI Spec 3.3)
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// Isochronous (High-Speed) Transfer Descriptors (iTD, EHCI Spec 3.2)
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typedef struct ehci_itd {
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// Hardware Part
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addr_t next_phy;
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uint32 token[8];
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addr_t buffer_phy[7];
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addr_t ext_buffer_phy[7];
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// Software Part
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addr_t this_phy;
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struct ehci_itd *next;
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struct ehci_itd *prev;
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uint32 last_token;
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} ehci_itd;
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#define EHCI_ITD_TOFFSET_SHIFT 0
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#define EHCI_ITD_TOFFSET_MASK 0x0fff
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#define EHCI_ITD_IOC (1 << 15)
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#define EHCI_ITD_PG_SHIFT 12
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#define EHCI_ITD_PG_MASK 0x07
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#define EHCI_ITD_TLENGTH_SHIFT 16
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#define EHCI_ITD_TLENGTH_MASK 0x0fff
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#define EHCI_ITD_STATUS_SHIFT 28
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#define EHCI_ITD_STATUS_MASK 0xf
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#define EHCI_ITD_STATUS_ACTIVE (1 << 3) // Active
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#define EHCI_ITD_STATUS_BUFFER (1 << 2) // Data Buffer Error
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#define EHCI_ITD_STATUS_BABBLE (1 << 1) // Babble Detected
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#define EHCI_ITD_STATUS_TERROR (1 << 0) // Transaction Error
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#define EHCI_ITD_ADDRESS_SHIFT 0
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#define EHCI_ITD_ADDRESS_MASK 0x7f
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#define EHCI_ITD_ENDPOINT_SHIFT 8
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#define EHCI_ITD_ENDPOINT_MASK 0xf
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#define EHCI_ITD_DIR_SHIFT 11
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#define EHCI_ITD_MUL_SHIFT 0
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#define EHCI_ITD_BUFFERPOINTER_SHIFT 12
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#define EHCI_ITD_BUFFERPOINTER_MASK 0xfffff
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#define EHCI_ITD_MAXPACKETSIZE_SHIFT 0
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#define EHCI_ITD_MAXPACKETSIZE_MASK 0x7ff
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// Split Transaction Isochronous Transfer Descriptors (siTD, EHCI Spec 3.3)
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typedef struct ehci_sitd {
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// Hardware Part
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addr_t next_phy;
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uint8 port_number;
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uint8 hub_address;
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uint8 endpoint;
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uint8 device_address;
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uint16 reserved1;
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uint8 cmask;
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uint8 smask;
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uint16 transfer_length;
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uint8 cprogmask;
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uint8 status;
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addr_t buffer_phy[2];
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addr_t back_phy;
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addr_t ext_buffer_phy[2];
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// Software Part
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addr_t this_phy;
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struct ehci_sitd *next;
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struct ehci_sitd *prev;
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size_t buffer_size;
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void *buffer_log;
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} ehci_sitd;
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// Queue Element Transfer Descriptors (qTD, EHCI Spec 3.5)
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typedef struct {
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typedef struct ehci_qtd {
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// Hardware Part
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addr_t next_phy;
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addr_t alt_next_phy;
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@ -130,14 +196,13 @@ typedef struct {
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// Software Part
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addr_t this_phy;
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void *next_log;
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struct ehci_qtd *next_log;
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void *alt_next_log;
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size_t buffer_size;
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void *buffer_log;
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} ehci_qtd;
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#define EHCI_QTD_TERMINATE (1 << 0)
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#define EHCI_QTD_DATA_TOGGLE (1 << 31)
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#define EHCI_QTD_BYTES_SHIFT 16
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#define EHCI_QTD_BYTES_MASK 0x7fff
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@ -166,7 +231,7 @@ typedef struct {
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// Queue Head (QH, EHCI Spec 3.6)
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typedef struct {
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typedef struct ehci_qh {
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// Hardware Part
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addr_t next_phy;
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uint32 endpoint_chars;
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@ -183,10 +248,10 @@ typedef struct {
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// Software Part
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addr_t this_phy;
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void *next_log;
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void *prev_log;
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void *stray_log;
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void *element_log;
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struct ehci_qh *next_log;
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struct ehci_qh *prev_log;
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ehci_qtd *stray_log;
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ehci_qtd *element_log;
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} ehci_qh;
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@ -195,13 +260,22 @@ typedef struct {
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uint32 padding[2];
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} interrupt_entry;
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typedef struct {
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ehci_itd itd;
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uint32 padding[5]; // align on 128
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} itd_entry;
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typedef struct {
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ehci_sitd sitd;
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uint32 padding[2]; // align on 64
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} sitd_entry;
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#define EHCI_INTERRUPT_ENTRIES_COUNT (7 + 1) // (log 128 / log 2) + 1
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#define EHCI_VFRAMELIST_ENTRIES_COUNT 128
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#define EHCI_FRAMELIST_ENTRIES_COUNT 1024
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#define MAX_AVAILABLE_BANDWIDTH 125 // Microseconds
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// Applies to ehci_qh.link_phy
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#define EHCI_QH_TYPE_ITD (0 << 1)
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#define EHCI_QH_TYPE_QH (1 << 1)
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#define EHCI_QH_TYPE_SITD (2 << 1)
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#define EHCI_QH_TYPE_FSTN (3 << 1)
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#define EHCI_QH_TERMINATE (1 << 0)
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// Applies to ehci_qh.endpoint_chars
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#define EHCI_QH_CHARS_RL_SHIFT 28 // NAK Count Reload
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