Fixed ordering of registers in arch_debug_gdb_get_registers.
Current code was sending EAX, EBX, ECX, EDX..., GDB (all versions as far as I can tell) expects EAX, ECX, EDX, EBX... Also added missing FS and GS.
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@ -1188,21 +1188,22 @@ arch_debug_gdb_get_registers(char* buffer, size_t bufferSize)
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// For x86 the register order is:
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// For x86 the register order is:
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//
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//
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// eax, ebx, ecx, edx,
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// eax, ecx, edx, ebx,
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// esp, ebp, esi, edi,
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// esp, ebp, esi, edi,
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// eip, eflags,
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// eip, eflags,
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// cs, ss, ds, es
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// cs, ss, ds, es, fs, gs
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//
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//
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// Note that even though the segment descriptors are actually 16 bits wide,
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// Note that even though the segment descriptors are actually 16 bits wide,
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// gdb requires them as 32 bit integers. Note also that for some reason
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// gdb requires them as 32 bit integers. Note also that for some reason
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// gdb wants the register dump in *big endian* format.
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// gdb wants the register dump in *big endian* format.
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static const int32 kRegisterCount = 14;
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static const int32 kRegisterCount = 16;
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uint32 registers[kRegisterCount] = {
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uint32 registers[kRegisterCount] = {
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frame->eax, frame->ebx, frame->ecx, frame->edx,
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frame->eax, frame->ecx, frame->edx, frame->ebx,
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frame->esp, frame->ebp, frame->esi, frame->edi,
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frame->esp, frame->ebp, frame->esi, frame->edi,
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frame->eip, frame->flags,
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frame->eip, frame->flags,
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frame->cs, frame->ds, frame->ds, frame->es
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frame->cs, frame->ds, frame->ds, frame->es,
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// assume ss == ds
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// assume ss == ds
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frame->fs, frame->gs
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};
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};
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const char* const bufferStart = buffer;
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const char* const bufferStart = buffer;
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