Update to actual AGE driver version. (Tested on real hardware - work fine)
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33158 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -7,7 +7,7 @@
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#include <sys/bus.h>
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HAIKU_FBSD_DRIVER_GLUE(attansic_l1, age, pci);
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HAIKU_FBSD_DRIVER_GLUE(atl1, age, pci);
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HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE);
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@ -28,7 +28,7 @@
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/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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__FBSDID("$FreeBSD: src/sys/dev/age/if_age.c,v 1.6 2008/11/07 07:02:28 yongari Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -67,7 +67,6 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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#include <machine/in_cksum.h>
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#include <machine/resource.h>
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#include "if_agereg.h"
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#include "if_agevar.h"
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@ -93,6 +92,8 @@ __FBSDID("$FreeBSD$");
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#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
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#endif
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#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
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MODULE_DEPEND(age, pci, 1, 1, 1);
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MODULE_DEPEND(age, ether, 1, 1, 1);
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MODULE_DEPEND(age, miibus, 1, 1, 1);
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@ -120,8 +121,6 @@ static int age_miibus_writereg(device_t, int, int, int);
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static void age_miibus_statchg(device_t);
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static void age_mediastatus(struct ifnet *, struct ifmediareq *);
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static int age_mediachange(struct ifnet *);
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static int age_read_vpd_word(struct age_softc *, uint32_t, uint32_t,
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uint32_t *);
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static int age_probe(device_t);
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static void age_get_macaddr(struct age_softc *);
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static void age_phy_reset(struct age_softc *);
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@ -334,29 +333,6 @@ age_mediachange(struct ifnet *ifp)
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return (error);
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}
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static int
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age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset,
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uint32_t *word)
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{
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int i;
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pci_write_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, offset, 2);
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for (i = AGE_TIMEOUT; i > 0; i--) {
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DELAY(10);
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if ((pci_read_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, 2) &
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0x8000) == 0x8000)
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break;
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}
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if (i == 0) {
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device_printf(sc->age_dev, "VPD read timeout!\n");
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*word = 0;
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return (ETIMEDOUT);
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}
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*word = pci_read_config(sc->age_dev, vpdc + PCIR_VPD_DATA, 4);
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return (0);
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}
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static int
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age_probe(device_t dev)
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{
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@ -382,8 +358,8 @@ age_probe(device_t dev)
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static void
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age_get_macaddr(struct age_softc *sc)
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{
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uint32_t ea[2], off, reg, word;
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int vpd_error, match, vpdc;
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uint32_t ea[2], reg;
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int i, vpdc;
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reg = CSR_READ_4(sc, AGE_SPI_CTRL);
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if ((reg & SPI_VPD_ENB) != 0) {
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@ -392,130 +368,120 @@ age_get_macaddr(struct age_softc *sc)
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CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
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}
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vpd_error = 0;
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ea[0] = ea[1] = 0;
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if ((vpd_error = pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc)) == 0) {
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if (pci_find_extcap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
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/*
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* PCI VPD capability exists, but it seems that it's
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* not in the standard form as stated in PCI VPD
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* specification such that driver could not use
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* pci_get_vpd_readonly(9) with keyword 'NA'.
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* Search VPD data starting at address 0x0100. The data
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* chwould be used as initializers to set AGE_PAR0,
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* AGE_PAR1 register including other PCI configuration
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* registers.
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* PCI VPD capability found, let TWSI reload EEPROM.
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* This will set ethernet address of controller.
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*/
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word = 0;
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match = 0;
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reg = 0;
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for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END;
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off += sizeof(uint32_t)) {
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vpd_error = age_read_vpd_word(sc, vpdc, off, &word);
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if (vpd_error != 0)
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break;
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if (match != 0) {
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switch (reg) {
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case AGE_PAR0:
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ea[0] = word;
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break;
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case AGE_PAR1:
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ea[1] = word;
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break;
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default:
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break;
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}
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match = 0;
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} else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) {
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match = 1;
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reg = word >> 16;
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} else
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CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
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TWSI_CTRL_SW_LD_START);
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for (i = 100; i > 0; i--) {
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DELAY(1000);
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reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
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if ((reg & TWSI_CTRL_SW_LD_START) == 0)
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break;
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}
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if (off >= AGE_VPD_REG_CONF_END)
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vpd_error = ENOENT;
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if (vpd_error == 0) {
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/*
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* Don't blindly trust ethernet address obtained
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* from VPD. Check whether ethernet address is
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* valid one. Otherwise fall-back to reading
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* PAR register.
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*/
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ea[1] &= 0xFFFF;
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if ((ea[0] == 0 && ea[1] == 0) ||
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(ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) {
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if (1 || bootverbose)
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device_printf(sc->age_dev,
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"invalid ethernet address "
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"returned from VPD.\n");
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vpd_error = EINVAL;
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}
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}
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if (vpd_error != 0 && (1 || bootverbose))
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device_printf(sc->age_dev, "VPD access failure!\n");
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if (i == 0)
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device_printf(sc->age_dev,
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"reloading EEPROM timeout!\n");
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} else {
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if (1 || bootverbose)
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if (bootverbose)
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device_printf(sc->age_dev,
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"PCI VPD capability not found!\n");
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}
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/*
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* It seems that L1 also provides a way to extract ethernet
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* address via SPI flash interface. Because SPI flash memory
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* device of different vendors vary in their instruction
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* codes for read ID instruction, it's very hard to get
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* instructions codes without detailed information for the
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* flash memory device used on ethernet controller. To simplify
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* code, just read AGE_PAR0/AGE_PAR1 register to get ethernet
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* address which is supposed to be set by hardware during
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* power on reset.
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*/
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if (vpd_error != 0) {
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/*
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* VPD is mapped to SPI flash memory or BIOS set it.
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*/
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ea[0] = CSR_READ_4(sc, AGE_PAR0);
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ea[1] = CSR_READ_4(sc, AGE_PAR1);
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}
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ea[1] &= 0xFFFF;
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if ((ea[0] == 0 && ea[1] == 0) ||
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(ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) {
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device_printf(sc->age_dev,
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"generating fake ethernet address.\n");
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#ifdef __HAIKU__
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ea[0] = random();
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#else
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ea[0] = arc4random();
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#endif
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/* Set OUI to ASUSTek COMPUTER INC. */
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sc->age_eaddr[0] = 0x00;
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sc->age_eaddr[1] = 0x1B;
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sc->age_eaddr[2] = 0xFC;
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sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
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sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
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sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
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} else {
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sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
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sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
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sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
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sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
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sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
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sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
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}
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ea[0] = CSR_READ_4(sc, AGE_PAR0);
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ea[1] = CSR_READ_4(sc, AGE_PAR1);
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sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
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sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
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sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
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sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
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sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
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sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
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}
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static void
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age_phy_reset(struct age_softc *sc)
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{
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uint16_t reg, pn;
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int i, linkup;
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/* Reset PHY. */
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CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
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// pause("agephy", hz / 1000);
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DELAY(1000);
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DELAY(2000);
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CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
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DELAY(1000);
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//pause("agephy", hz / 1000);
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DELAY(2000);
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#define ATPHY_DBG_ADDR 0x1D
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#define ATPHY_DBG_DATA 0x1E
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#define ATPHY_CDTC 0x16
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#define PHY_CDTC_ENB 0x0001
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#define PHY_CDTC_POFF 8
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#define ATPHY_CDTS 0x1C
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#define PHY_CDTS_STAT_OK 0x0000
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#define PHY_CDTS_STAT_SHORT 0x0100
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#define PHY_CDTS_STAT_OPEN 0x0200
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#define PHY_CDTS_STAT_INVAL 0x0300
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#define PHY_CDTS_STAT_MASK 0x0300
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/* Check power saving mode. Magic from Linux. */
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
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for (linkup = 0, pn = 0; pn < 4; pn++) {
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
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(pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
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for (i = 200; i > 0; i--) {
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DELAY(1000);
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reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
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ATPHY_CDTC);
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if ((reg & PHY_CDTC_ENB) == 0)
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break;
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}
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DELAY(1000);
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reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
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ATPHY_CDTS);
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if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
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#if 1
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device_printf(sc->age_dev, "link found!\n");
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#endif
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linkup++;
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break;
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}
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}
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
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BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
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if (linkup == 0) {
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#if 1
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device_printf(sc->age_dev, "waking up PHY\n");
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#endif
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
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ATPHY_DBG_ADDR, 0);
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA, 0x124E);
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
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ATPHY_DBG_ADDR, 1);
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reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA);
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA, reg | 0x03);
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/* XXX */
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DELAY(1500 * 1000);
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
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ATPHY_DBG_ADDR, 0);
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age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
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ATPHY_DBG_DATA, 0x024E);
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}
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#undef ATPHY_DBG_ADDR
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#undef ATPHY_DBG_DATA
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#undef ATPHY_CDTC
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#undef PHY_CDTC_ENB
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#undef PHY_CDTC_POFF
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#undef ATPHY_CDTS
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#undef PHY_CDTS_STAT_OK
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#undef PHY_CDTS_STAT_SHORT
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#undef PHY_CDTS_STAT_OPEN
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#undef PHY_CDTS_STAT_INVAL
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#undef PHY_CDTS_STAT_MASK
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}
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static int
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@ -559,8 +525,9 @@ age_attach(device_t dev)
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sc->age_rev = pci_get_revid(dev);
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sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
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MASTER_CHIP_REV_SHIFT;
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if (1 || bootverbose) {
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device_printf(dev, "PCI device revision : 0x%04x\n", sc->age_rev);
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if (bootverbose) {
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device_printf(dev, "PCI device revision : 0x%04x\n",
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sc->age_rev);
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device_printf(dev, "Chip id/revision : 0x%04x\n",
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sc->age_chip_rev);
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}
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@ -586,7 +553,7 @@ age_attach(device_t dev)
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/* Allocate IRQ resources. */
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msixc = pci_msix_count(dev);
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msic = pci_msi_count(dev);
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if (1 || bootverbose) {
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if (bootverbose) {
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device_printf(dev, "MSIX count : %d\n", msixc);
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device_printf(dev, "MSI count : %d\n", msic);
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}
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@ -633,7 +600,7 @@ age_attach(device_t dev)
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/* Max payload size. */
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sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
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DMA_CFG_WR_BURST_SHIFT;
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if (1 || bootverbose) {
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if (bootverbose) {
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device_printf(dev, "Read request size : %d bytes.\n",
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128 << ((burst >> 12) & 0x07));
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device_printf(dev, "TLP payload size : %d bytes.\n",
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@ -1390,7 +1357,7 @@ age_setwol(struct age_softc *sc)
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AGE_LOCK_ASSERT(sc);
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if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) == 0) {
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if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
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CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
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/*
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* No PME capability, PHY power down.
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@ -1448,7 +1415,7 @@ age_setwol(struct age_softc *sc)
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MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
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DELAY(1000);
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if (aneg != 0) {
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/* Poll link state until jme(4) get a 10/100 link. */
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/* Poll link state until age(4) get a 10/100 link. */
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for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
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mii_pollstat(mii);
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if ((mii->mii_media_status & IFM_AVALID) != 0) {
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@ -1463,8 +1430,11 @@ age_setwol(struct age_softc *sc)
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}
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}
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AGE_UNLOCK(sc);
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//pause("agelnk", hz);
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#ifdef __HAIKU__
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DELAY(1);
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#else
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pause("agelnk", hz);
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#endif
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AGE_LOCK(sc);
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}
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if (i == MII_ANEGTICKS_GIGE)
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@ -1546,6 +1516,9 @@ age_resume(device_t dev)
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cmd &= ~0x0400;
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pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2);
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}
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AGE_UNLOCK(sc);
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age_phy_reset(sc);
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AGE_LOCK(sc);
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ifp = sc->age_ifp;
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if ((ifp->if_flags & IFF_UP) != 0)
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age_init_locked(sc);
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@ -1579,12 +1552,13 @@ age_encap(struct age_softc *sc, struct mbuf **m_head)
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ip_off = poff = 0;
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if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
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/*
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* L1 requires TCP/UDP payload offset in its Tx descriptor
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* to perform hardware Tx checksum offload. Additionally
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* TSO requires IP/TCP header size and modification of
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* IP/TCP header in order to make TSO engine work. This
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* kind of operation takes many CPU cycles so fast host
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* CPU is needed to get smooth TSO performance.
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* L1 requires offset of TCP/UDP payload in its Tx
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* descriptor to perform hardware Tx checksum offload.
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* Additionally, TSO requires IP/TCP header size and
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* modification of IP/TCP header in order to make TSO
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* engine work. This kind of operation takes many CPU
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* cycles on FreeBSD so fast host CPU is needed to get
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* smooth TSO performance.
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*/
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struct ether_header *eh;
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@ -1633,11 +1607,18 @@ age_encap(struct age_softc *sc, struct mbuf **m_head)
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||||
}
|
||||
tcp = (struct tcphdr *)(mtod(m, char *) + poff);
|
||||
/*
|
||||
* L1 requires IP/TCP header size and offset as well
|
||||
* as TCP pseudo checksum which all complicates TSO
|
||||
* configuration. Hopefully this wouldn't be much
|
||||
* burden on modern CPUs.
|
||||
* Reset IP checksum and recompute TCP pseudo checksum.
|
||||
* L1 requires IP/TCP header size and offset as
|
||||
* well as TCP pseudo checksum which complicates
|
||||
* TSO configuration. I guess this comes from the
|
||||
* adherence to Microsoft NDIS Large Send
|
||||
* specification which requires insertion of
|
||||
* pseudo checksum by upper stack. The pseudo
|
||||
* checksum that NDIS refers to doesn't include
|
||||
* TCP payload length so age(4) should recompute
|
||||
* the pseudo checksum here. Hopefully this wouldn't
|
||||
* be much burden on modern CPUs.
|
||||
* Reset IP checksum and recompute TCP pseudo
|
||||
* checksum as NDIS specification said.
|
||||
*/
|
||||
ip->ip_sum = 0;
|
||||
if (poff + (tcp->th_off << 2) == m->m_pkthdr.len)
|
||||
@ -2492,9 +2473,6 @@ age_rxintr(struct age_softc *sc, int rr_prod, int count)
|
||||
bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
|
||||
sc->age_cdata.age_rr_ring_map,
|
||||
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
|
||||
sc->age_cdata.age_rx_ring_map,
|
||||
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
|
||||
|
||||
for (prog = 0; rr_cons != rr_prod; prog++) {
|
||||
if (count <= 0)
|
||||
@ -2527,9 +2505,6 @@ age_rxintr(struct age_softc *sc, int rr_prod, int count)
|
||||
sc->age_cdata.age_rr_cons = rr_cons;
|
||||
|
||||
/* Sync descriptors. */
|
||||
bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
|
||||
sc->age_cdata.age_rx_ring_map,
|
||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
||||
bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
|
||||
sc->age_cdata.age_rr_ring_map,
|
||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
||||
@ -2564,14 +2539,8 @@ age_reset(struct age_softc *sc)
|
||||
int i;
|
||||
|
||||
CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
|
||||
for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
|
||||
DELAY(1);
|
||||
if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0)
|
||||
break;
|
||||
}
|
||||
if (i == 0)
|
||||
device_printf(sc->age_dev, "master reset timeout!\n");
|
||||
|
||||
CSR_READ_4(sc, AGE_MASTER_CFG);
|
||||
DELAY(1000);
|
||||
for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
|
||||
if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
|
||||
break;
|
||||
@ -2705,7 +2674,7 @@ age_init_locked(struct age_softc *sc)
|
||||
else
|
||||
reg |= MASTER_ITIMER_ENB;
|
||||
CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
|
||||
if (1 || bootverbose)
|
||||
if (bootverbose)
|
||||
device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
|
||||
sc->age_int_mod);
|
||||
CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
|
||||
@ -3231,7 +3200,8 @@ sysctl_age_stats(SYSCTL_HANDLER_ARGS)
|
||||
return (error);
|
||||
|
||||
sc = (struct age_softc *)arg1;
|
||||
stats = &sc->age_stat; /*
|
||||
stats = &sc->age_stat;
|
||||
#if 0
|
||||
printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
|
||||
printf("Transmit good frames : %ju\n",
|
||||
(uintmax_t)stats->tx_frames);
|
||||
@ -3331,7 +3301,8 @@ sysctl_age_stats(SYSCTL_HANDLER_ARGS)
|
||||
printf("Receive frames with alignment errors : %u\n",
|
||||
stats->rx_alignerrs);
|
||||
printf("Receive frames dropped due to address filtering : %ju\n",
|
||||
(uint64_t)stats->rx_pkts_filtered);*/
|
||||
(uint64_t)stats->rx_pkts_filtered);
|
||||
#endif
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
@ -24,7 +24,7 @@
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD
|
||||
* $FreeBSD: src/sys/dev/age/if_agereg.h,v 1.1 2008/05/19 01:39:59 yongari Exp $
|
||||
*/
|
||||
|
||||
#ifndef _IF_AGEREG_H
|
||||
@ -91,6 +91,9 @@
|
||||
#define AGE_SPI_OP_READ 0x217 /* 8bits */
|
||||
|
||||
#define AGE_TWSI_CTRL 0x218
|
||||
#define TWSI_CTRL_SW_LD_START 0x00000800
|
||||
#define TWSI_CTRL_HW_LD_START 0x00001000
|
||||
#define TWSI_CTRL_LD_EXIST 0x00400000
|
||||
|
||||
#define AGE_DEV_MISC_CTRL 0x21C
|
||||
|
||||
@ -483,10 +486,6 @@
|
||||
(INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \
|
||||
INTR_CMB_TX | INTR_CMB_RX)
|
||||
|
||||
#define AGE_RD_RRD_IDX 0x1800
|
||||
|
||||
#define AGE_TPD_IDX 0x1804
|
||||
|
||||
/* Statistics counters collected by the MAC. */
|
||||
struct smb {
|
||||
/* Rx stats. */
|
||||
|
Loading…
Reference in New Issue
Block a user