Patch by Euan Kirkhope:
* VIP FIFO functions for Rage Theater200 support git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@20278 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
0caeca2af7
commit
7ce2eaa1e0
@ -20,8 +20,8 @@
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#include "ddc.h"
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// magic code for ioctls
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// changed from TKRA to TKR1 for RADEON_WAITFORFIFO ioctl
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#define RADEON_PRIVATE_DATA_MAGIC 'TKR1'
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// changed from TKRA to TKR2 for VIP FIFO ioctls
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#define RADEON_PRIVATE_DATA_MAGIC 'TKR2'
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#define MAX_RADEON_DEVICE_NAME_LENGTH MAXPATHLEN
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@ -40,7 +40,10 @@ enum {
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RADEON_RESETENGINE,
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RADEON_VIPREAD,
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RADEON_VIPWRITE,
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RADEON_VIPFIFOREAD,
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RADEON_VIPFIFOWRITE,
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RADEON_FINDVIPDEVICE,
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RADEON_VIPRESET,
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RADEON_WAIT_FOR_CAP_IRQ,
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RADEON_DMACOPY,
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@ -633,6 +636,26 @@ typedef struct {
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bool lock; // true, if CP lock must be acquired
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} radeon_vip_write;
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// read VIP fifo
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typedef struct {
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uint32 magic;
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uint channel; // channel, i.e. device
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uint address; // address
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uint32 count; // size of buffer
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uint8 *data; // read data
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bool lock; // true, if CP lock must be acquired
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} radeon_vip_fifo_read;
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// write VIP fifo
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typedef struct {
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uint32 magic;
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uint channel; // channel, i.e. device
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uint address; // address
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uint32 count; // size of buffer
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uint8 *data; // data to write
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bool lock; // true, if CP lock must be acquired
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} radeon_vip_fifo_write;
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// find channel of device with given ID
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typedef struct {
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uint32 magic;
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@ -640,6 +663,13 @@ typedef struct {
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uint channel; // channel of device (-1 if not found)
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} radeon_find_vip_device;
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// reset / init VIP
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typedef struct {
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uint32 magic;
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bool lock;
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} radeon_vip_reset;
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// wait for capture interrupt and get status about
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typedef struct {
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uint32 magic;
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@ -8,4 +8,4 @@
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*/
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// current version
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#define RADEON_DRIVER_VERSION "Version: 5.1.4.9"
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#define RADEON_DRIVER_VERSION "Version: 5.1.5.0"
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@ -400,6 +400,26 @@ static status_t control_hook( void *dev, uint32 msg, void *buf, size_t len )
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vw->lock ) ? B_OK : B_ERROR;
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} break;
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case RADEON_VIPFIFOREAD: {
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radeon_vip_fifo_read *vr = (radeon_vip_fifo_read *)buf;
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if( vr->magic != RADEON_PRIVATE_DATA_MAGIC )
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break;
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result = Radeon_VIPFifoRead( di, vr->channel, vr->address, vr->count, vr->data,
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vr->lock ) ? B_OK : B_ERROR;
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} break;
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case RADEON_VIPFIFOWRITE: {
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radeon_vip_fifo_write *vw = (radeon_vip_fifo_write *)buf;
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if( vw->magic != RADEON_PRIVATE_DATA_MAGIC )
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break;
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result = Radeon_VIPFifoWrite( di, vw->channel, vw->address, vw->count, vw->data,
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vw->lock ) ? B_OK : B_ERROR;
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} break;
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case RADEON_FINDVIPDEVICE: {
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radeon_find_vip_device *fvd = (radeon_find_vip_device *)buf;
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@ -409,7 +429,18 @@ static status_t control_hook( void *dev, uint32 msg, void *buf, size_t len )
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fvd->channel = Radeon_FindVIPDevice( di, fvd->device_id );
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result = B_OK;
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} break;
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case RADEON_VIPRESET: {
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radeon_vip_reset *fvd = (radeon_vip_reset *)buf;
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if( fvd->magic != RADEON_PRIVATE_DATA_MAGIC )
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break;
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Radeon_VIPReset( di, fvd->lock );
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result = B_OK;
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} break;
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case RADEON_WAIT_FOR_CAP_IRQ: {
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radeon_wait_for_cap_irq *wvc = (radeon_wait_for_cap_irq *)buf;
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@ -225,7 +225,10 @@ void Radeon_SetDynamicClock( device_info *di, int mode );
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// vip.c
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bool Radeon_VIPRead( device_info *di, uint channel, uint address, uint32 *data, bool lock );
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bool Radeon_VIPWrite( device_info *di, uint8 channel, uint address, uint32 data, bool lock );
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bool Radeon_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock);
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bool Radeon_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock);
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int Radeon_FindVIPDevice( device_info *di, uint32 device_id );
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void Radeon_VIPReset( device_info *di, bool lock );
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// dma.c
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@ -21,6 +21,7 @@
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// moved to bottom to avoid inlining
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static bool Radeon_VIPWaitForIdle( device_info *di );
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static status_t RADEON_VIPFifoIdle(device_info *di, uint8 channel);
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// read data from VIP
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@ -84,6 +85,96 @@ bool Radeon_VIPRead(
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ACQUIRE_BEN( di->si->cp.lock );
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res = do_VIPRead( di, channel, address, data );
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if( lock )
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RELEASE_BEN( di->si->cp.lock );
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// SHOW_FLOW( 2, "address=%x, data=%lx, lock=%d", address, *data, lock );
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return res;
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}
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static bool do_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer)
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{
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vuint8 *regs = di->regs;
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uint32 status, tmp;
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if(count!=1)
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{
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SHOW_FLOW0( 2, "Attempt to access VIP bus with non-stadard transaction length\n");
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return false;
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}
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SHOW_FLOW( 2, "address=%lx, count=%ld ", address, count );
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Radeon_WaitForFifo( di, 2);
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SHOW_FLOW0( 2, "1");
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OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x3000);
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SHOW_FLOW0( 2, "3");
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while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
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if(B_OK != status) return false;
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// disable VIPH_REGR_DIS to enable VIP cycle.
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// The LSB of VIPH_TIMEOUT_STAT are set to 0
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// because 1 would have acknowledged various VIP
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// interrupts unexpectedly
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SHOW_FLOW0( 2, "4");
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Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
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SHOW_FLOW0( 2, "5");
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OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,
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INREG( regs, RADEON_VIPH_TIMEOUT_STAT) &
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(0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS) );
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// the value returned here is garbage. The read merely initiates
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// a register cycle
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SHOW_FLOW0( 2, "6");
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Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
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INREG( regs, RADEON_VIPH_REG_DATA);
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SHOW_FLOW0( 2, "7");
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while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
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if(B_OK != status) return false;
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// set VIPH_REGR_DIS so that the read won't take too long.
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SHOW_FLOW0( 2, "8");
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Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
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SHOW_FLOW0( 2, "9");
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tmp = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
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OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
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SHOW_FLOW0( 2, "10");
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Radeon_WaitForFifo( di, 2 ); // Radeon_WaitForIdle( di, false, false );
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switch(count){
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case 1:
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*buffer=(uint8)(INREG( regs, RADEON_VIPH_REG_DATA) & 0xff);
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break;
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case 2:
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*(uint16 *)buffer=(uint16) (INREG( regs, RADEON_VIPH_REG_DATA) & 0xffff);
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break;
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case 4:
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*(uint32 *)buffer=(uint32) ( INREG( regs, RADEON_VIPH_REG_DATA) & 0xffffffff);
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break;
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}
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SHOW_FLOW0( 2, "11");
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while(B_BUSY == (status = RADEON_VIPFifoIdle( di , 0xff)));
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if(B_OK != status) return false;
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// so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles.
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SHOW_FLOW0( 2, "12");
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OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,
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(INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
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return true;
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}
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bool Radeon_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock)
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{
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bool res;
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if( lock )
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ACQUIRE_BEN( di->si->cp.lock );
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res = do_VIPFifoRead( di, channel, address, count, buffer );
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if( lock )
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RELEASE_BEN( di->si->cp.lock );
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@ -95,31 +186,26 @@ bool Radeon_VIPRead(
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// write data to VIP
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// CP must be hold
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static bool do_VIPWrite(
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device_info *di, uint8 channel, uint address, uint32 data )
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static bool do_VIPWrite( device_info *di, uint8 channel, uint address, uint32 data )
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{
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vuint8 *regs = di->regs;
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bool res;
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Radeon_WaitForFifo( di, 2 );
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OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | (address & ~0x2000) );
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if( !Radeon_VIPWaitForIdle( di ))
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return false;
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if( !Radeon_VIPWaitForIdle( di )) return false;
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//SHOW_FLOW( 4, "channel=%d, address=%x, data=%lx", channel, address, data );
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Radeon_WaitForFifo( di, 2 );
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OUTREG( regs, RADEON_VIPH_REG_DATA, data );
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res = Radeon_VIPWaitForIdle( di );
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return Radeon_VIPWaitForIdle( di );
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return res;
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}
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// public function: write data to VIP
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bool Radeon_VIPWrite(
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device_info *di, uint8 channel, uint address, uint32 data, bool lock )
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bool Radeon_VIPWrite(device_info *di, uint8 channel, uint address, uint32 data, bool lock )
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{
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bool res;
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@ -137,8 +223,64 @@ bool Radeon_VIPWrite(
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}
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static bool do_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer)
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{
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vuint8 *regs = di->regs;
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uint32 status;
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uint32 i;
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SHOW_FLOW( 2, "address=%lx, count=%ld, ", address, count );
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Radeon_WaitForFifo( di, 2 );
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OUTREG( regs, RADEON_VIPH_REG_ADDR, ((channel << 14) | address | 0x1000) & ~0x2000 );
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SHOW_FLOW0( 2, "1");
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while(B_BUSY == (status = RADEON_VIPFifoIdle( di, 0x0f)));
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if(B_OK != status){
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SHOW_FLOW( 2 ,"cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
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return false;
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}
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SHOW_FLOW0( 2, "2");
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for (i = 0; i < count; i+=4)
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{
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Radeon_WaitForFifo( di, 2);
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SHOW_FLOW( 2, "count %ld", count);
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OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i));
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while(B_BUSY == (status = RADEON_VIPFifoIdle( di, 0x0f)));
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if(B_OK != status)
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{
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SHOW_FLOW0( 2 , "cannot write to VIPH_REG_DATA\n");
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return false;
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}
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}
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return true;
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}
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bool Radeon_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer, bool lock)
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{
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bool res;
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//SHOW_FLOW( 2, "address=%x, data=%lx, lock=%d", address, data, lock );
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if( lock )
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ACQUIRE_BEN( di->si->cp.lock );
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Radeon_VIPReset( di, false);
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res = do_VIPFifoWrite( di, channel, address, count, buffer );
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if( lock )
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RELEASE_BEN( di->si->cp.lock );
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return res;
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}
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// reset VIP
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static void VIPReset(
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void Radeon_VIPReset(
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device_info *di, bool lock )
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{
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vuint8 *regs = di->regs;
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@ -146,27 +288,43 @@ static void VIPReset(
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if( lock )
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ACQUIRE_BEN( di->si->cp.lock );
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Radeon_WaitForFifo( di, 5 );
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OUTREG( regs, RADEON_VIPH_CONTROL,
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4 |
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(15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
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RADEON_VIPH_CONTROL_VIPH_DMA_MODE |
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RADEON_VIPH_CONTROL_VIPH_EN );
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OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS,
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~RADEON_VIPH_TIMEOUT_STAT_AK_MASK & ~RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
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OUTREG( regs, RADEON_VIPH_DV_LAT,
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0xff |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT));
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OUTREG( regs, RADEON_VIPH_DMA_CHUNK,
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1 |
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(1 << RADEON_VIPH_DMA_CHUNK_VIPH_CH1_CHUNK_SHIFT) |
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(1 << RADEON_VIPH_DMA_CHUNK_VIPH_CH2_CHUNK_SHIFT) |
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(1 << RADEON_VIPH_DMA_CHUNK_VIPH_CH3_CHUNK_SHIFT));
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OUTREGP( regs, RADEON_TEST_DEBUG_CNTL, 0, ~RADEON_TEST_DEBUG_CNTL_OUT_EN );
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Radeon_WaitForFifo( di, 5 ); // Radeon_WaitForIdle( di, false, false );
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switch(di->asic){
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case rt_r200:
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case rt_rs200:
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case rt_rv200:
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case rt_rs100:
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case rt_rv100:
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case rt_r100:
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OUTREG( regs, RADEON_VIPH_CONTROL, 4 | (15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
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RADEON_VIPH_CONTROL_VIPH_DMA_MODE | RADEON_VIPH_CONTROL_VIPH_EN ); // slowest, timeout in 16 phases
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OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |
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RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
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OUTREG( regs, RADEON_VIPH_DV_LAT,
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0xff |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT)); // set timeslice
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OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x151);
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OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
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default:
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OUTREG( regs, RADEON_VIPH_CONTROL, 9 | (15 << RADEON_VIPH_CONTROL_VIPH_MAX_WAIT_SHIFT) |
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RADEON_VIPH_CONTROL_VIPH_DMA_MODE | RADEON_VIPH_CONTROL_VIPH_EN ); // slowest, timeout in 16 phases
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OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xFFFFFF00) |
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RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS);
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OUTREG( regs, RADEON_VIPH_DV_LAT,
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0xff |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV0_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV1_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV2_LAT_SHIFT) |
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(4 << RADEON_VIPH_DV_LAT_VIPH_DV3_LAT_SHIFT)); // set timeslice
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OUTREG( regs, RADEON_VIPH_DMA_CHUNK, 0x0);
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OUTREG( regs, RADEON_TEST_DEBUG_CNTL, INREG( regs, RADEON_TEST_DEBUG_CNTL) & (~RADEON_TEST_DEBUG_CNTL_OUT_EN));
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break;
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}
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if( lock )
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RELEASE_BEN( di->si->cp.lock );
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}
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@ -184,25 +342,30 @@ static status_t Radeon_VIPIdle(
|
||||
|
||||
// if there is a stuck transaction, acknowledge that
|
||||
timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT );
|
||||
if( (timeout & RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_STAT) != 0 ) {
|
||||
OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT,
|
||||
RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_AK,
|
||||
~RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_AK & ~RADEON_VIPH_TIMEOUT_STAT_AK_MASK );
|
||||
if( (INREG( regs, RADEON_VIPH_CONTROL) & RADEON_VIPH_CONTROL_VIPH_REG_RDY) != 0 )
|
||||
return B_BUSY;
|
||||
else
|
||||
return B_ERROR;
|
||||
if( (timeout & RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_STAT) != 0 )
|
||||
{
|
||||
OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT,
|
||||
(timeout & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REG_AK);
|
||||
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
|
||||
}
|
||||
|
||||
//Radeon_WaitForIdle( di, false, false );
|
||||
|
||||
if( (INREG( regs, RADEON_VIPH_CONTROL) & RADEON_VIPH_CONTROL_VIPH_REG_RDY) != 0 )
|
||||
return B_BUSY;
|
||||
else
|
||||
return B_OK;
|
||||
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK;
|
||||
}
|
||||
|
||||
static status_t RADEON_VIPFifoIdle(device_info *di, uint8 channel)
|
||||
{
|
||||
vuint8 *regs = di->regs;
|
||||
uint32 timeout;
|
||||
|
||||
timeout = INREG( regs, RADEON_VIPH_TIMEOUT_STAT);
|
||||
if((timeout & 0x0000000f) & channel) /* lockup ?? */
|
||||
{
|
||||
OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (timeout & 0xfffffff0) | channel);
|
||||
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_ERROR;
|
||||
}
|
||||
return (INREG( regs, RADEON_VIPH_CONTROL) & 0x2000) ? B_BUSY : B_OK ;
|
||||
}
|
||||
|
||||
|
||||
// wait until VIP host is idle
|
||||
// lock must be hold
|
||||
static bool Radeon_VIPWaitForIdle(
|
||||
@ -240,23 +403,28 @@ int Radeon_FindVIPDevice(
|
||||
|
||||
// if card has no VIP port, let hardware detection fail;
|
||||
// in this case, noone will bother us again
|
||||
if( !di->has_vip )
|
||||
if( !di->has_vip ) {
|
||||
SHOW_FLOW0( 3, "This Device has no VIP Bus.");
|
||||
return -1;
|
||||
|
||||
}
|
||||
|
||||
ACQUIRE_BEN( di->si->cp.lock );
|
||||
|
||||
VIPReset( di, false );
|
||||
Radeon_VIPReset( di, false );
|
||||
|
||||
// there are up to 4 devices, connected to one of 4 channels
|
||||
for( channel = 0; channel < 4; ++channel ) {
|
||||
|
||||
// read device id
|
||||
if( !Radeon_VIPRead( di, channel, RADEON_VIP_VENDOR_DEVICE_ID, &cur_device_id, false ))
|
||||
if( !Radeon_VIPRead( di, channel, RADEON_VIP_VENDOR_DEVICE_ID, &cur_device_id, false )) {
|
||||
SHOW_FLOW( 3, "No device found on channel %d", channel);
|
||||
continue;
|
||||
}
|
||||
|
||||
// compare device id directly
|
||||
if( cur_device_id == device_id ) {
|
||||
SHOW_FLOW( 3, "Device %08lx found on channel %d", device_id, channel);
|
||||
RELEASE_BEN( di->si->cp.lock );
|
||||
|
||||
return channel;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user