Adding ralinkwifi driver. This driver compiles, only, as there is a glue.c
is missing atm. If someone wanne add it go ahead. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34507 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Colin Günther
parent
afa6c0001b
commit
7bb39c3df3
@ -8,3 +8,4 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi2200 ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi3945 ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi4965 ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network wlan marvell88w8363 ;
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SubInclude HAIKU_TOP src add-ons kernel drivers network wlan ralinkwifi ;
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24
src/add-ons/kernel/drivers/network/wlan/ralinkwifi/Jamfile
Normal file
24
src/add-ons/kernel/drivers/network/wlan/ralinkwifi/Jamfile
Normal file
@ -0,0 +1,24 @@
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SubDir HAIKU_TOP src add-ons kernel drivers network wlan ralinkwifi ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
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UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_wlan ] : true ;
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UsePrivateHeaders net system ;
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UsePrivateKernelHeaders ;
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SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ]
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-Wno-format
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-Wno-unused
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-Wno-uninitialized ;
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UseHeaders [ FDirName $(SUBDIR) ] : true ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) dev ral ] ;
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KernelAddon ralinkwifi :
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if_ral_pci.c
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rt2560.c
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rt2661.c
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:
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libfreebsd_wlan.a
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libfreebsd_network.a
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;
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@ -0,0 +1,272 @@
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2005, 2006
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* Damien Bergamini <damien.bergamini@free.fr>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* PCI/Cardbus front-end for the Ralink RT2560/RT2561/RT2561S/RT2661 driver.
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*/
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#include <sys/param.h>
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#include <sys/sysctl.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <net/bpf.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <net80211/ieee80211_amrr.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ral/rt2560var.h>
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#include <dev/ral/rt2661var.h>
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MODULE_DEPEND(ral, pci, 1, 1, 1);
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MODULE_DEPEND(ral, firmware, 1, 1, 1);
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MODULE_DEPEND(ral, wlan, 1, 1, 1);
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MODULE_DEPEND(ral, wlan_amrr, 1, 1, 1);
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struct ral_pci_ident {
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uint16_t vendor;
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uint16_t device;
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const char *name;
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};
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static const struct ral_pci_ident ral_pci_ids[] = {
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{ 0x1814, 0x0201, "Ralink Technology RT2560" },
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{ 0x1814, 0x0301, "Ralink Technology RT2561S" },
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{ 0x1814, 0x0302, "Ralink Technology RT2561" },
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{ 0x1814, 0x0401, "Ralink Technology RT2661" },
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{ 0, 0, NULL }
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};
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static struct ral_opns {
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int (*attach)(device_t, int);
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int (*detach)(void *);
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void (*shutdown)(void *);
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void (*suspend)(void *);
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void (*resume)(void *);
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void (*intr)(void *);
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} ral_rt2560_opns = {
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rt2560_attach,
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rt2560_detach,
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rt2560_stop,
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rt2560_stop,
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rt2560_resume,
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rt2560_intr
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}, ral_rt2661_opns = {
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rt2661_attach,
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rt2661_detach,
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rt2661_shutdown,
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rt2661_suspend,
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rt2661_resume,
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rt2661_intr
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};
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struct ral_pci_softc {
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union {
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struct rt2560_softc sc_rt2560;
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struct rt2661_softc sc_rt2661;
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} u;
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struct ral_opns *sc_opns;
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int irq_rid;
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int mem_rid;
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struct resource *irq;
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struct resource *mem;
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void *sc_ih;
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};
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static int ral_pci_probe(device_t);
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static int ral_pci_attach(device_t);
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static int ral_pci_detach(device_t);
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static int ral_pci_shutdown(device_t);
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static int ral_pci_suspend(device_t);
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static int ral_pci_resume(device_t);
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static device_method_t ral_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ral_pci_probe),
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DEVMETHOD(device_attach, ral_pci_attach),
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DEVMETHOD(device_detach, ral_pci_detach),
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DEVMETHOD(device_shutdown, ral_pci_shutdown),
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DEVMETHOD(device_suspend, ral_pci_suspend),
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DEVMETHOD(device_resume, ral_pci_resume),
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{ 0, 0 }
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};
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static driver_t ral_pci_driver = {
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"ral",
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ral_pci_methods,
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sizeof (struct ral_pci_softc)
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};
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static devclass_t ral_devclass;
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DRIVER_MODULE(ral, pci, ral_pci_driver, ral_devclass, 0, 0);
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static int
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ral_pci_probe(device_t dev)
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{
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const struct ral_pci_ident *ident;
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for (ident = ral_pci_ids; ident->name != NULL; ident++) {
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if (pci_get_vendor(dev) == ident->vendor &&
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pci_get_device(dev) == ident->device) {
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device_set_desc(dev, ident->name);
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return 0;
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}
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}
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return ENXIO;
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}
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/* Base Address Register */
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#define RAL_PCI_BAR0 0x10
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static int
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ral_pci_attach(device_t dev)
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{
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struct ral_pci_softc *psc = device_get_softc(dev);
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struct rt2560_softc *sc = &psc->u.sc_rt2560;
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int error;
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if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
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device_printf(dev, "chip is in D%d power mode "
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"-- setting to D0\n", pci_get_powerstate(dev));
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pci_set_powerstate(dev, PCI_POWERSTATE_D0);
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}
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/* enable bus-mastering */
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pci_enable_busmaster(dev);
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psc->sc_opns = (pci_get_device(dev) == 0x0201) ? &ral_rt2560_opns :
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&ral_rt2661_opns;
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psc->mem_rid = RAL_PCI_BAR0;
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psc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &psc->mem_rid,
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RF_ACTIVE);
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if (psc->mem == NULL) {
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device_printf(dev, "could not allocate memory resource\n");
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return ENXIO;
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}
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sc->sc_st = rman_get_bustag(psc->mem);
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sc->sc_sh = rman_get_bushandle(psc->mem);
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sc->sc_invalid = 1;
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psc->irq_rid = 0;
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psc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &psc->irq_rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (psc->irq == NULL) {
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device_printf(dev, "could not allocate interrupt resource\n");
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return ENXIO;
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}
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error = (*psc->sc_opns->attach)(dev, pci_get_device(dev));
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if (error != 0)
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return error;
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/*
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* Hook our interrupt after all initialization is complete.
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*/
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error = bus_setup_intr(dev, psc->irq, INTR_TYPE_NET | INTR_MPSAFE,
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NULL, psc->sc_opns->intr, psc, &psc->sc_ih);
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if (error != 0) {
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device_printf(dev, "could not set up interrupt\n");
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return error;
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}
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sc->sc_invalid = 0;
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return 0;
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}
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static int
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ral_pci_detach(device_t dev)
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{
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struct ral_pci_softc *psc = device_get_softc(dev);
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struct rt2560_softc *sc = &psc->u.sc_rt2560;
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/* check if device was removed */
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sc->sc_invalid = !bus_child_present(dev);
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(*psc->sc_opns->detach)(psc);
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bus_generic_detach(dev);
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bus_teardown_intr(dev, psc->irq, psc->sc_ih);
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bus_release_resource(dev, SYS_RES_IRQ, psc->irq_rid, psc->irq);
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bus_release_resource(dev, SYS_RES_MEMORY, psc->mem_rid, psc->mem);
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return 0;
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}
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static int
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ral_pci_shutdown(device_t dev)
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{
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struct ral_pci_softc *psc = device_get_softc(dev);
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(*psc->sc_opns->shutdown)(psc);
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return 0;
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}
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static int
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ral_pci_suspend(device_t dev)
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{
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struct ral_pci_softc *psc = device_get_softc(dev);
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(*psc->sc_opns->suspend)(psc);
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return 0;
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}
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static int
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ral_pci_resume(device_t dev)
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{
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struct ral_pci_softc *psc = device_get_softc(dev);
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(*psc->sc_opns->resume)(psc);
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return 0;
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}
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2841
src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c
Normal file
2841
src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,489 @@
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/* $FreeBSD$ */
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/*-
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* Copyright (c) 2005, 2006
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* Damien Bergamini <damien.bergamini@free.fr>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#define RT2560_DEFAULT_RSSI_CORR 0x79
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#define RT2560_NOISE_FLOOR -95
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#define RT2560_TX_RING_COUNT 48
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#define RT2560_ATIM_RING_COUNT 4
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#define RT2560_PRIO_RING_COUNT 16
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#define RT2560_BEACON_RING_COUNT 1
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#define RT2560_RX_RING_COUNT 32
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#define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc))
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#define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc))
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#define RT2560_MAX_SCATTER 1
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/*
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* Control and status registers.
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*/
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#define RT2560_CSR0 0x0000 /* ASIC version number */
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#define RT2560_CSR1 0x0004 /* System control */
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#define RT2560_CSR3 0x000c /* STA MAC address 0 */
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#define RT2560_CSR4 0x0010 /* STA MAC address 1 */
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#define RT2560_CSR5 0x0014 /* BSSID 0 */
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#define RT2560_CSR6 0x0018 /* BSSID 1 */
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#define RT2560_CSR7 0x001c /* Interrupt source */
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#define RT2560_CSR8 0x0020 /* Interrupt mask */
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#define RT2560_CSR9 0x0024 /* Maximum frame length */
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#define RT2560_SECCSR0 0x0028 /* WEP control */
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#define RT2560_CSR11 0x002c /* Back-off control */
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#define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */
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#define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */
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#define RT2560_CSR14 0x0038 /* Synchronization control */
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#define RT2560_CSR15 0x003c /* Synchronization status */
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#define RT2560_CSR16 0x0040 /* TSF timer 0 */
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#define RT2560_CSR17 0x0044 /* TSF timer 1 */
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#define RT2560_CSR18 0x0048 /* IFS timer 0 */
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#define RT2560_CSR19 0x004c /* IFS timer 1 */
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#define RT2560_CSR20 0x0050 /* WAKEUP timer */
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#define RT2560_CSR21 0x0054 /* EEPROM control */
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#define RT2560_CSR22 0x0058 /* CFP control */
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#define RT2560_TXCSR0 0x0060 /* TX control */
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#define RT2560_TXCSR1 0x0064 /* TX configuration */
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#define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */
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#define RT2560_TXCSR3 0x006c /* TX ring base address */
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#define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */
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#define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */
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#define RT2560_TXCSR6 0x0078 /* Beacon base address */
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#define RT2560_TXCSR7 0x007c /* AutoResponder control */
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#define RT2560_RXCSR0 0x0080 /* RX control */
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#define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */
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#define RT2560_RXCSR2 0x0088 /* RX ring base address */
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#define RT2560_PCICSR 0x008c /* PCI control */
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#define RT2560_RXCSR3 0x0090 /* BBP ID 0 */
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#define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */
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#define RT2560_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */
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#define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */
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#define RT2560_CNT0 0x00a0 /* FCS error counter */
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#define RT2560_CNT1 0x00ac /* PLCP error counter */
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#define RT2560_CNT2 0x00b0 /* Long error counter */
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#define RT2560_CNT3 0x00b8 /* CCA false alarm counter */
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#define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */
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#define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */
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#define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */
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#define RT2560_PSCSR0 0x00c8 /* Power state transition time */
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#define RT2560_PSCSR1 0x00cc /* Power state transition time */
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#define RT2560_PSCSR2 0x00d0 /* Power state transition time */
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#define RT2560_PSCSR3 0x00d4 /* Power state transition time */
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#define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */
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#define RT2560_TIMECSR 0x00dc /* Timer control */
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#define RT2560_MACCSR0 0x00e0 /* MAC configuration */
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#define RT2560_MACCSR1 0x00e4 /* MAC configuration */
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#define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */
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#define RT2560_BCNCSR 0x00ec /* Beacon interval control */
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#define RT2560_BBPCSR 0x00f0 /* BBP serial control */
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#define RT2560_RFCSR 0x00f4 /* RF serial control */
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#define RT2560_LEDCSR 0x00f8 /* LED control */
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#define RT2560_SECCSR3 0x00fc /* XXX not documented */
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#define RT2560_DMACSR0 0x0100 /* Current RX ring address */
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#define RT2560_DMACSR1 0x0104 /* Current Tx ring address */
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#define RT2560_DMACSR2 0x0104 /* Current Priority ring address */
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#define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */
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#define RT2560_TXACKCSR0 0x0110 /* XXX not documented */
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#define RT2560_GPIOCSR 0x0120 /* */
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#define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */
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#define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */
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#define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */
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#define RT2560_BCNOCSR 0x0130 /* Beacon time offset */
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#define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */
|
||||
#define RT2560_TESTCSR 0x0138 /* Test Mode Select */
|
||||
#define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */
|
||||
#define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */
|
||||
#define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */
|
||||
#define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */
|
||||
#define RT2560_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */
|
||||
#define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time */
|
||||
#define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time */
|
||||
#define RT2560_SECCSR1 0x0158 /* WEP control */
|
||||
#define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */
|
||||
|
||||
|
||||
/* possible flags for register RXCSR0 */
|
||||
#define RT2560_DISABLE_RX (1 << 0)
|
||||
#define RT2560_DROP_CRC_ERROR (1 << 1)
|
||||
#define RT2560_DROP_PHY_ERROR (1 << 2)
|
||||
#define RT2560_DROP_CTL (1 << 3)
|
||||
#define RT2560_DROP_NOT_TO_ME (1 << 4)
|
||||
#define RT2560_DROP_TODS (1 << 5)
|
||||
#define RT2560_DROP_VERSION_ERROR (1 << 6)
|
||||
|
||||
/* possible flags for register CSR1 */
|
||||
#define RT2560_RESET_ASIC (1 << 0)
|
||||
#define RT2560_RESET_BBP (1 << 1)
|
||||
#define RT2560_HOST_READY (1 << 2)
|
||||
|
||||
/* possible flags for register CSR14 */
|
||||
#define RT2560_ENABLE_TSF (1 << 0)
|
||||
#define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1)
|
||||
#define RT2560_ENABLE_TBCN (1 << 3)
|
||||
#define RT2560_ENABLE_BEACON_GENERATOR (1 << 6)
|
||||
|
||||
/* possible flags for register CSR21 */
|
||||
#define RT2560_C (1 << 1)
|
||||
#define RT2560_S (1 << 2)
|
||||
#define RT2560_D (1 << 3)
|
||||
#define RT2560_Q (1 << 4)
|
||||
#define RT2560_93C46 (1 << 5)
|
||||
|
||||
#define RT2560_SHIFT_D 3
|
||||
#define RT2560_SHIFT_Q 4
|
||||
|
||||
/* possible flags for register TXCSR0 */
|
||||
#define RT2560_KICK_TX (1 << 0)
|
||||
#define RT2560_KICK_ATIM (1 << 1)
|
||||
#define RT2560_KICK_PRIO (1 << 2)
|
||||
#define RT2560_ABORT_TX (1 << 3)
|
||||
|
||||
/* possible flags for register SECCSR0 */
|
||||
#define RT2560_KICK_DECRYPT (1 << 0)
|
||||
|
||||
/* possible flags for register SECCSR1 */
|
||||
#define RT2560_KICK_ENCRYPT (1 << 0)
|
||||
|
||||
/* possible flags for register CSR7 */
|
||||
#define RT2560_BEACON_EXPIRE 0x00000001
|
||||
#define RT2560_WAKEUP_EXPIRE 0x00000002
|
||||
#define RT2560_ATIM_EXPIRE 0x00000004
|
||||
#define RT2560_TX_DONE 0x00000008
|
||||
#define RT2560_ATIM_DONE 0x00000010
|
||||
#define RT2560_PRIO_DONE 0x00000020
|
||||
#define RT2560_RX_DONE 0x00000040
|
||||
#define RT2560_DECRYPTION_DONE 0x00000080
|
||||
#define RT2560_ENCRYPTION_DONE 0x00000100
|
||||
|
||||
#define RT2560_INTR_MASK \
|
||||
(~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \
|
||||
RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \
|
||||
RT2560_ENCRYPTION_DONE))
|
||||
|
||||
/* Tx descriptor */
|
||||
struct rt2560_tx_desc {
|
||||
uint32_t flags;
|
||||
#define RT2560_TX_BUSY (1 << 0)
|
||||
#define RT2560_TX_VALID (1 << 1)
|
||||
|
||||
#define RT2560_TX_RESULT_MASK 0x0000001c
|
||||
#define RT2560_TX_SUCCESS (0 << 2)
|
||||
#define RT2560_TX_SUCCESS_RETRY (1 << 2)
|
||||
#define RT2560_TX_FAIL_RETRY (2 << 2)
|
||||
#define RT2560_TX_FAIL_INVALID (3 << 2)
|
||||
#define RT2560_TX_FAIL_OTHER (4 << 2)
|
||||
|
||||
#define RT2560_TX_MORE_FRAG (1 << 8)
|
||||
#define RT2560_TX_ACK (1 << 9)
|
||||
#define RT2560_TX_TIMESTAMP (1 << 10)
|
||||
#define RT2560_TX_OFDM (1 << 11)
|
||||
#define RT2560_TX_CIPHER_BUSY (1 << 12)
|
||||
|
||||
#define RT2560_TX_IFS_MASK 0x00006000
|
||||
#define RT2560_TX_IFS_BACKOFF (0 << 13)
|
||||
#define RT2560_TX_IFS_SIFS (1 << 13)
|
||||
#define RT2560_TX_IFS_NEWBACKOFF (2 << 13)
|
||||
#define RT2560_TX_IFS_NONE (3 << 13)
|
||||
|
||||
#define RT2560_TX_LONG_RETRY (1 << 15)
|
||||
|
||||
#define RT2560_TX_CIPHER_MASK 0xe0000000
|
||||
#define RT2560_TX_CIPHER_NONE (0 << 29)
|
||||
#define RT2560_TX_CIPHER_WEP40 (1 << 29)
|
||||
#define RT2560_TX_CIPHER_WEP104 (2 << 29)
|
||||
#define RT2560_TX_CIPHER_TKIP (3 << 29)
|
||||
#define RT2560_TX_CIPHER_AES (4 << 29)
|
||||
|
||||
#define RT2560_TX_RETRYCNT(v) (((v) >> 5) & 0x7)
|
||||
|
||||
uint32_t physaddr;
|
||||
uint16_t wme;
|
||||
#define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12)
|
||||
#define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8)
|
||||
#define RT2560_AIFSN(x) (((x) & 0x3) << 6)
|
||||
#define RT2560_IVOFFSET(x) (((x) & 0x3f))
|
||||
|
||||
uint16_t reserved1;
|
||||
uint8_t plcp_signal;
|
||||
uint8_t plcp_service;
|
||||
#define RT2560_PLCP_LENGEXT 0x80
|
||||
|
||||
uint8_t plcp_length_lo;
|
||||
uint8_t plcp_length_hi;
|
||||
uint32_t iv;
|
||||
uint32_t eiv;
|
||||
uint8_t key[IEEE80211_KEYBUF_SIZE];
|
||||
uint32_t reserved2[2];
|
||||
} __packed;
|
||||
|
||||
/* Rx descriptor */
|
||||
struct rt2560_rx_desc {
|
||||
uint32_t flags;
|
||||
#define RT2560_RX_BUSY (1 << 0)
|
||||
#define RT2560_RX_CRC_ERROR (1 << 5)
|
||||
#define RT2560_RX_OFDM (1 << 6)
|
||||
#define RT2560_RX_PHY_ERROR (1 << 7)
|
||||
#define RT2560_RX_CIPHER_BUSY (1 << 8)
|
||||
#define RT2560_RX_ICV_ERROR (1 << 9)
|
||||
|
||||
#define RT2560_RX_CIPHER_MASK 0xe0000000
|
||||
#define RT2560_RX_CIPHER_NONE (0 << 29)
|
||||
#define RT2560_RX_CIPHER_WEP40 (1 << 29)
|
||||
#define RT2560_RX_CIPHER_WEP104 (2 << 29)
|
||||
#define RT2560_RX_CIPHER_TKIP (3 << 29)
|
||||
#define RT2560_RX_CIPHER_AES (4 << 29)
|
||||
|
||||
uint32_t physaddr;
|
||||
uint8_t rate;
|
||||
uint8_t rssi;
|
||||
uint8_t ta[IEEE80211_ADDR_LEN];
|
||||
uint32_t iv;
|
||||
uint32_t eiv;
|
||||
uint8_t key[IEEE80211_KEYBUF_SIZE];
|
||||
uint32_t reserved[2];
|
||||
} __packed;
|
||||
|
||||
#define RAL_RF1 0
|
||||
#define RAL_RF2 2
|
||||
#define RAL_RF3 1
|
||||
#define RAL_RF4 3
|
||||
|
||||
#define RT2560_RF1_AUTOTUNE 0x08000
|
||||
#define RT2560_RF3_AUTOTUNE 0x00040
|
||||
|
||||
#define RT2560_BBP_BUSY (1 << 15)
|
||||
#define RT2560_BBP_WRITE (1 << 16)
|
||||
#define RT2560_RF_20BIT (20 << 24)
|
||||
#define RT2560_RF_BUSY (1 << 31)
|
||||
|
||||
#define RT2560_RF_2522 0x00
|
||||
#define RT2560_RF_2523 0x01
|
||||
#define RT2560_RF_2524 0x02
|
||||
#define RT2560_RF_2525 0x03
|
||||
#define RT2560_RF_2525E 0x04
|
||||
#define RT2560_RF_2526 0x05
|
||||
/* dual-band RF */
|
||||
#define RT2560_RF_5222 0x10
|
||||
|
||||
#define RT2560_BBP_VERSION 0
|
||||
#define RT2560_BBP_TX 2
|
||||
#define RT2560_BBP_RX 14
|
||||
|
||||
#define RT2560_BBP_ANTA 0x00
|
||||
#define RT2560_BBP_DIVERSITY 0x01
|
||||
#define RT2560_BBP_ANTB 0x02
|
||||
#define RT2560_BBP_ANTMASK 0x03
|
||||
#define RT2560_BBP_FLIPIQ 0x04
|
||||
|
||||
#define RT2560_LED_MODE_DEFAULT 0
|
||||
#define RT2560_LED_MODE_TXRX_ACTIVITY 1
|
||||
#define RT2560_LED_MODE_SINGLE 2
|
||||
#define RT2560_LED_MODE_ASUS 3
|
||||
|
||||
#define RT2560_JAPAN_FILTER 0x8
|
||||
|
||||
#define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
|
||||
|
||||
#define RT2560_EEPROM_CONFIG0 16
|
||||
#define RT2560_EEPROM_BBP_BASE 19
|
||||
#define RT2560_EEPROM_TXPOWER 35
|
||||
#define RT2560_EEPROM_CALIBRATE 62
|
||||
|
||||
/*
|
||||
* control and status registers access macros
|
||||
*/
|
||||
#define RAL_READ(sc, reg) \
|
||||
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
|
||||
|
||||
#define RAL_WRITE(sc, reg, val) \
|
||||
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
|
||||
|
||||
/*
|
||||
* EEPROM access macro
|
||||
*/
|
||||
#define RT2560_EEPROM_CTL(sc, val) do { \
|
||||
RAL_WRITE((sc), RT2560_CSR21, (val)); \
|
||||
DELAY(RT2560_EEPROM_DELAY); \
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
/*
|
||||
* Default values for MAC registers; values taken from the reference driver.
|
||||
*/
|
||||
#define RT2560_DEF_MAC \
|
||||
{ RT2560_PSCSR0, 0x00020002 }, \
|
||||
{ RT2560_PSCSR1, 0x00000002 }, \
|
||||
{ RT2560_PSCSR2, 0x00020002 }, \
|
||||
{ RT2560_PSCSR3, 0x00000002 }, \
|
||||
{ RT2560_TIMECSR, 0x00003f21 }, \
|
||||
{ RT2560_CSR9, 0x00000780 }, \
|
||||
{ RT2560_CSR11, 0x07041483 }, \
|
||||
{ RT2560_CNT3, 0x00000000 }, \
|
||||
{ RT2560_TXCSR1, 0x07614562 }, \
|
||||
{ RT2560_ARSP_PLCP_0, 0x8c8d8b8a }, \
|
||||
{ RT2560_ACKPCTCSR, 0x7038140a }, \
|
||||
{ RT2560_ARTCSR1, 0x21212929 }, \
|
||||
{ RT2560_ARTCSR2, 0x1d1d1d1d }, \
|
||||
{ RT2560_RXCSR0, 0xffffffff }, \
|
||||
{ RT2560_RXCSR3, 0xb3aab3af }, \
|
||||
{ RT2560_PCICSR, 0x000003b8 }, \
|
||||
{ RT2560_PWRCSR0, 0x3f3b3100 }, \
|
||||
{ RT2560_GPIOCSR, 0x0000ff00 }, \
|
||||
{ RT2560_TESTCSR, 0x000000f0 }, \
|
||||
{ RT2560_PWRCSR1, 0x000001ff }, \
|
||||
{ RT2560_MACCSR0, 0x00213223 }, \
|
||||
{ RT2560_MACCSR1, 0x00235518 }, \
|
||||
{ RT2560_RLPWCSR, 0x00000040 }, \
|
||||
{ RT2560_RALINKCSR, 0x9a009a11 }, \
|
||||
{ RT2560_CSR7, 0xffffffff }, \
|
||||
{ RT2560_BBPCSR1, 0x82188200 }, \
|
||||
{ RT2560_TXACKCSR0, 0x00000020 }, \
|
||||
{ RT2560_SECCSR3, 0x0000e78f }
|
||||
|
||||
/*
|
||||
* Default values for BBP registers; values taken from the reference driver.
|
||||
*/
|
||||
#define RT2560_DEF_BBP \
|
||||
{ 3, 0x02 }, \
|
||||
{ 4, 0x19 }, \
|
||||
{ 14, 0x1c }, \
|
||||
{ 15, 0x30 }, \
|
||||
{ 16, 0xac }, \
|
||||
{ 17, 0x48 }, \
|
||||
{ 18, 0x18 }, \
|
||||
{ 19, 0xff }, \
|
||||
{ 20, 0x1e }, \
|
||||
{ 21, 0x08 }, \
|
||||
{ 22, 0x08 }, \
|
||||
{ 23, 0x08 }, \
|
||||
{ 24, 0x80 }, \
|
||||
{ 25, 0x50 }, \
|
||||
{ 26, 0x08 }, \
|
||||
{ 27, 0x23 }, \
|
||||
{ 30, 0x10 }, \
|
||||
{ 31, 0x2b }, \
|
||||
{ 32, 0xb9 }, \
|
||||
{ 34, 0x12 }, \
|
||||
{ 35, 0x50 }, \
|
||||
{ 39, 0xc4 }, \
|
||||
{ 40, 0x02 }, \
|
||||
{ 41, 0x60 }, \
|
||||
{ 53, 0x10 }, \
|
||||
{ 54, 0x18 }, \
|
||||
{ 56, 0x08 }, \
|
||||
{ 57, 0x10 }, \
|
||||
{ 58, 0x08 }, \
|
||||
{ 61, 0x60 }, \
|
||||
{ 62, 0x10 }, \
|
||||
{ 75, 0xff }
|
||||
|
||||
/*
|
||||
* Default values for RF register R2 indexed by channel numbers; values taken
|
||||
* from the reference driver.
|
||||
*/
|
||||
#define RT2560_RF2522_R2 \
|
||||
{ \
|
||||
0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \
|
||||
0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \
|
||||
}
|
||||
|
||||
#define RT2560_RF2523_R2 \
|
||||
{ \
|
||||
0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
|
||||
0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
|
||||
}
|
||||
|
||||
#define RT2560_RF2524_R2 \
|
||||
{ \
|
||||
0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \
|
||||
0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \
|
||||
}
|
||||
|
||||
#define RT2560_RF2525_R2 \
|
||||
{ \
|
||||
0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \
|
||||
0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \
|
||||
}
|
||||
|
||||
#define RT2560_RF2525_HI_R2 \
|
||||
{ \
|
||||
0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \
|
||||
0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \
|
||||
}
|
||||
|
||||
#define RT2560_RF2525E_R2 \
|
||||
{ \
|
||||
0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \
|
||||
0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \
|
||||
}
|
||||
|
||||
#define RT2560_RF2526_HI_R2 \
|
||||
{ \
|
||||
0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \
|
||||
0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \
|
||||
}
|
||||
|
||||
#define RT2560_RF2526_R2 \
|
||||
{ \
|
||||
0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \
|
||||
0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \
|
||||
}
|
||||
|
||||
/*
|
||||
* For dual-band RF, RF registers R1 and R4 also depend on channel number;
|
||||
* values taken from the reference driver.
|
||||
*/
|
||||
#define RT2560_RF5222 \
|
||||
{ 1, 0x08808, 0x0044d, 0x00282 }, \
|
||||
{ 2, 0x08808, 0x0044e, 0x00282 }, \
|
||||
{ 3, 0x08808, 0x0044f, 0x00282 }, \
|
||||
{ 4, 0x08808, 0x00460, 0x00282 }, \
|
||||
{ 5, 0x08808, 0x00461, 0x00282 }, \
|
||||
{ 6, 0x08808, 0x00462, 0x00282 }, \
|
||||
{ 7, 0x08808, 0x00463, 0x00282 }, \
|
||||
{ 8, 0x08808, 0x00464, 0x00282 }, \
|
||||
{ 9, 0x08808, 0x00465, 0x00282 }, \
|
||||
{ 10, 0x08808, 0x00466, 0x00282 }, \
|
||||
{ 11, 0x08808, 0x00467, 0x00282 }, \
|
||||
{ 12, 0x08808, 0x00468, 0x00282 }, \
|
||||
{ 13, 0x08808, 0x00469, 0x00282 }, \
|
||||
{ 14, 0x08808, 0x0046b, 0x00286 }, \
|
||||
\
|
||||
{ 36, 0x08804, 0x06225, 0x00287 }, \
|
||||
{ 40, 0x08804, 0x06226, 0x00287 }, \
|
||||
{ 44, 0x08804, 0x06227, 0x00287 }, \
|
||||
{ 48, 0x08804, 0x06228, 0x00287 }, \
|
||||
{ 52, 0x08804, 0x06229, 0x00287 }, \
|
||||
{ 56, 0x08804, 0x0622a, 0x00287 }, \
|
||||
{ 60, 0x08804, 0x0622b, 0x00287 }, \
|
||||
{ 64, 0x08804, 0x0622c, 0x00287 }, \
|
||||
\
|
||||
{ 100, 0x08804, 0x02200, 0x00283 }, \
|
||||
{ 104, 0x08804, 0x02201, 0x00283 }, \
|
||||
{ 108, 0x08804, 0x02202, 0x00283 }, \
|
||||
{ 112, 0x08804, 0x02203, 0x00283 }, \
|
||||
{ 116, 0x08804, 0x02204, 0x00283 }, \
|
||||
{ 120, 0x08804, 0x02205, 0x00283 }, \
|
||||
{ 124, 0x08804, 0x02206, 0x00283 }, \
|
||||
{ 128, 0x08804, 0x02207, 0x00283 }, \
|
||||
{ 132, 0x08804, 0x02208, 0x00283 }, \
|
||||
{ 136, 0x08804, 0x02209, 0x00283 }, \
|
||||
{ 140, 0x08804, 0x0220a, 0x00283 }, \
|
||||
\
|
||||
{ 149, 0x08808, 0x02429, 0x00281 }, \
|
||||
{ 153, 0x08808, 0x0242b, 0x00281 }, \
|
||||
{ 157, 0x08808, 0x0242d, 0x00281 }, \
|
||||
{ 161, 0x08808, 0x0242f, 0x00281 }
|
||||
@ -0,0 +1,175 @@
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2005, 2006
|
||||
* Damien Bergamini <damien.bergamini@free.fr>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
struct rt2560_rx_radiotap_header {
|
||||
struct ieee80211_radiotap_header wr_ihdr;
|
||||
uint64_t wr_tsf;
|
||||
uint8_t wr_flags;
|
||||
uint8_t wr_rate;
|
||||
uint16_t wr_chan_freq;
|
||||
uint16_t wr_chan_flags;
|
||||
int8_t wr_antsignal;
|
||||
int8_t wr_antnoise;
|
||||
uint8_t wr_antenna;
|
||||
};
|
||||
|
||||
#define RT2560_RX_RADIOTAP_PRESENT \
|
||||
((1 << IEEE80211_RADIOTAP_TSFT) | \
|
||||
(1 << IEEE80211_RADIOTAP_FLAGS) | \
|
||||
(1 << IEEE80211_RADIOTAP_RATE) | \
|
||||
(1 << IEEE80211_RADIOTAP_CHANNEL) | \
|
||||
(1 << IEEE80211_RADIOTAP_ANTENNA) | \
|
||||
(1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
|
||||
(1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
|
||||
|
||||
struct rt2560_tx_radiotap_header {
|
||||
struct ieee80211_radiotap_header wt_ihdr;
|
||||
uint8_t wt_flags;
|
||||
uint8_t wt_rate;
|
||||
uint16_t wt_chan_freq;
|
||||
uint16_t wt_chan_flags;
|
||||
uint8_t wt_antenna;
|
||||
};
|
||||
|
||||
#define RT2560_TX_RADIOTAP_PRESENT \
|
||||
((1 << IEEE80211_RADIOTAP_FLAGS) | \
|
||||
(1 << IEEE80211_RADIOTAP_RATE) | \
|
||||
(1 << IEEE80211_RADIOTAP_CHANNEL) | \
|
||||
(1 << IEEE80211_RADIOTAP_ANTENNA))
|
||||
|
||||
struct rt2560_tx_data {
|
||||
bus_dmamap_t map;
|
||||
struct mbuf *m;
|
||||
struct ieee80211_node *ni;
|
||||
uint8_t rix;
|
||||
int8_t rssi;
|
||||
};
|
||||
|
||||
struct rt2560_tx_ring {
|
||||
bus_dma_tag_t desc_dmat;
|
||||
bus_dma_tag_t data_dmat;
|
||||
bus_dmamap_t desc_map;
|
||||
bus_addr_t physaddr;
|
||||
struct rt2560_tx_desc *desc;
|
||||
struct rt2560_tx_data *data;
|
||||
int count;
|
||||
int queued;
|
||||
int cur;
|
||||
int next;
|
||||
int cur_encrypt;
|
||||
int next_encrypt;
|
||||
};
|
||||
|
||||
struct rt2560_rx_data {
|
||||
bus_dmamap_t map;
|
||||
struct mbuf *m;
|
||||
int drop;
|
||||
};
|
||||
|
||||
struct rt2560_rx_ring {
|
||||
bus_dma_tag_t desc_dmat;
|
||||
bus_dma_tag_t data_dmat;
|
||||
bus_dmamap_t desc_map;
|
||||
bus_addr_t physaddr;
|
||||
struct rt2560_rx_desc *desc;
|
||||
struct rt2560_rx_data *data;
|
||||
int count;
|
||||
int cur;
|
||||
int next;
|
||||
int cur_decrypt;
|
||||
};
|
||||
|
||||
struct rt2560_node {
|
||||
struct ieee80211_node ni;
|
||||
struct ieee80211_amrr_node amrr;
|
||||
};
|
||||
#define RT2560_NODE(ni) ((struct rt2560_node *)(ni))
|
||||
|
||||
struct rt2560_vap {
|
||||
struct ieee80211vap ral_vap;
|
||||
struct ieee80211_beacon_offsets ral_bo;
|
||||
struct ieee80211_amrr amrr;
|
||||
|
||||
int (*ral_newstate)(struct ieee80211vap *,
|
||||
enum ieee80211_state, int);
|
||||
};
|
||||
#define RT2560_VAP(vap) ((struct rt2560_vap *)(vap))
|
||||
|
||||
struct rt2560_softc {
|
||||
struct ifnet *sc_ifp;
|
||||
device_t sc_dev;
|
||||
bus_space_tag_t sc_st;
|
||||
bus_space_handle_t sc_sh;
|
||||
|
||||
struct mtx sc_mtx;
|
||||
|
||||
struct callout watchdog_ch;
|
||||
|
||||
int sc_tx_timer;
|
||||
int sc_invalid;
|
||||
int sc_debug;
|
||||
/*
|
||||
* The same in both up to here
|
||||
* ------------------------------------------------
|
||||
*/
|
||||
uint32_t asic_rev;
|
||||
uint32_t eeprom_rev;
|
||||
uint8_t rf_rev;
|
||||
uint8_t rssi_corr;
|
||||
|
||||
struct rt2560_tx_ring txq;
|
||||
struct rt2560_tx_ring prioq;
|
||||
struct rt2560_tx_ring atimq;
|
||||
struct rt2560_tx_ring bcnq;
|
||||
struct rt2560_rx_ring rxq;
|
||||
|
||||
uint32_t rf_regs[4];
|
||||
uint8_t txpow[14];
|
||||
|
||||
struct {
|
||||
uint8_t reg;
|
||||
uint8_t val;
|
||||
} bbp_prom[16];
|
||||
|
||||
int led_mode;
|
||||
int hw_radio;
|
||||
int rx_ant;
|
||||
int tx_ant;
|
||||
int nb_ant;
|
||||
|
||||
struct rt2560_rx_radiotap_header sc_rxtap;
|
||||
int sc_rxtap_len;
|
||||
|
||||
struct rt2560_tx_radiotap_header sc_txtap;
|
||||
int sc_txtap_len;
|
||||
#define RT2560_F_INPUT_RUNNING 0x1
|
||||
#define RT2560_F_PRIO_OACTIVE 0x2
|
||||
#define RT2560_F_DATA_OACTIVE 0x4
|
||||
int sc_flags;
|
||||
};
|
||||
|
||||
int rt2560_attach(device_t, int);
|
||||
int rt2560_detach(void *);
|
||||
void rt2560_stop(void *);
|
||||
void rt2560_resume(void *);
|
||||
void rt2560_intr(void *);
|
||||
|
||||
#define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
|
||||
#define RAL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
|
||||
#define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
|
||||
2878
src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c
Normal file
2878
src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,488 @@
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2006
|
||||
* Damien Bergamini <damien.bergamini@free.fr>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#define RT2661_NOISE_FLOOR -95
|
||||
|
||||
#define RT2661_TX_RING_COUNT 32
|
||||
#define RT2661_MGT_RING_COUNT 32
|
||||
#define RT2661_RX_RING_COUNT 64
|
||||
|
||||
#define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc))
|
||||
#define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4)
|
||||
#define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc))
|
||||
#define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4)
|
||||
|
||||
#define RT2661_MAX_SCATTER 5
|
||||
|
||||
/*
|
||||
* Control and status registers.
|
||||
*/
|
||||
#define RT2661_HOST_CMD_CSR 0x0008
|
||||
#define RT2661_MCU_CNTL_CSR 0x000c
|
||||
#define RT2661_SOFT_RESET_CSR 0x0010
|
||||
#define RT2661_MCU_INT_SOURCE_CSR 0x0014
|
||||
#define RT2661_MCU_INT_MASK_CSR 0x0018
|
||||
#define RT2661_PCI_USEC_CSR 0x001c
|
||||
#define RT2661_H2M_MAILBOX_CSR 0x2100
|
||||
#define RT2661_M2H_CMD_DONE_CSR 0x2104
|
||||
#define RT2661_HW_BEACON_BASE0 0x2c00
|
||||
#define RT2661_MAC_CSR0 0x3000
|
||||
#define RT2661_MAC_CSR1 0x3004
|
||||
#define RT2661_MAC_CSR2 0x3008
|
||||
#define RT2661_MAC_CSR3 0x300c
|
||||
#define RT2661_MAC_CSR4 0x3010
|
||||
#define RT2661_MAC_CSR5 0x3014
|
||||
#define RT2661_MAC_CSR6 0x3018
|
||||
#define RT2661_MAC_CSR7 0x301c
|
||||
#define RT2661_MAC_CSR8 0x3020
|
||||
#define RT2661_MAC_CSR9 0x3024
|
||||
#define RT2661_MAC_CSR10 0x3028
|
||||
#define RT2661_MAC_CSR11 0x302c
|
||||
#define RT2661_MAC_CSR12 0x3030
|
||||
#define RT2661_MAC_CSR13 0x3034
|
||||
#define RT2661_MAC_CSR14 0x3038
|
||||
#define RT2661_MAC_CSR15 0x303c
|
||||
#define RT2661_TXRX_CSR0 0x3040
|
||||
#define RT2661_TXRX_CSR1 0x3044
|
||||
#define RT2661_TXRX_CSR2 0x3048
|
||||
#define RT2661_TXRX_CSR3 0x304c
|
||||
#define RT2661_TXRX_CSR4 0x3050
|
||||
#define RT2661_TXRX_CSR5 0x3054
|
||||
#define RT2661_TXRX_CSR6 0x3058
|
||||
#define RT2661_TXRX_CSR7 0x305c
|
||||
#define RT2661_TXRX_CSR8 0x3060
|
||||
#define RT2661_TXRX_CSR9 0x3064
|
||||
#define RT2661_TXRX_CSR10 0x3068
|
||||
#define RT2661_TXRX_CSR11 0x306c
|
||||
#define RT2661_TXRX_CSR12 0x3070
|
||||
#define RT2661_TXRX_CSR13 0x3074
|
||||
#define RT2661_TXRX_CSR14 0x3078
|
||||
#define RT2661_TXRX_CSR15 0x307c
|
||||
#define RT2661_PHY_CSR0 0x3080
|
||||
#define RT2661_PHY_CSR1 0x3084
|
||||
#define RT2661_PHY_CSR2 0x3088
|
||||
#define RT2661_PHY_CSR3 0x308c
|
||||
#define RT2661_PHY_CSR4 0x3090
|
||||
#define RT2661_PHY_CSR5 0x3094
|
||||
#define RT2661_PHY_CSR6 0x3098
|
||||
#define RT2661_PHY_CSR7 0x309c
|
||||
#define RT2661_SEC_CSR0 0x30a0
|
||||
#define RT2661_SEC_CSR1 0x30a4
|
||||
#define RT2661_SEC_CSR2 0x30a8
|
||||
#define RT2661_SEC_CSR3 0x30ac
|
||||
#define RT2661_SEC_CSR4 0x30b0
|
||||
#define RT2661_SEC_CSR5 0x30b4
|
||||
#define RT2661_STA_CSR0 0x30c0
|
||||
#define RT2661_STA_CSR1 0x30c4
|
||||
#define RT2661_STA_CSR2 0x30c8
|
||||
#define RT2661_STA_CSR3 0x30cc
|
||||
#define RT2661_STA_CSR4 0x30d0
|
||||
#define RT2661_AC0_BASE_CSR 0x3400
|
||||
#define RT2661_AC1_BASE_CSR 0x3404
|
||||
#define RT2661_AC2_BASE_CSR 0x3408
|
||||
#define RT2661_AC3_BASE_CSR 0x340c
|
||||
#define RT2661_MGT_BASE_CSR 0x3410
|
||||
#define RT2661_TX_RING_CSR0 0x3418
|
||||
#define RT2661_TX_RING_CSR1 0x341c
|
||||
#define RT2661_AIFSN_CSR 0x3420
|
||||
#define RT2661_CWMIN_CSR 0x3424
|
||||
#define RT2661_CWMAX_CSR 0x3428
|
||||
#define RT2661_TX_DMA_DST_CSR 0x342c
|
||||
#define RT2661_TX_CNTL_CSR 0x3430
|
||||
#define RT2661_LOAD_TX_RING_CSR 0x3434
|
||||
#define RT2661_RX_BASE_CSR 0x3450
|
||||
#define RT2661_RX_RING_CSR 0x3454
|
||||
#define RT2661_RX_CNTL_CSR 0x3458
|
||||
#define RT2661_PCI_CFG_CSR 0x3460
|
||||
#define RT2661_INT_SOURCE_CSR 0x3468
|
||||
#define RT2661_INT_MASK_CSR 0x346c
|
||||
#define RT2661_E2PROM_CSR 0x3470
|
||||
#define RT2661_AC_TXOP_CSR0 0x3474
|
||||
#define RT2661_AC_TXOP_CSR1 0x3478
|
||||
#define RT2661_TEST_MODE_CSR 0x3484
|
||||
#define RT2661_IO_CNTL_CSR 0x3498
|
||||
#define RT2661_MCU_CODE_BASE 0x4000
|
||||
|
||||
|
||||
/* possible flags for register HOST_CMD_CSR */
|
||||
#define RT2661_KICK_CMD (1 << 7)
|
||||
/* Host to MCU (8051) command identifiers */
|
||||
#define RT2661_MCU_CMD_SLEEP 0x30
|
||||
#define RT2661_MCU_CMD_WAKEUP 0x31
|
||||
#define RT2661_MCU_SET_LED 0x50
|
||||
#define RT2661_MCU_SET_RSSI_LED 0x52
|
||||
|
||||
/* possible flags for register MCU_CNTL_CSR */
|
||||
#define RT2661_MCU_SEL (1 << 0)
|
||||
#define RT2661_MCU_RESET (1 << 1)
|
||||
#define RT2661_MCU_READY (1 << 2)
|
||||
|
||||
/* possible flags for register MCU_INT_SOURCE_CSR */
|
||||
#define RT2661_MCU_CMD_DONE 0xff
|
||||
#define RT2661_MCU_WAKEUP (1 << 8)
|
||||
#define RT2661_MCU_BEACON_EXPIRE (1 << 9)
|
||||
|
||||
/* possible flags for register H2M_MAILBOX_CSR */
|
||||
#define RT2661_H2M_BUSY (1 << 24)
|
||||
#define RT2661_TOKEN_NO_INTR 0xff
|
||||
|
||||
/* possible flags for register MAC_CSR5 */
|
||||
#define RT2661_ONE_BSSID 3
|
||||
|
||||
/* possible flags for register TXRX_CSR0 */
|
||||
/* Tx filter flags are in the low 16 bits */
|
||||
#define RT2661_AUTO_TX_SEQ (1 << 15)
|
||||
/* Rx filter flags are in the high 16 bits */
|
||||
#define RT2661_DISABLE_RX (1 << 16)
|
||||
#define RT2661_DROP_CRC_ERROR (1 << 17)
|
||||
#define RT2661_DROP_PHY_ERROR (1 << 18)
|
||||
#define RT2661_DROP_CTL (1 << 19)
|
||||
#define RT2661_DROP_NOT_TO_ME (1 << 20)
|
||||
#define RT2661_DROP_TODS (1 << 21)
|
||||
#define RT2661_DROP_VER_ERROR (1 << 22)
|
||||
#define RT2661_DROP_MULTICAST (1 << 23)
|
||||
#define RT2661_DROP_BROADCAST (1 << 24)
|
||||
#define RT2661_DROP_ACKCTS (1 << 25)
|
||||
|
||||
/* possible flags for register TXRX_CSR4 */
|
||||
#define RT2661_SHORT_PREAMBLE (1 << 19)
|
||||
#define RT2661_MRR_ENABLED (1 << 20)
|
||||
#define RT2661_MRR_CCK_FALLBACK (1 << 23)
|
||||
|
||||
/* possible flags for register TXRX_CSR9 */
|
||||
#define RT2661_TSF_TICKING (1 << 16)
|
||||
#define RT2661_TSF_MODE(x) (((x) & 0x3) << 17)
|
||||
/* TBTT stands for Target Beacon Transmission Time */
|
||||
#define RT2661_ENABLE_TBTT (1 << 19)
|
||||
#define RT2661_GENERATE_BEACON (1 << 20)
|
||||
|
||||
/* possible flags for register PHY_CSR0 */
|
||||
#define RT2661_PA_PE_2GHZ (1 << 16)
|
||||
#define RT2661_PA_PE_5GHZ (1 << 17)
|
||||
|
||||
/* possible flags for register PHY_CSR3 */
|
||||
#define RT2661_BBP_READ (1 << 15)
|
||||
#define RT2661_BBP_BUSY (1 << 16)
|
||||
|
||||
/* possible flags for register PHY_CSR4 */
|
||||
#define RT2661_RF_21BIT (21 << 24)
|
||||
#define RT2661_RF_BUSY (1 << 31)
|
||||
|
||||
/* possible values for register STA_CSR4 */
|
||||
#define RT2661_TX_STAT_VALID (1 << 0)
|
||||
#define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7)
|
||||
#define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf)
|
||||
#define RT2661_TX_QID(v) (((v) >> 8) & 0xf)
|
||||
#define RT2661_TX_SUCCESS 0
|
||||
#define RT2661_TX_RETRY_FAIL 6
|
||||
|
||||
/* possible flags for register TX_CNTL_CSR */
|
||||
#define RT2661_KICK_MGT (1 << 4)
|
||||
|
||||
/* possible flags for register INT_SOURCE_CSR */
|
||||
#define RT2661_TX_DONE (1 << 0)
|
||||
#define RT2661_RX_DONE (1 << 1)
|
||||
#define RT2661_TX0_DMA_DONE (1 << 16)
|
||||
#define RT2661_TX1_DMA_DONE (1 << 17)
|
||||
#define RT2661_TX2_DMA_DONE (1 << 18)
|
||||
#define RT2661_TX3_DMA_DONE (1 << 19)
|
||||
#define RT2661_MGT_DONE (1 << 20)
|
||||
|
||||
/* possible flags for register E2PROM_CSR */
|
||||
#define RT2661_C (1 << 1)
|
||||
#define RT2661_S (1 << 2)
|
||||
#define RT2661_D (1 << 3)
|
||||
#define RT2661_Q (1 << 4)
|
||||
#define RT2661_93C46 (1 << 5)
|
||||
|
||||
/* Tx descriptor */
|
||||
struct rt2661_tx_desc {
|
||||
uint32_t flags;
|
||||
#define RT2661_TX_BUSY (1 << 0)
|
||||
#define RT2661_TX_VALID (1 << 1)
|
||||
#define RT2661_TX_MORE_FRAG (1 << 2)
|
||||
#define RT2661_TX_NEED_ACK (1 << 3)
|
||||
#define RT2661_TX_TIMESTAMP (1 << 4)
|
||||
#define RT2661_TX_OFDM (1 << 5)
|
||||
#define RT2661_TX_IFS (1 << 6)
|
||||
#define RT2661_TX_LONG_RETRY (1 << 7)
|
||||
#define RT2661_TX_BURST (1 << 28)
|
||||
|
||||
uint16_t wme;
|
||||
#define RT2661_QID(v) (v)
|
||||
#define RT2661_AIFSN(v) ((v) << 4)
|
||||
#define RT2661_LOGCWMIN(v) ((v) << 8)
|
||||
#define RT2661_LOGCWMAX(v) ((v) << 12)
|
||||
|
||||
uint16_t xflags;
|
||||
#define RT2661_TX_HWSEQ (1 << 12)
|
||||
|
||||
uint8_t plcp_signal;
|
||||
uint8_t plcp_service;
|
||||
#define RT2661_PLCP_LENGEXT 0x80
|
||||
|
||||
uint8_t plcp_length_lo;
|
||||
uint8_t plcp_length_hi;
|
||||
|
||||
uint32_t iv;
|
||||
uint32_t eiv;
|
||||
|
||||
uint8_t offset;
|
||||
uint8_t qid;
|
||||
#define RT2661_QID_MGT 13
|
||||
|
||||
uint8_t txpower;
|
||||
#define RT2661_DEFAULT_TXPOWER 0
|
||||
|
||||
uint8_t reserved1;
|
||||
|
||||
uint32_t addr[RT2661_MAX_SCATTER];
|
||||
uint16_t len[RT2661_MAX_SCATTER];
|
||||
|
||||
uint16_t reserved2;
|
||||
} __packed;
|
||||
|
||||
/* Rx descriptor */
|
||||
struct rt2661_rx_desc {
|
||||
uint32_t flags;
|
||||
#define RT2661_RX_BUSY (1 << 0)
|
||||
#define RT2661_RX_DROP (1 << 1)
|
||||
#define RT2661_RX_CRC_ERROR (1 << 6)
|
||||
#define RT2661_RX_OFDM (1 << 7)
|
||||
#define RT2661_RX_PHY_ERROR (1 << 8)
|
||||
#define RT2661_RX_CIPHER_MASK 0x00000600
|
||||
|
||||
uint8_t rate;
|
||||
uint8_t rssi;
|
||||
uint8_t reserved1;
|
||||
uint8_t offset;
|
||||
uint32_t iv;
|
||||
uint32_t eiv;
|
||||
uint32_t reserved2;
|
||||
uint32_t physaddr;
|
||||
uint32_t reserved3[10];
|
||||
} __packed;
|
||||
|
||||
#define RAL_RF1 0
|
||||
#define RAL_RF2 2
|
||||
#define RAL_RF3 1
|
||||
#define RAL_RF4 3
|
||||
|
||||
/* dual-band RF */
|
||||
#define RT2661_RF_5225 1
|
||||
#define RT2661_RF_5325 2
|
||||
/* single-band RF */
|
||||
#define RT2661_RF_2527 3
|
||||
#define RT2661_RF_2529 4
|
||||
|
||||
#define RT2661_RX_DESC_BACK 4
|
||||
|
||||
#define RT2661_SMART_MODE (1 << 0)
|
||||
|
||||
#define RT2661_BBPR94_DEFAULT 6
|
||||
|
||||
#define RT2661_SHIFT_D 3
|
||||
#define RT2661_SHIFT_Q 4
|
||||
|
||||
#define RT2661_EEPROM_MAC01 0x02
|
||||
#define RT2661_EEPROM_MAC23 0x03
|
||||
#define RT2661_EEPROM_MAC45 0x04
|
||||
#define RT2661_EEPROM_ANTENNA 0x10
|
||||
#define RT2661_EEPROM_CONFIG2 0x11
|
||||
#define RT2661_EEPROM_BBP_BASE 0x13
|
||||
#define RT2661_EEPROM_TXPOWER 0x23
|
||||
#define RT2661_EEPROM_FREQ_OFFSET 0x2f
|
||||
#define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d
|
||||
#define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e
|
||||
|
||||
#define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
|
||||
|
||||
/*
|
||||
* control and status registers access macros
|
||||
*/
|
||||
#define RAL_READ(sc, reg) \
|
||||
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
|
||||
|
||||
#define RAL_READ_REGION_4(sc, offset, datap, count) \
|
||||
bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
|
||||
(datap), (count))
|
||||
|
||||
#define RAL_WRITE(sc, reg, val) \
|
||||
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
|
||||
|
||||
#define RAL_WRITE_REGION_1(sc, offset, datap, count) \
|
||||
bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \
|
||||
(datap), (count))
|
||||
|
||||
/*
|
||||
* EEPROM access macro
|
||||
*/
|
||||
#define RT2661_EEPROM_CTL(sc, val) do { \
|
||||
RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \
|
||||
DELAY(RT2661_EEPROM_DELAY); \
|
||||
} while (/* CONSTCOND */0)
|
||||
|
||||
/*
|
||||
* Default values for MAC registers; values taken from the reference driver.
|
||||
*/
|
||||
#define RT2661_DEF_MAC \
|
||||
{ RT2661_TXRX_CSR0, 0x0000b032 }, \
|
||||
{ RT2661_TXRX_CSR1, 0x9eb39eb3 }, \
|
||||
{ RT2661_TXRX_CSR2, 0x8a8b8c8d }, \
|
||||
{ RT2661_TXRX_CSR3, 0x00858687 }, \
|
||||
{ RT2661_TXRX_CSR7, 0x2e31353b }, \
|
||||
{ RT2661_TXRX_CSR8, 0x2a2a2a2c }, \
|
||||
{ RT2661_TXRX_CSR15, 0x0000000f }, \
|
||||
{ RT2661_MAC_CSR6, 0x00000fff }, \
|
||||
{ RT2661_MAC_CSR8, 0x016c030a }, \
|
||||
{ RT2661_MAC_CSR10, 0x00000718 }, \
|
||||
{ RT2661_MAC_CSR12, 0x00000004 }, \
|
||||
{ RT2661_MAC_CSR13, 0x0000e000 }, \
|
||||
{ RT2661_SEC_CSR0, 0x00000000 }, \
|
||||
{ RT2661_SEC_CSR1, 0x00000000 }, \
|
||||
{ RT2661_SEC_CSR5, 0x00000000 }, \
|
||||
{ RT2661_PHY_CSR1, 0x000023b0 }, \
|
||||
{ RT2661_PHY_CSR5, 0x060a100c }, \
|
||||
{ RT2661_PHY_CSR6, 0x00080606 }, \
|
||||
{ RT2661_PHY_CSR7, 0x00000a08 }, \
|
||||
{ RT2661_PCI_CFG_CSR, 0x3cca4808 }, \
|
||||
{ RT2661_AIFSN_CSR, 0x00002273 }, \
|
||||
{ RT2661_CWMIN_CSR, 0x00002344 }, \
|
||||
{ RT2661_CWMAX_CSR, 0x000034aa }, \
|
||||
{ RT2661_TEST_MODE_CSR, 0x00000200 }, \
|
||||
{ RT2661_M2H_CMD_DONE_CSR, 0xffffffff }
|
||||
|
||||
/*
|
||||
* Default values for BBP registers; values taken from the reference driver.
|
||||
*/
|
||||
#define RT2661_DEF_BBP \
|
||||
{ 3, 0x00 }, \
|
||||
{ 15, 0x30 }, \
|
||||
{ 17, 0x20 }, \
|
||||
{ 21, 0xc8 }, \
|
||||
{ 22, 0x38 }, \
|
||||
{ 23, 0x06 }, \
|
||||
{ 24, 0xfe }, \
|
||||
{ 25, 0x0a }, \
|
||||
{ 26, 0x0d }, \
|
||||
{ 34, 0x12 }, \
|
||||
{ 37, 0x07 }, \
|
||||
{ 39, 0xf8 }, \
|
||||
{ 41, 0x60 }, \
|
||||
{ 53, 0x10 }, \
|
||||
{ 54, 0x18 }, \
|
||||
{ 60, 0x10 }, \
|
||||
{ 61, 0x04 }, \
|
||||
{ 62, 0x04 }, \
|
||||
{ 75, 0xfe }, \
|
||||
{ 86, 0xfe }, \
|
||||
{ 88, 0xfe }, \
|
||||
{ 90, 0x0f }, \
|
||||
{ 99, 0x00 }, \
|
||||
{ 102, 0x16 }, \
|
||||
{ 107, 0x04 }
|
||||
|
||||
/*
|
||||
* Default settings for RF registers; values taken from the reference driver.
|
||||
*/
|
||||
#define RT2661_RF5225_1 \
|
||||
{ 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
|
||||
{ 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
|
||||
{ 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
|
||||
{ 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
|
||||
{ 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
|
||||
{ 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
|
||||
{ 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
|
||||
{ 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
|
||||
{ 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
|
||||
{ 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
|
||||
{ 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
|
||||
{ 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
|
||||
{ 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
|
||||
{ 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
|
||||
\
|
||||
{ 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \
|
||||
{ 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \
|
||||
{ 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \
|
||||
{ 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \
|
||||
{ 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \
|
||||
{ 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \
|
||||
{ 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \
|
||||
{ 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \
|
||||
\
|
||||
{ 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \
|
||||
{ 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \
|
||||
{ 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \
|
||||
{ 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \
|
||||
{ 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \
|
||||
{ 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \
|
||||
{ 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \
|
||||
{ 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \
|
||||
{ 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \
|
||||
{ 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \
|
||||
{ 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \
|
||||
\
|
||||
{ 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \
|
||||
{ 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \
|
||||
{ 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \
|
||||
{ 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \
|
||||
{ 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
|
||||
|
||||
#define RT2661_RF5225_2 \
|
||||
{ 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \
|
||||
{ 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \
|
||||
{ 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \
|
||||
{ 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \
|
||||
{ 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \
|
||||
{ 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \
|
||||
{ 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \
|
||||
{ 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \
|
||||
{ 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \
|
||||
{ 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \
|
||||
{ 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \
|
||||
{ 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \
|
||||
{ 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \
|
||||
{ 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \
|
||||
\
|
||||
{ 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \
|
||||
{ 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \
|
||||
{ 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \
|
||||
{ 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \
|
||||
{ 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \
|
||||
{ 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \
|
||||
{ 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \
|
||||
{ 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \
|
||||
\
|
||||
{ 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \
|
||||
{ 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \
|
||||
{ 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \
|
||||
{ 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \
|
||||
{ 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \
|
||||
{ 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \
|
||||
{ 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \
|
||||
{ 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \
|
||||
{ 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \
|
||||
{ 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \
|
||||
{ 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \
|
||||
\
|
||||
{ 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \
|
||||
{ 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \
|
||||
{ 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \
|
||||
{ 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \
|
||||
{ 165, 0x00b35, 0x11246, 0x2e014, 0x30285 }
|
||||
@ -0,0 +1,180 @@
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2005
|
||||
* Damien Bergamini <damien.bergamini@free.fr>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
struct rt2661_rx_radiotap_header {
|
||||
struct ieee80211_radiotap_header wr_ihdr;
|
||||
uint64_t wr_tsf;
|
||||
uint8_t wr_flags;
|
||||
uint8_t wr_rate;
|
||||
uint16_t wr_chan_freq;
|
||||
uint16_t wr_chan_flags;
|
||||
int8_t wr_antsignal;
|
||||
int8_t wr_antnoise;
|
||||
} __packed;
|
||||
|
||||
#define RT2661_RX_RADIOTAP_PRESENT \
|
||||
((1 << IEEE80211_RADIOTAP_TSFT) | \
|
||||
(1 << IEEE80211_RADIOTAP_FLAGS) | \
|
||||
(1 << IEEE80211_RADIOTAP_RATE) | \
|
||||
(1 << IEEE80211_RADIOTAP_CHANNEL) | \
|
||||
(1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
|
||||
(1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
|
||||
|
||||
struct rt2661_tx_radiotap_header {
|
||||
struct ieee80211_radiotap_header wt_ihdr;
|
||||
uint8_t wt_flags;
|
||||
uint8_t wt_rate;
|
||||
uint16_t wt_chan_freq;
|
||||
uint16_t wt_chan_flags;
|
||||
} __packed;
|
||||
|
||||
#define RT2661_TX_RADIOTAP_PRESENT \
|
||||
((1 << IEEE80211_RADIOTAP_FLAGS) | \
|
||||
(1 << IEEE80211_RADIOTAP_RATE) | \
|
||||
(1 << IEEE80211_RADIOTAP_CHANNEL))
|
||||
|
||||
struct rt2661_tx_data {
|
||||
bus_dmamap_t map;
|
||||
struct mbuf *m;
|
||||
struct ieee80211_node *ni;
|
||||
uint8_t rix;
|
||||
int8_t rssi;
|
||||
};
|
||||
|
||||
struct rt2661_tx_ring {
|
||||
bus_dma_tag_t desc_dmat;
|
||||
bus_dma_tag_t data_dmat;
|
||||
bus_dmamap_t desc_map;
|
||||
bus_addr_t physaddr;
|
||||
struct rt2661_tx_desc *desc;
|
||||
struct rt2661_tx_data *data;
|
||||
int count;
|
||||
int queued;
|
||||
int cur;
|
||||
int next;
|
||||
int stat;
|
||||
};
|
||||
|
||||
struct rt2661_rx_data {
|
||||
bus_dmamap_t map;
|
||||
struct mbuf *m;
|
||||
};
|
||||
|
||||
struct rt2661_rx_ring {
|
||||
bus_dma_tag_t desc_dmat;
|
||||
bus_dma_tag_t data_dmat;
|
||||
bus_dmamap_t desc_map;
|
||||
bus_addr_t physaddr;
|
||||
struct rt2661_rx_desc *desc;
|
||||
struct rt2661_rx_data *data;
|
||||
int count;
|
||||
int cur;
|
||||
int next;
|
||||
};
|
||||
|
||||
struct rt2661_node {
|
||||
struct ieee80211_node ni;
|
||||
struct ieee80211_amrr_node amrr;
|
||||
};
|
||||
#define RT2661_NODE(ni) ((struct rt2661_node *)(ni))
|
||||
|
||||
struct rt2661_vap {
|
||||
struct ieee80211vap ral_vap;
|
||||
struct ieee80211_amrr amrr;
|
||||
|
||||
int (*ral_newstate)(struct ieee80211vap *,
|
||||
enum ieee80211_state, int);
|
||||
};
|
||||
#define RT2661_VAP(vap) ((struct rt2661_vap *)(vap))
|
||||
|
||||
struct rt2661_softc {
|
||||
struct ifnet *sc_ifp;
|
||||
device_t sc_dev;
|
||||
bus_space_tag_t sc_st;
|
||||
bus_space_handle_t sc_sh;
|
||||
|
||||
struct mtx sc_mtx;
|
||||
|
||||
struct callout watchdog_ch;
|
||||
|
||||
int sc_tx_timer;
|
||||
int sc_invalid;
|
||||
int sc_debug;
|
||||
/*
|
||||
* The same in both up to here
|
||||
* ------------------------------------------------
|
||||
*/
|
||||
|
||||
int sc_flags;
|
||||
#define RAL_FW_LOADED 0x1
|
||||
#define RAL_INPUT_RUNNING 0x2
|
||||
int sc_id;
|
||||
struct ieee80211_channel *sc_curchan;
|
||||
|
||||
uint8_t rf_rev;
|
||||
|
||||
uint8_t rfprog;
|
||||
uint8_t rffreq;
|
||||
|
||||
struct rt2661_tx_ring txq[4];
|
||||
struct rt2661_tx_ring mgtq;
|
||||
struct rt2661_rx_ring rxq;
|
||||
|
||||
uint32_t rf_regs[4];
|
||||
int8_t txpow[38];
|
||||
|
||||
struct {
|
||||
uint8_t reg;
|
||||
uint8_t val;
|
||||
} bbp_prom[16];
|
||||
|
||||
int hw_radio;
|
||||
int rx_ant;
|
||||
int tx_ant;
|
||||
int nb_ant;
|
||||
int ext_2ghz_lna;
|
||||
int ext_5ghz_lna;
|
||||
int rssi_2ghz_corr;
|
||||
int rssi_5ghz_corr;
|
||||
|
||||
uint8_t bbp18;
|
||||
uint8_t bbp21;
|
||||
uint8_t bbp22;
|
||||
uint8_t bbp16;
|
||||
uint8_t bbp17;
|
||||
uint8_t bbp64;
|
||||
|
||||
int dwelltime;
|
||||
|
||||
struct rt2661_rx_radiotap_header sc_rxtap;
|
||||
int sc_rxtap_len;
|
||||
struct rt2661_tx_radiotap_header sc_txtap;
|
||||
int sc_txtap_len;
|
||||
};
|
||||
|
||||
int rt2661_attach(device_t, int);
|
||||
int rt2661_detach(void *);
|
||||
void rt2661_shutdown(void *);
|
||||
void rt2661_suspend(void *);
|
||||
void rt2661_resume(void *);
|
||||
void rt2661_intr(void *);
|
||||
|
||||
#define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
|
||||
#define RAL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
|
||||
#define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
|
||||
Loading…
Reference in New Issue
Block a user