Now you can also select the refresh rate you like under R5. Looks like there is
room for improvements left in our screen preferences application, which ignores the pixel clock values completely. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16876 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -356,9 +356,9 @@ intel_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high)
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// lower limit of about 48Hz vertical refresh
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uint32 totalClocks = (uint32)mode->timing.h_total * (uint32)mode->timing.v_total;
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uint32 low = (totalClocks * 48L) / 1000L;
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if (low < gInfo->shared_info->pll_info.max_frequency)
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low = gInfo->shared_info->pll_info.max_frequency;
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else if (low > gInfo->shared_info->pll_info.max_frequency)
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if (low < gInfo->shared_info->pll_info.min_frequency)
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low = gInfo->shared_info->pll_info.min_frequency;
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else if (low > gInfo->shared_info->pll_info.max_frequency)
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return B_ERROR;
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*_low = low;
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@ -175,7 +175,7 @@ if (file >= 0) {
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info.shared_info->graphics_memory_size = memorySize;
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info.shared_info->dpms_mode = B_DPMS_ON;
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info.shared_info->pll_info.reference_frequency = 48000; // 48 kHz
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info.shared_info->pll_info.min_frequency = 100000; // 100 MHz (not tested)
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info.shared_info->pll_info.min_frequency = 25000; // 25 MHz (not tested)
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info.shared_info->pll_info.max_frequency = 350000; // 350 MHz RAM DAC speed
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info.shared_info->pll_info.divisor_register = INTEL_DISPLAY_PLL_DIVISOR_0;
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