* The save_lvds_mode() function did not correctly support the i965 chipset -
I've now removed that code, and factored out a retrieve_current_mode() function that can work on head A and B. * This fixes Adrien's flickering problem on his laptop - I can't find the bug ticket, though. Hopefully it does not break other laptop chips. Testing would be welcome, as I don't have any other machine here. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33633 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
4740a17020
commit
795bd7a697
@ -353,6 +353,7 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_B_PLL 0x06018
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#define INTEL_DISPLAY_B_PLL_MULTIPLIER_DIVISOR 0x06020
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#define INTEL_DISPLAY_B_PLL_DIVISOR_0 0x06048
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#define INTEL_DISPLAY_B_PLL_DIVISOR_1 0x0604c
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// LVDS panel
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#define INTEL_PANEL_STATUS 0x61200
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@ -333,17 +333,42 @@ compute_pll_divisors(const display_mode ¤t, pll_divisors& divisors,
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}
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/*! Store away panel information if identified on startup
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(used for pipe B->lvds).
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*/
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void
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save_lvds_mode(void)
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retrieve_current_mode(display_mode& mode, uint32 pllRegister)
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{
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// dump currently programmed mode.
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display_mode biosMode;
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uint32 pll = read32(pllRegister);
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uint32 pllDivisor;
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uint32 hTotalRegister;
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uint32 vTotalRegister;
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uint32 hSyncRegister;
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uint32 vSyncRegister;
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uint32 imageSizeRegister;
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uint32 controlRegister;
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uint32 pll = read32(INTEL_DISPLAY_B_PLL);
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uint32 pllDivisor = read32(INTEL_DISPLAY_B_PLL_DIVISOR_0);
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if (pllRegister == INTEL_DISPLAY_A_PLL) {
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pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0
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? INTEL_DISPLAY_A_PLL_DIVISOR_1 : INTEL_DISPLAY_A_PLL_DIVISOR_0);
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hTotalRegister = INTEL_DISPLAY_A_HTOTAL;
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vTotalRegister = INTEL_DISPLAY_A_VTOTAL;
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hSyncRegister = INTEL_DISPLAY_A_HSYNC;
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vSyncRegister = INTEL_DISPLAY_A_VSYNC;
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imageSizeRegister = INTEL_DISPLAY_A_IMAGE_SIZE;
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controlRegister = INTEL_DISPLAY_A_CONTROL;
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} else if (pllRegister == INTEL_DISPLAY_B_PLL) {
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pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0
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? INTEL_DISPLAY_B_PLL_DIVISOR_1 : INTEL_DISPLAY_B_PLL_DIVISOR_0);
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hTotalRegister = INTEL_DISPLAY_B_HTOTAL;
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vTotalRegister = INTEL_DISPLAY_B_VTOTAL;
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hSyncRegister = INTEL_DISPLAY_B_HSYNC;
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vSyncRegister = INTEL_DISPLAY_B_VSYNC;
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imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE;
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controlRegister = INTEL_DISPLAY_B_CONTROL;
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} else {
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// TODO: not supported
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return;
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}
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pll_divisors divisors;
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divisors.m1 = (pllDivisor & DISPLAY_PLL_M1_DIVISOR_MASK)
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@ -364,9 +389,6 @@ save_lvds_mode(void)
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divisors.post2 = limits.max.post2;
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else
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divisors.post2 = limits.min.post2;
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// Fix this? Need to support dual channel LVDS.
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divisors.post2 = LVDS_POST2_RATE_SLOW;
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} else {
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// 8xx
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divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK)
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@ -381,66 +403,71 @@ save_lvds_mode(void)
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divisors.m = 5 * divisors.m1 + divisors.m2;
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divisors.post = divisors.post1 * divisors.post2;
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float referenceClock = gInfo->shared_info->pll_info.reference_frequency
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/ 1000.0f;
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float pixelClock = ((referenceClock * divisors.m) / divisors.n)
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/ divisors.post;
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float referenceClock
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= gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
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float pixelClock
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= ((referenceClock * divisors.m) / divisors.n) / divisors.post;
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// timing
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biosMode.timing.pixel_clock = uint32(pixelClock * 1000);
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biosMode.timing.flags = 0;
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mode.timing.pixel_clock = uint32(pixelClock * 1000);
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mode.timing.flags = 0;
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uint32 value = read32(INTEL_DISPLAY_B_HTOTAL);
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biosMode.timing.h_total = (value >> 16) + 1;
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biosMode.timing.h_display = (value & 0xffff) + 1;
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uint32 value = read32(hTotalRegister);
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mode.timing.h_total = (value >> 16) + 1;
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mode.timing.h_display = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_B_HSYNC);
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biosMode.timing.h_sync_end = (value >> 16) + 1;
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biosMode.timing.h_sync_start = (value & 0xffff) + 1;
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value = read32(hSyncRegister);
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mode.timing.h_sync_end = (value >> 16) + 1;
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mode.timing.h_sync_start = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_B_VTOTAL);
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biosMode.timing.v_total = (value >> 16) + 1;
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biosMode.timing.v_display = (value & 0xffff) + 1;
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value = read32(vTotalRegister);
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mode.timing.v_total = (value >> 16) + 1;
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mode.timing.v_display = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_B_VSYNC);
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biosMode.timing.v_sync_end = (value >> 16) + 1;
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biosMode.timing.v_sync_start = (value & 0xffff) + 1;
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value = read32(vSyncRegister);
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mode.timing.v_sync_end = (value >> 16) + 1;
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mode.timing.v_sync_start = (value & 0xffff) + 1;
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// image size and color space
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// using virtual size based on image size is the 'proper' way to do it, however the bios appears to be
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// suggesting scaling or somesuch, so ignore the proper virtual way for now.
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value = read32(imageSizeRegister);
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mode.virtual_width = (value >> 16) + 1;
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mode.virtual_height = (value & 0xffff) + 1;
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biosMode.virtual_width = biosMode.timing.h_display;
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biosMode.virtual_height = biosMode.timing.v_display;
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//value = read32(INTEL_DISPLAY_B_IMAGE_SIZE);
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//biosMode.virtual_width = (value >> 16) + 1;
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//biosMode.virtual_height = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_B_CONTROL);
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value = read32(controlRegister);
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switch (value & DISPLAY_CONTROL_COLOR_MASK) {
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case DISPLAY_CONTROL_RGB32:
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default:
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biosMode.space = B_RGB32;
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mode.space = B_RGB32;
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break;
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case DISPLAY_CONTROL_RGB16:
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biosMode.space = B_RGB16;
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mode.space = B_RGB16;
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break;
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case DISPLAY_CONTROL_RGB15:
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biosMode.space = B_RGB15;
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mode.space = B_RGB15;
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break;
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case DISPLAY_CONTROL_CMAP8:
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biosMode.space = B_CMAP8;
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mode.space = B_CMAP8;
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break;
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}
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biosMode.h_display_start = 0;
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biosMode.v_display_start = 0;
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biosMode.flags = B_8_BIT_DAC | B_HARDWARE_CURSOR | B_PARALLEL_ACCESS
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mode.h_display_start = 0;
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mode.v_display_start = 0;
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mode.flags = B_8_BIT_DAC | B_HARDWARE_CURSOR | B_PARALLEL_ACCESS
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| B_DPMS | B_SUPPORTS_OVERLAYS;
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}
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/*! Store away panel information if identified on startup
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(used for pipe B->lvds).
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*/
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void
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save_lvds_mode(void)
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{
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// dump currently programmed mode.
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display_mode biosMode;
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retrieve_current_mode(biosMode, INTEL_DISPLAY_B_PLL);
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gInfo->lvds_panel_mode = biosMode;
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}
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@ -825,101 +852,10 @@ intel_get_display_mode(display_mode *_currentMode)
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{
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TRACE(("intel_get_display_mode()\n"));
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display_mode &mode = *_currentMode;
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uint32 pll = read32(INTEL_DISPLAY_A_PLL);
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uint32 pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0
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? INTEL_DISPLAY_A_PLL_DIVISOR_1 : INTEL_DISPLAY_A_PLL_DIVISOR_0);
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pll_divisors divisors;
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divisors.m1 = (pllDivisor & DISPLAY_PLL_M1_DIVISOR_MASK)
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>> DISPLAY_PLL_M1_DIVISOR_SHIFT;
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divisors.m2 = (pllDivisor & DISPLAY_PLL_M2_DIVISOR_MASK)
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>> DISPLAY_PLL_M2_DIVISOR_SHIFT;
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divisors.n = (pllDivisor & DISPLAY_PLL_N_DIVISOR_MASK)
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>> DISPLAY_PLL_N_DIVISOR_SHIFT;
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pll_limits limits;
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get_pll_limits(limits);
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if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
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divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
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>> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
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if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0)
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divisors.post2 = limits.max.post2;
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else
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divisors.post2 = limits.min.post2;
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} else {
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// 8xx
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divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK)
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>> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
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if ((pll & DISPLAY_PLL_DIVIDE_4X) != 0)
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divisors.post2 = limits.max.post2;
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else
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divisors.post2 = limits.min.post2;
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}
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divisors.m = 5 * divisors.m1 + divisors.m2;
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divisors.post = divisors.post1 * divisors.post2;
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float referenceClock
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= gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
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float pixelClock
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= ((referenceClock * divisors.m) / divisors.n) / divisors.post;
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// timing
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mode.timing.pixel_clock = uint32(pixelClock * 1000);
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mode.timing.flags = 0;
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uint32 value = read32(INTEL_DISPLAY_A_HTOTAL);
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mode.timing.h_total = (value >> 16) + 1;
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mode.timing.h_display = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_A_HSYNC);
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mode.timing.h_sync_end = (value >> 16) + 1;
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mode.timing.h_sync_start = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_A_VTOTAL);
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mode.timing.v_total = (value >> 16) + 1;
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mode.timing.v_display = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_A_VSYNC);
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mode.timing.v_sync_end = (value >> 16) + 1;
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mode.timing.v_sync_start = (value & 0xffff) + 1;
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// image size and color space
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value = read32(INTEL_DISPLAY_A_IMAGE_SIZE);
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mode.virtual_width = (value >> 16) + 1;
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mode.virtual_height = (value & 0xffff) + 1;
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value = read32(INTEL_DISPLAY_A_CONTROL);
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switch (value & DISPLAY_CONTROL_COLOR_MASK) {
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case DISPLAY_CONTROL_RGB32:
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default:
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mode.space = B_RGB32;
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break;
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case DISPLAY_CONTROL_RGB16:
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mode.space = B_RGB16;
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break;
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case DISPLAY_CONTROL_RGB15:
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mode.space = B_RGB15;
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break;
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case DISPLAY_CONTROL_CMAP8:
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mode.space = B_CMAP8;
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break;
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}
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mode.h_display_start = 0;
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mode.v_display_start = 0;
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mode.flags = 0;
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retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL);
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return B_OK;
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}
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#ifdef __HAIKU__
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status_t
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intel_get_edid_info(void* info, size_t size, uint32* _version)
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@ -936,7 +872,6 @@ intel_get_edid_info(void* info, size_t size, uint32* _version)
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return B_OK;
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}
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#endif // __HAIKU__
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status_t
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intel_get_frame_buffer_config(frame_buffer_config *config)
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