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* Overlay on the G33 does not work anymore in the secondary ring buffer;

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we now always only use the primary ring buffer.
* Removed secondary ring buffer allocation and member fields.
* Increased size of the primary ring buffer to 65536 bytes.
* The bytes per row register is computed differently for 9xx chips.
* On G33, the overlay does not need a physical address anymore, so we
  don't pass B_APERTURE_NEED_PHYSICAL to the allocation anymore for that
  device.
* intel_free_memory() accidently added the aperture base to the allocation
  and would therefore never free any memory.
* INTEL_RING_BUFFER_SIZE_MASK was shifted one bit to the right, didn't
  cause any harm with our buffer sizes, yet, though.
* With these changes, the driver runs stable on a G33 chipset (I have not
  yet tested the hardware cursor, though, it might need some work, too).
  The only known issue left is that overlay flickers a bit if its buffer
  is partially backed up by reserved and allocated memory.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23798 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler 2008-01-31 18:28:48 +00:00
parent d23e60e77b
commit 78fa3affbc
4 changed files with 34 additions and 29 deletions
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3
headers/private/graphics/intel_extreme/intel_extreme.h
View File

@ -76,7 +76,6 @@ struct intel_shared_info {
struct lock engine_lock;
ring_buffer primary_ring_buffer;
ring_buffer secondary_ring_buffer;
int32 overlay_channel_used;
bool overlay_active;
@ -200,7 +199,7 @@ struct intel_free_graphics_memory {
#define RING_BUFFER_HEAD 0x4
#define RING_BUFFER_START 0x8
#define RING_BUFFER_CONTROL 0xc
#define INTEL_RING_BUFFER_SIZE_MASK 0x000ff800
#define INTEL_RING_BUFFER_SIZE_MASK 0x001ff000
#define INTEL_RING_BUFFER_HEAD_MASK 0x001ffffc
#define INTEL_RING_BUFFER_ENABLED 1

2
src/add-ons/accelerants/intel_extreme/accelerant.cpp
View File

@ -190,7 +190,6 @@ intel_init_accelerant(int device)
init_lock(&info.engine_lock, "intel extreme engine");
setup_ring_buffer(info.primary_ring_buffer, "intel primary ring buffer");
setup_ring_buffer(info.secondary_ring_buffer, "intel secondary ring buffer");
// determine head depending on what's already enabled from the BIOS
// TODO: it would be nicer to retrieve this data via DDC - else the
@ -291,7 +290,6 @@ intel_uninit_accelerant(void)
uninit_lock(&info.engine_lock);
uninit_ring_buffer(info.primary_ring_buffer);
uninit_ring_buffer(info.secondary_ring_buffer);
uninit_common();
}

38
src/add-ons/accelerants/intel_extreme/overlay.cpp
View File

@ -229,7 +229,7 @@ update_overlay(bool updateCoefficients)
|| gInfo->shared_info->device_type == INTEL_TYPE_965)
return;
QueueCommands queue(gInfo->shared_info->secondary_ring_buffer);
QueueCommands queue(gInfo->shared_info->primary_ring_buffer);
queue.PutFlush();
queue.PutWaitFor(COMMAND_WAIT_FOR_OVERLAY_FLIP);
queue.PutOverlayFlip(COMMAND_OVERLAY_CONTINUE, updateCoefficients);
@ -238,9 +238,9 @@ update_overlay(bool updateCoefficients)
queue.PutWaitFor(COMMAND_WAIT_FOR_OVERLAY_FLIP);
queue.PutFlush();
// TRACE(("update overlay: UPDATE: %lx, TEST: %lx, STATUS: %lx, EXTENDED_STATUS: %lx\n",
// read32(INTEL_OVERLAY_UPDATE), read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS),
// read32(INTEL_OVERLAY_EXTENDED_STATUS)));
TRACE(("update overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), ERR: %lx\n",
read32(INTEL_OVERLAY_UPDATE), read32(INtEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS),
*(((uint32 *)gInfo->overlay_registers) + 0x68/4), read32(0x30168), read32(0x2024)));
}
@ -254,9 +254,13 @@ show_overlay(void)
gInfo->shared_info->overlay_active = true;
gInfo->overlay_registers->overlay_enabled = true;
QueueCommands queue(gInfo->shared_info->secondary_ring_buffer);
QueueCommands queue(gInfo->shared_info->primary_ring_buffer);
queue.PutOverlayFlip(COMMAND_OVERLAY_ON, true);
queue.PutFlush();
TRACE(("show overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), ERR: %lx\n",
read32(INTEL_OVERLAY_UPDATE), read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS),
*(((uint32 *)gInfo->overlay_registers) + 0x68/4), read32(0x30168), read32(0x2024)));
}
@ -272,7 +276,7 @@ hide_overlay(void)
gInfo->shared_info->overlay_active = false;
registers->overlay_enabled = false;
QueueCommands queue(gInfo->shared_info->secondary_ring_buffer);
QueueCommands queue(gInfo->shared_info->primary_ring_buffer);
// flush pending commands
queue.PutFlush();
@ -297,6 +301,7 @@ uint32
intel_overlay_count(const display_mode *mode)
{
// TODO: make this depending on the amount of RAM and the screen mode
// (and we could even have more than one when using 3D as well)
return 1;
}
@ -360,12 +365,16 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
// TODO: locking!
// alloc graphics mem
overlay_buffer *buffer = &overlay->buffer;
int32 alignment = 0x3f;
if (sharedInfo.device_type == INTEL_TYPE_965)
alignment = 0xff;
overlay_buffer *buffer = &overlay->buffer;
buffer->space = colorSpace;
buffer->width = width;
buffer->height = height;
buffer->bytes_per_row = (width * bytesPerPixel + 0x3f) & ~0x3f;
buffer->bytes_per_row = (width * bytesPerPixel + alignment) & ~alignment;
status_t status = intel_allocate_memory(buffer->bytes_per_row * height,
0, overlay->buffer_base);
@ -394,8 +403,8 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
buffer->buffer_dma = (uint8 *)gInfo->shared_info->physical_graphics_memory
+ overlay->buffer_offset;
TRACE(("allocated overlay buffer: handle=%x, offset=%x, address=%x, "
"physical address=%x\n", overlay->buffer_handle, overlay->buffer_offset,
TRACE(("allocated overlay buffer: base=%x, offset=%x, address=%x, "
"physical address=%x\n", overlay->buffer_base, overlay->buffer_offset,
buffer->buffer, buffer->buffer_dma));
return buffer;
@ -604,8 +613,13 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
// result will be wrong, too.
registers->source_width_rgb = right - left;
registers->source_height_rgb = bottom - top;
registers->source_bytes_per_row_rgb = (((overlay->buffer_offset + (view->width << 1)
+ 0x1f) >> 5) - (overlay->buffer_offset >> 5) - 1) << 2;
if ((gInfo->shared_info->device_type & INTEL_TYPE_8xx) != 0) {
registers->source_bytes_per_row_rgb = (((overlay->buffer_offset + (view->width << 1)
+ 0x1f) >> 5) - (overlay->buffer_offset >> 5) - 1) << 2;
} else {
registers->source_bytes_per_row_rgb = ((((overlay->buffer_offset + (view->width << 1)
+ 0x3f) >> 6) - (overlay->buffer_offset >> 6) << 1) - 1) << 2;
}
// horizontal scaling
registers->scale_rgb.horizontal_downscale_factor = horizontalScale >> 12;

20
src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
View File

@ -156,9 +156,9 @@ init_interrupt_handler(intel_info &info)
status_t
intel_free_memory(intel_info &info, addr_t offset)
intel_free_memory(intel_info &info, addr_t base)
{
return gGART->deallocate_memory(info.aperture, info.aperture_base + offset);
return gGART->free_memory(info.aperture, base);
}
@ -231,21 +231,13 @@ intel_extreme_init(intel_info &info)
// write combining...
ring_buffer &primary = info.shared_info->primary_ring_buffer;
if (intel_allocate_memory(info, 4 * B_PAGE_SIZE, 0, 0,
if (intel_allocate_memory(info, 16 * B_PAGE_SIZE, 0, 0,
(addr_t *)&primary.base) == B_OK) {
primary.register_base = INTEL_PRIMARY_RING_BUFFER;
primary.size = 4 * B_PAGE_SIZE;
primary.size = 16 * B_PAGE_SIZE;
primary.offset = (addr_t)primary.base - info.aperture_base;
}
ring_buffer &secondary = info.shared_info->secondary_ring_buffer;
if (intel_allocate_memory(info, B_PAGE_SIZE, 0, 0,
(addr_t *)&secondary.base) == B_OK) {
secondary.register_base = INTEL_SECONDARY_RING_BUFFER_0;
secondary.size = B_PAGE_SIZE;
secondary.offset = (addr_t)secondary.base - info.aperture_base;
}
// Fix some problems on certain chips (taken from X driver)
// TODO: clean this up
if (info.pci->device_id == 0x2a02 || info.pci->device_id == 0x2a12) {
@ -293,7 +285,9 @@ intel_extreme_init(intel_info &info)
// setup overlay registers
if (intel_allocate_memory(info, B_PAGE_SIZE, 0, B_APERTURE_NEED_PHYSICAL,
if (intel_allocate_memory(info, B_PAGE_SIZE, 0,
intel_uses_physical_overlay(*info.shared_info)
? B_APERTURE_NEED_PHYSICAL : 0,
(addr_t *)&info.overlay_registers,
&info.shared_info->physical_overlay_registers) == B_OK) {
info.shared_info->overlay_offset = (addr_t)info.overlay_registers