added chip_rev fetching code, updated doc.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14195 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -4,7 +4,7 @@
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</head>
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<body>
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<p><h2>Changes done for each driverversion:</h2></p>
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<p><h1>via_driver (SVN 0.11, Rudolf)</h1></p>
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<p><h1>via_driver (SVN 0.12, Rudolf)</h1></p>
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<ul>
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<li>Initial setup based on nVidia driver 0.30;
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<li>Kerneldriver uses MTR-WC mapping where available;
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@ -23,7 +23,7 @@
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</ul>
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<p><h1>Still todo:</h1></p>
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<ul>
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<li>Video overlay;
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<li>Video overlay (in progress);
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<li>2D acceleration;
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<li>And yet more could be done.
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</ul>
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@ -31,6 +31,6 @@
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<hr><br>
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<br>
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<a href="mailto:info.be-hold@inter.nl.net">Rudolf Cornelissen.</a>
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<p>(Page last updated on September 15, 2005)</p>
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<p>(Page last updated on September 17, 2005)</p>
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</body>
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</html>
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@ -4,7 +4,7 @@
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Other authors:
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Mark Watson;
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Rudolf Cornelissen 3/2002-11/2004.
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Rudolf Cornelissen 3/2002-9/2005.
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*/
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/* standard kernel driver stuff */
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@ -670,29 +670,8 @@ static status_t open_hook (const char* name, uint32 flags, void** cookie) {
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si->device = di->pcii.device;
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si->function = di->pcii.function;
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/* note the amount of system RAM the system BIOS assigned to the card if applicable:
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* unified memory architecture (UMA) */
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switch ((((uint32)(si->device_id)) << 16) | si->vendor_id)
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{
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case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */
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/* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */
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si->ps.memory_size = 1024 * 1024 *
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(((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1);
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/* last 64kB RAM is used for the BIOS (or something else?) */
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si->ps.memory_size -= (64 * 1024);
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break;
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case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */
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/* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */
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si->ps.memory_size = 1024 * 1024 *
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(((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1);
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/* last 64kB RAM is used for the BIOS (or something else?) */
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si->ps.memory_size -= (64 * 1024);
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break;
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default:
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/* all other cards have own RAM: the amount of which is determined in the
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* accelerant. */
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break;
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}
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/* device at bus #0, device #0, function #0 holds byte value at byte-index 0xf6 */
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si->ps.chip_rev = ((*pci_bus->read_pci_config)(0, 0, 0, 0xf6, 1));
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/* map the device */
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result = map_device(di);
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