added chip_rev fetching code, updated doc.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14195 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-09-17 08:44:34 +00:00
parent f583f15cbc
commit 76da25cab4
2 changed files with 6 additions and 27 deletions

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@ -4,7 +4,7 @@
</head>
<body>
<p><h2>Changes done for each driverversion:</h2></p>
<p><h1>via_driver (SVN 0.11, Rudolf)</h1></p>
<p><h1>via_driver (SVN 0.12, Rudolf)</h1></p>
<ul>
<li>Initial setup based on nVidia driver 0.30;
<li>Kerneldriver uses MTR-WC mapping where available;
@ -23,7 +23,7 @@
</ul>
<p><h1>Still todo:</h1></p>
<ul>
<li>Video overlay;
<li>Video overlay (in progress);
<li>2D acceleration;
<li>And yet more could be done.
</ul>
@ -31,6 +31,6 @@
<hr><br>
<br>
<a href="mailto:info.be-hold@inter.nl.net">Rudolf Cornelissen.</a>
<p>(Page last updated on September 15, 2005)</p>
<p>(Page last updated on September 17, 2005)</p>
</body>
</html>

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@ -4,7 +4,7 @@
Other authors:
Mark Watson;
Rudolf Cornelissen 3/2002-11/2004.
Rudolf Cornelissen 3/2002-9/2005.
*/
/* standard kernel driver stuff */
@ -670,29 +670,8 @@ static status_t open_hook (const char* name, uint32 flags, void** cookie) {
si->device = di->pcii.device;
si->function = di->pcii.function;
/* note the amount of system RAM the system BIOS assigned to the card if applicable:
* unified memory architecture (UMA) */
switch ((((uint32)(si->device_id)) << 16) | si->vendor_id)
{
case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */
/* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */
si->ps.memory_size = 1024 * 1024 *
(((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1);
/* last 64kB RAM is used for the BIOS (or something else?) */
si->ps.memory_size -= (64 * 1024);
break;
case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */
/* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */
si->ps.memory_size = 1024 * 1024 *
(((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1);
/* last 64kB RAM is used for the BIOS (or something else?) */
si->ps.memory_size -= (64 * 1024);
break;
default:
/* all other cards have own RAM: the amount of which is determined in the
* accelerant. */
break;
}
/* device at bus #0, device #0, function #0 holds byte value at byte-index 0xf6 */
si->ps.chip_rev = ((*pci_bus->read_pci_config)(0, 0, 0, 0xf6, 1));
/* map the device */
result = map_device(di);