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radeon_hd: 64 bit PCI bus fixes

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Change-Id: If14dc31bf4c9360b5e1d0b477ba375cec8f75ba7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4306
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
This commit is contained in:
X512 2021-07-26 02:39:09 +09:00 committed by Alex von Gluck IV
parent 7508e28c4f
commit 756884ad48
3 changed files with 36 additions and 7 deletions
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2
src/add-ons/accelerants/radeon_hd/gpu.cpp
View File

@ -570,7 +570,7 @@ radeon_gpu_mc_init()
} }
gInfo->fb.vramStart = vramBase; gInfo->fb.vramStart = vramBase;
gInfo->fb.vramSize = gInfo->shared_info->frame_buffer_size * 1024; gInfo->fb.vramSize = (uint64)gInfo->shared_info->frame_buffer_size * 1024;
gInfo->fb.vramEnd = (vramBase + gInfo->fb.vramSize) - 1; gInfo->fb.vramEnd = (vramBase + gInfo->fb.vramSize) - 1;
} }

14
src/add-ons/accelerants/radeon_hd/mode.cpp
View File

@ -179,6 +179,14 @@ radeon_set_display_mode(display_mode* mode)
// TODO: multi-monitor? For now we set the mode on // TODO: multi-monitor? For now we set the mode on
// the first display found. // the first display found.
TRACE("%s\n", __func__);
TRACE(" mode->space: %#" B_PRIx32 "\n", mode->space);
TRACE(" mode->virtual_width: %" B_PRIu16 "\n", mode->virtual_width);
TRACE(" mode->virtual_height: %" B_PRIu16 "\n", mode->virtual_height);
TRACE(" mode->h_display_start: %" B_PRIu16 "\n", mode->h_display_start);
TRACE(" mode->v_display_start: %" B_PRIu16 "\n", mode->v_display_start);
TRACE(" mode->flags: %#" B_PRIx32 "\n", mode->flags);
uint8 crtcID = 0; uint8 crtcID = 0;
if (gDisplay[crtcID]->attached == false) if (gDisplay[crtcID]->attached == false)
@ -277,6 +285,12 @@ radeon_get_frame_buffer_config(frame_buffer_config* config)
config->bytes_per_row = gInfo->shared_info->bytes_per_row; config->bytes_per_row = gInfo->shared_info->bytes_per_row;
TRACE(" config->frame_buffer: %#" B_PRIxADDR "\n",
(phys_addr_t)config->frame_buffer);
TRACE(" config->frame_buffer_dma: %#" B_PRIxADDR "\n",
(phys_addr_t)config->frame_buffer_dma);
TRACE(" config->bytes_per_row: %" B_PRIu32 "\n", config->bytes_per_row);
return B_OK; return B_OK;
} }

27
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
View File

@ -538,6 +538,11 @@ radeon_hd_init(radeon_info &info)
"Radeon %s 1002:%" B_PRIX32 "\n", __func__, info.id, "Radeon %s 1002:%" B_PRIX32 "\n", __func__, info.id,
radeon_chip_name[info.chipsetID], info.pciID); radeon_chip_name[info.chipsetID], info.pciID);
// Enable response in I/O, memory space. Enable bus mastering
uint32 pciConfig = get_pci_config(info.pci, PCI_command, 2);
pciConfig |= PCI_command_io | PCI_command_memory | PCI_command_master;
set_pci_config(info.pci, PCI_command, 2, pciConfig);
// *** Map shared info // *** Map shared info
AreaKeeper sharedCreator; AreaKeeper sharedCreator;
info.shared_area = sharedCreator.Create("radeon hd shared info", info.shared_area = sharedCreator.Create("radeon hd shared info",
@ -629,27 +634,37 @@ radeon_hd_init(radeon_info &info)
info.shared_info->graphics_memory_size / 1024); info.shared_info->graphics_memory_size / 1024);
// *** Framebuffer mapping // *** Framebuffer mapping
phys_addr_t physicalAddress = info.pci->u.h0.base_registers[PCI_BAR_FB];
if ((info.pci->u.h0.base_register_flags[PCI_BAR_FB] & PCI_address_type)
== PCI_address_type_64) {
physicalAddress
|= (uint64)info.pci->u.h0.base_registers[PCI_BAR_FB + 1] << 32;
}
TRACE("framebuffer paddr: %#" B_PRIxADDR "\n", physicalAddress);
AreaKeeper frambufferMapper; AreaKeeper frambufferMapper;
info.framebuffer_area = frambufferMapper.Map("radeon hd frame buffer", info.framebuffer_area = frambufferMapper.Map("radeon hd frame buffer",
info.pci->u.h0.base_registers[PCI_BAR_FB], physicalAddress, info.shared_info->frame_buffer_size * 1024,
info.shared_info->frame_buffer_size * 1024,
B_ANY_KERNEL_ADDRESS, B_READ_AREA | B_WRITE_AREA, B_ANY_KERNEL_ADDRESS, B_READ_AREA | B_WRITE_AREA,
(void**)&info.shared_info->frame_buffer); (void**)&info.shared_info->frame_buffer);
if (frambufferMapper.InitCheck() < B_OK) { if (frambufferMapper.InitCheck() < B_OK) {
ERROR("%s: card(%" B_PRId32 "): couldn't map frame buffer!\n", ERROR("%s: card(%" B_PRId32 "): couldn't map frame buffer!\n",
__func__, info.id); __func__, info.id);
return info.framebuffer_area; return info.framebuffer_area;
} }
TRACE("frambuffer vaddr: %#" B_PRIxADDR "\n",
(addr_t)info.shared_info->frame_buffer);
TRACE("frambuffer size: %#" B_PRIxSIZE "\n",
(size_t)info.shared_info->frame_buffer_size * 1024);
// Turn on write combining for the frame buffer area // Turn on write combining for the frame buffer area
vm_set_area_memory_type(info.framebuffer_area, vm_set_area_memory_type(info.framebuffer_area, physicalAddress, B_MTR_WC);
info.pci->u.h0.base_registers[PCI_BAR_FB], B_MTR_WC);
frambufferMapper.Detach(); frambufferMapper.Detach();
info.shared_info->frame_buffer_area = info.framebuffer_area; info.shared_info->frame_buffer_area = info.framebuffer_area;
info.shared_info->frame_buffer_phys info.shared_info->frame_buffer_phys = physicalAddress;
= info.pci->u.h0.base_registers[PCI_BAR_FB];
// Pass common information to accelerant // Pass common information to accelerant
info.shared_info->deviceIndex = info.id; info.shared_info->deviceIndex = info.id;