x86: Debugger can now use dr3
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@ -62,7 +62,7 @@ void arch_syscall_64_bit_return_value(void);
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static inline void
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arch_thread_set_current_thread(Thread* t)
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{
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asm volatile("mov %0, %%gs:0" : : "r" (t));
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asm volatile("mov %0, %%gs:0" : : "r" (t) : "memory");
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}
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@ -9,12 +9,7 @@
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#define ARCH_INIT_USER_DEBUG x86_init_user_debug
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// number of breakpoints the CPU supports
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// On 32-bit, DR3 is used to hold the Thread*.
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#ifdef __x86_64__
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# define X86_BREAKPOINT_COUNT 4
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#else
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# define X86_BREAKPOINT_COUNT 3
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#endif
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#define X86_BREAKPOINT_COUNT 4
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// debug status register DR6
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enum {
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@ -1202,13 +1202,13 @@ arch_debug_get_interrupt_pc(bool* _isSyscall)
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void
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arch_debug_unset_current_thread(void)
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{
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#ifdef __x86_64__
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// Can't just write 0 to the GS base, that will cause the read from %gs:0
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// to fault. Instead point it at a NULL pointer, %gs:0 will get this value.
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static Thread* unsetThread = NULL;
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#ifdef __x86_64__
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x86_write_msr(IA32_MSR_GS_BASE, (addr_t)&unsetThread);
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#else
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x86_write_dr3(NULL);
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asm volatile("mov %0, %%gs:0" : : "r" (unsetThread) : "memory");
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#endif
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}
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@ -201,10 +201,7 @@ install_breakpoints(const arch_team_debug_info& teamInfo)
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asm("mov %0, %%dr0" : : "r"(teamInfo.breakpoints[0].address));
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asm("mov %0, %%dr1" : : "r"(teamInfo.breakpoints[1].address));
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asm("mov %0, %%dr2" : : "r"(teamInfo.breakpoints[2].address));
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#ifdef __x86_64__
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asm("mov %0, %%dr3" : : "r"(teamInfo.breakpoints[3].address));
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// DR3 is used to hold the current Thread* on 32.
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#endif
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// enable breakpoints
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asm("mov %0, %%dr7" : : "r"(teamInfo.dr7));
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