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updated a few comments, added some acc stuff for NV40+ for PIO mode: trying to get that up as well briefle now.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11328 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-02-10 19:40:26 +00:00
parent 5ff65f9b40
commit 7139e38e41
2 changed files with 275 additions and 189 deletions
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92
src/add-ons/accelerants/nvidia/engine/nv_acc.c
View File

@ -170,8 +170,31 @@ status_t nv_acc_init()
* That command is linked to the handle noted here. This handle is then used to
* tell the FIFO to which engine command it is connected!
* (CTX registers are actually a sort of RAM space.) */
if (si->ps.card_arch >= NV40A)
{
/* (first set) */
ACCW(HT_HANDL_00, (0x80000000 | NV10_CONTEXT_SURFACES_2D)); /* 32bit handle (not used) */
ACCW(HT_VALUE_00, 0x0010114c); /* instance $114c, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */
ACCW(HT_VALUE_01, 0x00101148); /* instance $1148, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_02, (0x80000000 | NV4_GDI_RECTANGLE_TEXT)); /* 32bit handle */
ACCW(HT_VALUE_02, 0x0010114a); /* instance $114a, engine = acc engine, CHID = $00 */
/* (second set) */
ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */
ACCW(HT_VALUE_10, 0x00101142); /* instance $1142, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_11, (0x80000000 | NV_IMAGE_BLACK_RECTANGLE)); /* 32bit handle */
ACCW(HT_VALUE_11, 0x00101144); /* instance $1144, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_12, (0x80000000 | NV_IMAGE_PATTERN)); /* 32bit handle */
ACCW(HT_VALUE_12, 0x00101146); /* instance $1146, engine = acc engine, CHID = $00 */
}
else
{
/* (first set) */
//fixme: for NV40 and above the handle values need to be different..
ACCW(HT_HANDL_00, (0x80000000 | NV1_IMAGE_FROM_CPU)); /* 32bit handle (not used?) */
ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */
@ -227,6 +250,7 @@ status_t nv_acc_init()
ACCW(HT_HANDL_17, (0x80000000 | NV10_CONTEXT_SURFACES_ARGB_ZS)); /* 32bit handle (3D only) */
ACCW(HT_VALUE_17, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
}
}
/* program CTX registers: CTX1 is mostly done later (colorspace dependant) */
/* note:
@ -235,6 +259,57 @@ status_t nv_acc_init()
* CTX registers are in fact in the same GPU internal RAM space as the engine's
* hashtable. This means that stuff programmed in here also survives resets and
* power-outages! (confirmed NV11) */
if (si->ps.card_arch >= NV40A)
{
/* setup a DMA define for use by command defines below. */
ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type;
* DMA target node is NVM (non-volatile memory?)
* (instead of doing PCI or AGP transfers) */
ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */
ACCW(PR_CTX2_R, ((0x00000000 & 0xfffff000) | 0x00000002));
/* DMA access type is READ_AND_WRITE;
* memory starts at start of cardRAM (b12-31):
* It's adress needs to be at a 4kb boundary! */
ACCW(PR_CTX3_R, 0x00000002); /* unknown (looks like this is rubbish/not needed?) */
/* setup set '0' for cmd NV_ROP5_SOLID */
ACCW(PR_CTX0_0, 0x02080043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */
ACCW(PR_CTX0_1, 0x00000000); /* extra */
ACCW(PR_CTX1_1, 0x00000000); /* extra */
/* setup set '1' for cmd NV_IMAGE_BLACK_RECTANGLE */
ACCW(PR_CTX0_2, 0x02080019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */
ACCW(PR_CTX0_3, 0x00000000); /* extra */
ACCW(PR_CTX1_3, 0x00000000); /* extra */
/* setup set '2' for cmd NV_IMAGE_PATTERN */
ACCW(PR_CTX0_4, 0x02080018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_4, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_4, 0x00000000); /* method traps disabled */
ACCW(PR_CTX0_5, 0x00000000); /* extra */
ACCW(PR_CTX1_5, 0x00000000); /* extra */
/* setup set '4' for cmd NV_IMAGE_BLIT */
ACCW(PR_CTX0_6, 0x0208005f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_6, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */
ACCW(PR_CTX0_7, 0x00000000); /* extra */
ACCW(PR_CTX1_7, 0x00000000); /* extra */
/* setup set '5' for cmd NV4_GDI_RECTANGLE_TEXT */
ACCW(PR_CTX0_8, 0x0208004a); /* NVclass $04a, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_8, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */
ACCW(PR_CTX0_9, 0x00000000); /* extra */
ACCW(PR_CTX1_9, 0x00000000); /* extra */
/* setup set '6' for cmd NV10_CONTEXT_SURFACES_2D */
ACCW(PR_CTX0_A, 0x02080062); /* NVclass $062, nv10+: little endian */
ACCW(PR_CTX2_A, 0x00001140); /* DMA0 instance is $1140, DMA1 instance invalid */
ACCW(PR_CTX3_A, 0x00001140); /* method trap 0 is $1140, trap 1 disabled */
ACCW(PR_CTX0_B, 0x00000000); /* extra */
ACCW(PR_CTX1_B, 0x00000000); /* extra */
}
else
{
/* setup a DMA define for use by command defines below.
* (would currently be used by CTX 'sets' 0x6 upto/including 0xe: 3D stuff.) */
ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type;
@ -247,8 +322,6 @@ status_t nv_acc_init()
* It's adress needs to be at a 4kb boundary! */
ACCW(PR_CTX3_R, 0x00000002); /* unknown (looks like this is rubbish/not needed?) */
/* setup set '0' for cmd NV_ROP5_SOLID */
//fixme: for NV40 and up each set takes up 8 32-bit words instead of just 4..
//note: setting the colorspaces the way we do needs to be updated as well for this.
ACCW(PR_CTX0_0, 0x01008043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */
ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */
ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */
@ -352,6 +425,7 @@ status_t nv_acc_init()
ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */
ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */
}
}
/*** PGRAPH ***/
switch (si->ps.card_arch)
@ -578,6 +652,8 @@ status_t nv_acc_init()
ACCW(BPIXEL, 0x00000021);
ACCW(STRD_FMT, 0x03020202);
/* PRAMIN */
if (si->ps.card_arch < NV40A)
{
ACCW(PR_CTX1_0, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX1_1, 0x00000302); /* format is X24Y8, LSB mono */
ACCW(PR_CTX1_2, 0x00000202); /* format is X16A8Y8, LSB mono */
@ -597,6 +673,16 @@ status_t nv_acc_init()
ACCW(PR_CTX1_D, 0x00000000); /* format is invalid */
ACCW(PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */
}
}
else
{
ACCW(PR_CTX1_0, 0x00000000); /* NV_ROP5_SOLID 0 */
ACCW(PR_CTX1_2, 0x00000000); /* NV_IMAGE_BLACK_RECTANGLE 1 */
ACCW(PR_CTX1_4, 0x02000000); /* NV_IMAGE_PATTERN 2 */
ACCW(PR_CTX1_6, 0x00000000); /* NV_IMAGE_BLIT 4 */
ACCW(PR_CTX1_8, 0x02000000); /* NV4_GDI_RECTANGLE_TEXT 5 */
ACCW(PR_CTX1_A, 0x00000000); /* NV10_CONTEXT_SURFACES_2D 9 */
}
break;
case B_RGB15_LITTLE:
/* acc engine */

16
src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
View File

@ -157,20 +157,20 @@ status_t nv_acc_init_dma()
ACCW(HT_VALUE_00, 0x0010114c); /* instance $114c, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */
ACCW(HT_VALUE_01, 0x00101148); /* instance $1146, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_01, 0x00101148); /* instance $1148, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_02, (0x80000000 | NV4_GDI_RECTANGLE_TEXT)); /* 32bit handle */
ACCW(HT_VALUE_02, 0x0010114a); /* instance $1147, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_02, 0x0010114a); /* instance $114a, engine = acc engine, CHID = $00 */
/* (second set) */
ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */
ACCW(HT_VALUE_10, 0x00101142); /* instance $1142, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_11, (0x80000000 | NV_IMAGE_BLACK_RECTANGLE)); /* 32bit handle */
ACCW(HT_VALUE_11, 0x00101144); /* instance $1143, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_11, 0x00101144); /* instance $1144, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_12, (0x80000000 | NV_IMAGE_PATTERN)); /* 32bit handle */
ACCW(HT_VALUE_12, 0x00101146); /* instance $1144, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_12, 0x00101146); /* instance $1146, engine = acc engine, CHID = $00 */
}
else
{
@ -179,20 +179,20 @@ status_t nv_acc_init_dma()
ACCW(HT_VALUE_00, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */
ACCW(HT_VALUE_01, 0x80011148); /* instance $1146, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_01, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_02, (0x80000000 | NV4_GDI_RECTANGLE_TEXT)); /* 32bit handle */
ACCW(HT_VALUE_02, 0x8001114a); /* instance $1147, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_02, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */
/* (second set) */
ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */
ACCW(HT_VALUE_10, 0x80011142); /* instance $1142, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_11, (0x80000000 | NV_IMAGE_BLACK_RECTANGLE)); /* 32bit handle */
ACCW(HT_VALUE_11, 0x80011144); /* instance $1143, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_11, 0x80011144); /* instance $1144, engine = acc engine, CHID = $00 */
ACCW(HT_HANDL_12, (0x80000000 | NV_IMAGE_PATTERN)); /* 32bit handle */
ACCW(HT_VALUE_12, 0x80011146); /* instance $1144, engine = acc engine, CHID = $00 */
ACCW(HT_VALUE_12, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */
}
/* program CTX registers: CTX1 is mostly done later (colorspace dependant) */