* Some preparations for the new driver architecture: added FindCapability(),
and {Read|Write}Config() that get a PCIDev structure, added a FindDevice()
method.
* Made sPCI a global gPCI, since the new PCI root/device modules will be using
it directly.
* Moved the functionality of pci_find_capability() into a new
PCI::FindCapability() method.
* Removed the redundant "Pci" from PCI::{Read|Write}PciConfig(), and
GetNthPciInfo().
* Added PCI::_NumFunctions() that returns the number of functions instead of
doing it manually every time.
* Tried to honour the 80 character limit, as well as other coding style things
a bit more.
* Added '_' prefix for private method names.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25575 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
parent
0f0fba6373
commit
705263f5b3
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,6 @@
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/*
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* Copyright 2006, Marcus Overhagen. All rights reserved.
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* Copyright 2005, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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* Copyright 2003, Marcus Overhagen. All rights reserved.
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* Copyright 2003-2008, Marcus Overhagen. All rights reserved.
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* Copyright 2005-2008, Axel Dörfler, axeld@pinc-software.de. All rights reserved.
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*
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* Distributed under the terms of the MIT License.
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*/
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@ -19,7 +18,7 @@
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#define TRACE_PCI
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#ifndef TRACE_PCI
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# define TRACE(x)
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# define TRACE(x)
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#else
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# define TRACE(x) dprintf x
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#endif
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@ -30,104 +29,131 @@
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struct PCIDev;
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struct PCIBus {
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PCIBus *next;
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PCIDev *parent;
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PCIDev *child;
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int domain;
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uint8 bus;
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PCIBus * next;
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PCIDev * parent;
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PCIDev * child;
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int domain;
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uint8 bus;
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};
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struct PCIDev {
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PCIDev *next;
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PCIBus *parent;
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PCIBus *child;
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int domain;
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uint8 bus;
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uint8 dev;
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uint8 func;
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pci_info info;
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PCIDev * next;
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PCIBus * parent;
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PCIBus * child;
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int domain;
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uint8 bus;
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uint8 device;
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uint8 function;
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pci_info info;
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};
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struct domain_data
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{
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struct domain_data {
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// These two are set in PCI::AddController:
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pci_controller * controller;
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void * controller_cookie;
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// All the rest is set in PCI::InitDomainData
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int max_bus_devices;
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};
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class PCI {
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public:
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public:
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PCI();
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~PCI();
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void InitDomainData();
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void InitBus();
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status_t AddController(pci_controller *controller, void *controller_cookie);
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void InitDomainData();
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void InitBus();
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status_t GetNthPciInfo(long index, pci_info *outInfo);
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status_t AddController(pci_controller *controller,
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void *controller_cookie);
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status_t ReadPciConfig(int domain, uint8 bus, uint8 device, uint8 function,
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uint8 offset, uint8 size, uint32 *value);
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status_t GetNthInfo(long index, pci_info *outInfo);
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uint32 ReadPciConfig(int domain, uint8 bus, uint8 device, uint8 function,
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uint8 offset, uint8 size);
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status_t ReadConfig(int domain, uint8 bus, uint8 device,
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uint8 function, uint8 offset, uint8 size,
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uint32 *value);
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uint32 ReadConfig(int domain, uint8 bus, uint8 device,
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uint8 function, uint8 offset, uint8 size);
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uint32 ReadConfig(PCIDev *device, uint8 offset,
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uint8 size);
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status_t WritePciConfig(int domain, uint8 bus, uint8 device, uint8 function,
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uint8 offset, uint8 size, uint32 value);
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status_t WriteConfig(int domain, uint8 bus, uint8 device,
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uint8 function, uint8 offset, uint8 size,
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uint32 value);
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status_t WriteConfig(PCIDev *device, uint8 offset,
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uint8 size, uint32 value);
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status_t ResolveVirtualBus(uint8 virtualBus, int *domain, uint8 *bus);
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void ClearDeviceStatus(PCIBus *bus, bool dumpStatus);
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status_t FindCapability(int domain, uint8 bus, uint8 device,
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uint8 function, uint8 capID, uint8 *offset);
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status_t FindCapability(PCIDev *device, uint8 capID,
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uint8 *offset);
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private:
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status_t ResolveVirtualBus(uint8 virtualBus, int *domain,
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uint8 *bus);
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void EnumerateBus(int domain, uint8 bus, uint8 *subordinate_bus = NULL);
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PCIDev * FindDevice(int domain, uint8 bus, uint8 device,
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uint8 function);
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void FixupDevices(int domain, uint8 bus);
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void ClearDeviceStatus(PCIBus *bus, bool dumpStatus);
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void DiscoverBus(PCIBus *bus);
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void DiscoverDevice(PCIBus *bus, uint8 dev, uint8 func);
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private:
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void _EnumerateBus(int domain, uint8 bus,
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uint8 *subordinateBus = NULL);
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PCIDev *CreateDevice(PCIBus *parent, uint8 dev, uint8 func);
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PCIBus *CreateBus(PCIDev *parent, int domain, uint8 bus);
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void _FixupDevices(int domain, uint8 bus);
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status_t GetNthPciInfo(PCIBus *bus, long *curindex, long wantindex, pci_info *outInfo);
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void ReadPciBasicInfo(PCIDev *dev);
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void ReadPciHeaderInfo(PCIDev *dev);
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void _DiscoverBus(PCIBus *bus);
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void _DiscoverDevice(PCIBus *bus, uint8 dev,
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uint8 function);
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void ConfigureBridges(PCIBus *bus);
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void RefreshDeviceInfo(PCIBus *bus);
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PCIDev * _CreateDevice(PCIBus *parent, uint8 dev,
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uint8 function);
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PCIBus * _CreateBus(PCIDev *parent, int domain, uint8 bus);
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uint32 BarSize(uint32 bits, uint32 mask);
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void GetBarInfo(PCIDev *dev, uint8 offset, uint32 *address, uint32 *size = 0, uint8 *flags = 0);
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void GetRomBarInfo(PCIDev *dev, uint8 offset, uint32 *address, uint32 *size = 0, uint8 *flags = 0);
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domain_data * GetDomainData(int domain);
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status_t CreateVirtualBus(int domain, uint8 bus, uint8 *virtualBus);
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status_t _GetNthInfo(PCIBus *bus, long *currentIndex,
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long wantIndex, pci_info *outInfo);
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void _ReadBasicInfo(PCIDev *dev);
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void _ReadHeaderInfo(PCIDev *dev);
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private:
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PCIBus * fRootBus;
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void _ConfigureBridges(PCIBus *bus);
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void _RefreshDeviceInfo(PCIBus *bus);
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enum { MAX_PCI_DOMAINS = 8 };
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domain_data fDomainData[MAX_PCI_DOMAINS];
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int fDomainCount;
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bool fBusEnumeration;
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uint32 _BarSize(uint32 bits, uint32 mask);
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void _GetBarInfo(PCIDev *dev, uint8 offset,
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uint32 *address, uint32 *size = 0,
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uint8 *flags = 0);
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void _GetRomBarInfo(PCIDev *dev, uint8 offset,
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uint32 *address, uint32 *size = 0,
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uint8 *flags = 0);
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typedef VectorMap<uint8, uint16> VirtualBusMap;
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domain_data * _GetDomainData(int domain);
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VirtualBusMap fVirtualBusMap;
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int fNextVirtualBus;
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status_t _CreateVirtualBus(int domain, uint8 bus,
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uint8 *virtualBus);
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int _NumFunctions(int domain, uint8 bus, uint8 device);
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PCIDev * _FindDevice(PCIBus *current, int domain, uint8 bus,
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uint8 device, uint8 function);
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private:
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PCIBus * fRootBus;
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enum { MAX_PCI_DOMAINS = 8 };
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domain_data fDomainData[MAX_PCI_DOMAINS];
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int fDomainCount;
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bool fBusEnumeration;
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typedef VectorMap<uint8, uint16> VirtualBusMap;
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VirtualBusMap fVirtualBusMap;
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int fNextVirtualBus;
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};
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extern PCI *gPCI;
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#endif // __cplusplus
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@ -140,8 +166,10 @@ void pci_uninit(void);
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long pci_get_nth_pci_info(long index, pci_info *outInfo);
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uint32 pci_read_config(uint8 virtualBus, uint8 device, uint8 function, uint8 offset, uint8 size);
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void pci_write_config(uint8 virtualBus, uint8 device, uint8 function, uint8 offset, uint8 size, uint32 value);
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uint32 pci_read_config(uint8 virtualBus, uint8 device, uint8 function,
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uint8 offset, uint8 size);
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void pci_write_config(uint8 virtualBus, uint8 device, uint8 function,
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uint8 offset, uint8 size, uint32 value);
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void __pci_resolve_virtual_bus(uint8 virtualBus, int *domain, uint8 *bus);
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@ -12,12 +12,13 @@
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/* The Jmicron AHCI controller has a mode that combines IDE and AHCI functionality
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* into a single PCI device at function 0. This happens when the controller is set
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* in the BIOS to "basic" or "IDE" mode (but not in "RAID" or "AHCI" mode).
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* To avoid needing two drivers to handle a single PCI device, we switch to the
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* multifunction (split device) AHCI mode. This will set PCI device at function 0
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* To avoid needing two drivers to handle a single PCI device, we switch to the
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* multifunction (split device) AHCI mode. This will set PCI device at function 0
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* to AHCI, and PCI device at function 1 to IDE controller.
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*/
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static void
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jmicron_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function, uint16 deviceId)
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jmicron_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device,
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uint8 function, uint16 deviceId)
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{
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switch (deviceId) {
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case 0x2361: // 1 SATA, 1 PATA
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@ -34,26 +35,26 @@ jmicron_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function
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domain, bus, device, function, deviceId);
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if (function == 0) {
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dprintf("jmicron_fixup_ahci: 0x40: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x40, 4));
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dprintf("jmicron_fixup_ahci: 0xdc: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0xdc, 4));
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uint32 val = pci->ReadPciConfig(domain, bus, device, function, 0xdc, 4);
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dprintf("jmicron_fixup_ahci: 0x40: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x40, 4));
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dprintf("jmicron_fixup_ahci: 0xdc: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0xdc, 4));
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uint32 val = pci->ReadConfig(domain, bus, device, function, 0xdc, 4);
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if (!(val & (1 << 30))) {
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uint8 irq = pci->ReadPciConfig(domain, bus, device, function, 0x3c, 1);
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uint8 irq = pci->ReadConfig(domain, bus, device, function, 0x3c, 1);
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dprintf("jmicron_fixup_ahci: enabling split device mode\n");
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val &= ~(1 << 24);
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val |= (1 << 25) | (1 << 30);
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pci->WritePciConfig(domain, bus, device, function, 0xdc, 4, val);
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val = pci->ReadPciConfig(domain, bus, device, function, 0x40, 4);
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pci->WriteConfig(domain, bus, device, function, 0xdc, 4, val);
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val = pci->ReadConfig(domain, bus, device, function, 0x40, 4);
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val &= ~(1 << 16);
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val |= (1 << 1) | (1 << 17) | (1 << 22);
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pci->WritePciConfig(domain, bus, device, function, 0x40, 4, val);
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pci->WriteConfig(domain, bus, device, function, 0x40, 4, val);
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if (function == 0)
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pci->WritePciConfig(domain, bus, device, 1, 0x3c, 1, irq);
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else
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pci->WriteConfig(domain, bus, device, 1, 0x3c, 1, irq);
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else
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dprintf("jmicron_fixup_ahci: can't assign IRQ\n");
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}
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dprintf("jmicron_fixup_ahci: 0x40: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x40, 4));
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dprintf("jmicron_fixup_ahci: 0xdc: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0xdc, 4));
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dprintf("jmicron_fixup_ahci: 0x40: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x40, 4));
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dprintf("jmicron_fixup_ahci: 0xdc: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0xdc, 4));
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}
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}
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@ -85,49 +86,49 @@ intel_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function,
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dprintf("intel_fixup_ahci: domain %u, bus %u, device %u, function %u, deviceId 0x%04x\n",
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domain, bus, device, function, deviceId);
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dprintf("intel_fixup_ahci: 0x24: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x24, 4));
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dprintf("intel_fixup_ahci: 0x90: 0x%02lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x90, 1));
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dprintf("intel_fixup_ahci: 0x24: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x24, 4));
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dprintf("intel_fixup_ahci: 0x90: 0x%02lx\n", pci->ReadConfig(domain, bus, device, function, 0x90, 1));
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uint8 map = pci->ReadPciConfig(domain, bus, device, function, 0x90, 1);
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uint8 map = pci->ReadConfig(domain, bus, device, function, 0x90, 1);
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if ((map >> 6) == 0) {
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uint32 bar5 = pci->ReadPciConfig(domain, bus, device, function, 0x24, 4);
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uint16 pcicmd = pci->ReadPciConfig(domain, bus, device, function, PCI_command, 2);
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uint32 bar5 = pci->ReadConfig(domain, bus, device, function, 0x24, 4);
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uint16 pcicmd = pci->ReadConfig(domain, bus, device, function, PCI_command, 2);
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dprintf("intel_fixup_ahci: switching from IDE to AHCI mode\n");
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pci->WritePciConfig(domain, bus, device, function, PCI_command, 2,
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pci->WriteConfig(domain, bus, device, function, PCI_command, 2,
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pcicmd & ~(PCI_command_io | PCI_command_memory));
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pci->WritePciConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
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dprintf("intel_fixup_ahci: ide-bar5 bits-1: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x24, 4));
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pci->WritePciConfig(domain, bus, device, function, 0x24, 4, 0);
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dprintf("intel_fixup_ahci: ide-bar5 bits-0: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x24, 4));
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pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
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dprintf("intel_fixup_ahci: ide-bar5 bits-1: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x24, 4));
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pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0);
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dprintf("intel_fixup_ahci: ide-bar5 bits-0: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x24, 4));
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map &= ~0x03;
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map |= 0x40;
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pci->WritePciConfig(domain, bus, device, function, 0x90, 1, map);
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pci->WriteConfig(domain, bus, device, function, 0x90, 1, map);
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pci->WritePciConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
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dprintf("intel_fixup_ahci: ahci-bar5 bits-1: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x24, 4));
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pci->WritePciConfig(domain, bus, device, function, 0x24, 4, 0);
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dprintf("intel_fixup_ahci: ahci-bar5 bits-0: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x24, 4));
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pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
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dprintf("intel_fixup_ahci: ahci-bar5 bits-1: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x24, 4));
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pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0);
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dprintf("intel_fixup_ahci: ahci-bar5 bits-0: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x24, 4));
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if (deviceId == 0x27c0 || deviceId == 0x27c4) // restore on ICH7
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pci->WritePciConfig(domain, bus, device, function, 0x24, 4, bar5);
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pci->WriteConfig(domain, bus, device, function, 0x24, 4, bar5);
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pci->WritePciConfig(domain, bus, device, function, PCI_command, 2, pcicmd);
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pci->WriteConfig(domain, bus, device, function, PCI_command, 2, pcicmd);
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}
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dprintf("intel_fixup_ahci: 0x24: 0x%08lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x24, 4));
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dprintf("intel_fixup_ahci: 0x90: 0x%02lx\n", pci->ReadPciConfig(domain, bus, device, function, 0x90, 1));
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dprintf("intel_fixup_ahci: 0x24: 0x%08lx\n", pci->ReadConfig(domain, bus, device, function, 0x24, 4));
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dprintf("intel_fixup_ahci: 0x90: 0x%02lx\n", pci->ReadConfig(domain, bus, device, function, 0x90, 1));
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}
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void
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pci_fixup_device(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function)
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{
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uint16 vendorId = pci->ReadPciConfig(domain, bus, device, function, PCI_vendor_id, 2);
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uint16 deviceId = pci->ReadPciConfig(domain, bus, device, function, PCI_device_id, 2);
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uint16 vendorId = pci->ReadConfig(domain, bus, device, function, PCI_vendor_id, 2);
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uint16 deviceId = pci->ReadConfig(domain, bus, device, function, PCI_device_id, 2);
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// dprintf("pci_fixup_device: domain %u, bus %u, device %u, function %u\n", domain, bus, device, function);
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