moved tracing into it's own header
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25579 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen
parent
307fe93f85
commit
6e251c6604
@ -12,10 +12,11 @@
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#include <KernelExport.h>
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#include <ByteOrder.h>
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#include <new>
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#include <stdio.h>
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#include <string.h>
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#include <tracing.h>
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#include <new>
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#include "ahci_tracing.h"
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#define TRACE(a...) dprintf("\33[34mahci:\33[0m " a)
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//#define FLOW(a...) dprintf("ahci: " a)
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@ -23,63 +24,6 @@
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#define FLOW(a...)
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#define RWTRACE(a...)
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#if AHCI_PORT_TRACING
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namespace AHCIPortTracing {
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class AHCIPortTraceEntry : public AbstractTraceEntry {
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protected:
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AHCIPortTraceEntry(AHCIController* controller, int index)
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: fController(controller)
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, fIndex(index)
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{
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}
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void AddDump(TraceOutput& out, const char* name)
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{
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out.Print("ahci port");
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out.Print(" - %s - ", name);
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out.Print("controller: %p", fController);
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out.Print(", index: %d", fIndex);
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}
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AHCIController* fController;
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int fIndex;
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};
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class AHCIPortPrdTable : public AHCIPortTraceEntry {
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public:
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AHCIPortPrdTable(AHCIController* controller, int index, void* address,
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size_t size)
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: AHCIPortTraceEntry(controller, index)
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, fAddress(address)
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, fSize(size)
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{
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Initialized();
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}
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void AddDump(TraceOutput& out)
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{
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AHCIPortTraceEntry::AddDump(out, "prd table");
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out.Print(", address: %p", fAddress);
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out.Print(", size: %lu", fSize);
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}
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void* fAddress;
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int fSize;
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};
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} // namespace AHCIPortTracing
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# define T(x) new(std::nothrow) AHCIPortTracing::x
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#else
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# define T(x)
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#endif // AHCI_PORT_TRACING
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AHCIPort::AHCIPort(AHCIController *controller, int index)
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: fController(controller)
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@ -385,7 +329,7 @@ AHCIPort::FillPrdTable(volatile prd *prdTable, int *prdCount, int prdMax, const
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while (sgCount > 0 && dataSize > 0) {
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size_t size = min_c(sgTable->size, dataSize);
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void *address = sgTable->address;
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T(AHCIPortPrdTable(fController, fIndex, address, size));
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T_PORT(AHCIPortPrdTable(fController, fIndex, address, size));
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FLOW("FillPrdTable: sg-entry addr %p, size %lu\n", address, size);
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if ((uint32)address & 1) {
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TRACE("AHCIPort::FillPrdTable: data alignment error\n");
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@ -1,30 +1,14 @@
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/*
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* Copyright 2007-2008, Marcus Overhagen. All rights reserved.
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* Copyright 2008, Bruno G. Albuquerque. All rights reserved.
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* Distributed under the terms of the MIT License.
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*/
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#include "ahci_port.h"
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#include "ahci_controller.h"
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#include "util.h"
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#include "ata_cmds.h"
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#include "scsi_cmds.h"
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#include "sata_request.h"
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#include <KernelExport.h>
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#include <ByteOrder.h>
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#include <new>
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#include <stdio.h>
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#include <string.h>
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#include <tracing.h>
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#define TRACE(a...) dprintf("\33[34mahci:\33[0m " a)
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//#define FLOW(a...) dprintf("ahci: " a)
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//#define RWTRACE(a...) dprintf("\33[34mahci:\33[0m " a)
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#define FLOW(a...)
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#define RWTRACE(a...)
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#if AHCI_PORT_TRACING
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class AHCIController;
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namespace AHCIPortTracing {
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class AHCIPortTraceEntry : public AbstractTraceEntry {
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@ -74,759 +58,9 @@ class AHCIPortPrdTable : public AHCIPortTraceEntry {
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} // namespace AHCIPortTracing
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# define T(x) new(std::nothrow) AHCIPortTracing::x
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# define T_PORT(x) new(std::nothrow) AHCIPortTracing::x
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#else
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# define T(x)
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# define T_PORT(x)
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#endif // AHCI_PORT_TRACING
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AHCIPort::AHCIPort(AHCIController *controller, int index)
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: fController(controller)
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, fIndex(index)
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, fRegs(&controller->fRegs->port[index])
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, fArea(-1)
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, fSpinlock(0)
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, fCommandsActive(0)
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, fRequestSem(-1)
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, fResponseSem(-1)
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, fDevicePresent(false)
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, fUse48BitCommands(false)
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, fSectorSize(0)
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, fSectorCount(0)
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, fIsATAPI(false)
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{
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fRequestSem = create_sem(1, "ahci request");
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fResponseSem = create_sem(0, "ahci response");
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}
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AHCIPort::~AHCIPort()
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{
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delete_sem(fRequestSem);
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delete_sem(fResponseSem);
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}
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status_t
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AHCIPort::Init1()
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{
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TRACE("AHCIPort::Init1 port %d\n", fIndex);
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size_t size = sizeof(command_list_entry) * COMMAND_LIST_ENTRY_COUNT + sizeof(fis) + sizeof(command_table) + sizeof(prd) * PRD_TABLE_ENTRY_COUNT;
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char *virtAddr;
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char *physAddr;
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fArea = alloc_mem((void **)&virtAddr, (void **)&physAddr, size, 0, "some AHCI port");
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if (fArea < B_OK) {
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TRACE("failed allocating memory for port %d\n", fIndex);
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return fArea;
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}
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memset(virtAddr, 0, size);
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fCommandList = (command_list_entry *)virtAddr;
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virtAddr += sizeof(command_list_entry) * COMMAND_LIST_ENTRY_COUNT;
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fFIS = (fis *)virtAddr;
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virtAddr += sizeof(fis);
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fCommandTable = (command_table *)virtAddr;
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virtAddr += sizeof(command_table);
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fPRDTable = (prd *)virtAddr;
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TRACE("PRD table is at %p\n", fPRDTable);
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fRegs->clb = LO32(physAddr);
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fRegs->clbu = HI32(physAddr);
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physAddr += sizeof(command_list_entry) * COMMAND_LIST_ENTRY_COUNT;
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fRegs->fb = LO32(physAddr);
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fRegs->fbu = HI32(physAddr);
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physAddr += sizeof(fis);
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fCommandList[0].ctba = LO32(physAddr);
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fCommandList[0].ctbau = HI32(physAddr);
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// prdt follows after command table
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// disable transitions to partial or slumber state
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fRegs->sctl |= 0x300;
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// clear IRQ status bits
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fRegs->is = fRegs->is;
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// clear error bits
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fRegs->serr = fRegs->serr;
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// power up device
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fRegs->cmd |= PORT_CMD_POD;
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// spin up device
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fRegs->cmd |= PORT_CMD_SUD;
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// activate link
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fRegs->cmd = (fRegs->cmd & ~PORT_CMD_ICC_MASK) | PORT_CMD_ICC_ACTIVE;
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// enable FIS receive
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fRegs->cmd |= PORT_CMD_FER;
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FlushPostedWrites();
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return B_OK;
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}
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// called with global interrupts enabled
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status_t
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AHCIPort::Init2()
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{
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TRACE("AHCIPort::Init2 port %d\n", fIndex);
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// start DMA engine
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fRegs->cmd |= PORT_CMD_ST;
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// enable interrupts
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fRegs->ie = PORT_INT_MASK;
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FlushPostedWrites();
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ResetDevice();
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PostResetDevice();
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TRACE("ie 0x%08lx\n", fRegs->ie);
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TRACE("is 0x%08lx\n", fRegs->is);
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TRACE("cmd 0x%08lx\n", fRegs->cmd);
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TRACE("ssts 0x%08lx\n", fRegs->ssts);
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TRACE("sctl 0x%08lx\n", fRegs->sctl);
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TRACE("serr 0x%08lx\n", fRegs->serr);
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TRACE("sact 0x%08lx\n", fRegs->sact);
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TRACE("tfd 0x%08lx\n", fRegs->tfd);
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fDevicePresent = (fRegs->ssts & 0xf) == 0x3;
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return B_OK;
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}
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void
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AHCIPort::Uninit()
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{
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TRACE("AHCIPort::Uninit port %d\n", fIndex);
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// disable FIS receive
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fRegs->cmd &= ~PORT_CMD_FER;
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// wait for receive completition, up to 500ms
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if (wait_until_clear(&fRegs->cmd, PORT_CMD_FR, 500000) < B_OK) {
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TRACE("AHCIPort::Uninit port %d error FIS rx still running\n", fIndex);
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}
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// stop DMA engine
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fRegs->cmd &= ~PORT_CMD_ST;
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// wait for DMA completition
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if (wait_until_clear(&fRegs->cmd, PORT_CMD_CR, 500000) < B_OK) {
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TRACE("AHCIPort::Uninit port %d error DMA engine still running\n", fIndex);
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}
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// disable interrupts
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fRegs->ie = 0;
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// clear pending interrupts
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fRegs->is = fRegs->is;
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// invalidate DMA addresses
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fRegs->clb = 0;
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fRegs->clbu = 0;
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fRegs->fb = 0;
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fRegs->fbu = 0;
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delete_area(fArea);
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}
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status_t
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AHCIPort::ResetDevice()
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{
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TRACE("AHCIPort::ResetDevice port %d\n", fIndex);
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// stop DMA engine
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fRegs->cmd &= ~PORT_CMD_ST;
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FlushPostedWrites();
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if (wait_until_clear(&fRegs->cmd, PORT_CMD_CR, 500000) < B_OK) {
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TRACE("AHCIPort::ResetDevice port %d error DMA engine doesn't stop\n", fIndex);
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}
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// perform a hard reset
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fRegs->sctl = (fRegs->sctl & ~0xf) | 1;
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FlushPostedWrites();
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spin(1100);
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fRegs->sctl &= ~0xf;
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FlushPostedWrites();
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if (wait_until_set(&fRegs->ssts, 0x1, 100000) < B_OK) {
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TRACE("AHCIPort::ResetDevice port %d no device detected\n", fIndex);
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}
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// clear error bits
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fRegs->serr = fRegs->serr;
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FlushPostedWrites();
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if (fRegs->ssts & 1) {
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if (wait_until_set(&fRegs->ssts, 0x3, 500000) < B_OK) {
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TRACE("AHCIPort::ResetDevice port %d device present but no phy communication\n", fIndex);
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}
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}
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// clear error bits
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fRegs->serr = fRegs->serr;
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FlushPostedWrites();
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// start DMA engine
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fRegs->cmd |= PORT_CMD_ST;
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FlushPostedWrites();
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return B_OK;
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}
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status_t
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AHCIPort::PostResetDevice()
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{
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TRACE("AHCIPort::PostResetDevice port %d\n", fIndex);
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if ((fRegs->ssts & 0xf) != 0x3 || (fRegs->tfd & 0xff) == 0x7f) {
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TRACE("AHCIPort::PostResetDevice port %d: no device\n", fIndex);
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return B_OK;
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}
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if ((fRegs->tfd & 0xff) == 0xff)
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snooze(200000);
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if ((fRegs->tfd & 0xff) == 0xff) {
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TRACE("AHCIPort::PostResetDevice port %d: invalid task file status 0xff\n", fIndex);
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return B_ERROR;
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}
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wait_until_clear(&fRegs->tfd, ATA_BSY, 31000000);
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fIsATAPI = fRegs->sig == 0xeb140101;
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if (fIsATAPI)
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fRegs->cmd |= PORT_CMD_ATAPI;
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else
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fRegs->cmd &= ~PORT_CMD_ATAPI;
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FlushPostedWrites();
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TRACE("device signature 0x%08lx (%s)\n", fRegs->sig,
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(fRegs->sig == 0xeb140101) ? "ATAPI" : (fRegs->sig == 0x00000101) ? "ATA" : "unknown");
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return B_OK;
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}
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void
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AHCIPort::DumpD2HFis()
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{
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TRACE("D2H FIS:\n");
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TRACE(" DW0 %02x %02x %02x %02x\n", fFIS->rfis[3], fFIS->rfis[2], fFIS->rfis[1], fFIS->rfis[0]);
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TRACE(" DW1 %02x %02x %02x %02x\n", fFIS->rfis[7], fFIS->rfis[6], fFIS->rfis[5], fFIS->rfis[4]);
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TRACE(" DW2 %02x %02x %02x %02x\n", fFIS->rfis[11], fFIS->rfis[10], fFIS->rfis[9], fFIS->rfis[8]);
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TRACE(" DW3 %02x %02x %02x %02x\n", fFIS->rfis[15], fFIS->rfis[14], fFIS->rfis[13], fFIS->rfis[12]);
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TRACE(" DW4 %02x %02x %02x %02x\n", fFIS->rfis[19], fFIS->rfis[18], fFIS->rfis[17], fFIS->rfis[16]);
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}
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void
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AHCIPort::Interrupt()
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{
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uint32 is = fRegs->is;
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uint32 ci = fRegs->ci;
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fRegs->is = is; // clear interrupts
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RWTRACE("AHCIPort::Interrupt port %d, fCommandsActive 0x%08lx, is 0x%08lx, ci 0x%08lx\n", fIndex, fCommandsActive, is, ci);
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if (is & PORT_INT_ERROR)
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TRACE("AHCIPort::Interrupt port %d, fCommandsActive 0x%08lx, is 0x%08lx, ci 0x%08lx\n", fIndex, fCommandsActive, is, ci);
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if (is & PORT_INT_FATAL)
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panic("ahci fatal error, is 0x%08lx", is);
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int release = 0;
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acquire_spinlock(&fSpinlock);
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if ((fCommandsActive & 1) && !(ci & 1)) {
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release = 1;
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fCommandsActive &= ~1;
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}
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release_spinlock(&fSpinlock);
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if (release)
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release_sem_etc(fResponseSem, 1, B_RELEASE_IF_WAITING_ONLY | B_DO_NOT_RESCHEDULE);
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}
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status_t
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AHCIPort::FillPrdTable(volatile prd *prdTable, int *prdCount, int prdMax, const void *data, size_t dataSize)
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{
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int peMax = prdMax + 1;
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physical_entry pe[peMax];
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if (get_memory_map(data, dataSize, pe, peMax ) < B_OK) {
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TRACE("AHCIPort::FillPrdTable get_memory_map failed\n");
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return B_ERROR;
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}
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int peUsed;
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for (peUsed = 0; pe[peUsed].size; peUsed++)
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;
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return FillPrdTable(prdTable, prdCount, prdMax, pe, peUsed, dataSize);
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}
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status_t
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AHCIPort::FillPrdTable(volatile prd *prdTable, int *prdCount, int prdMax, const physical_entry *sgTable, int sgCount, size_t dataSize)
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{
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*prdCount = 0;
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while (sgCount > 0 && dataSize > 0) {
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size_t size = min_c(sgTable->size, dataSize);
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void *address = sgTable->address;
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T(AHCIPortPrdTable(fController, fIndex, address, size));
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FLOW("FillPrdTable: sg-entry addr %p, size %lu\n", address, size);
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if ((uint32)address & 1) {
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TRACE("AHCIPort::FillPrdTable: data alignment error\n");
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return B_ERROR;
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}
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dataSize -= size;
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while (size > 0) {
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size_t bytes = min_c(size, PRD_MAX_DATA_LENGTH);
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if (*prdCount == prdMax) {
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TRACE("AHCIPort::FillPrdTable: prd table exhausted\n");
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return B_ERROR;
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}
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FLOW("FillPrdTable: prd-entry %u, addr %p, size %lu\n", *prdCount, address, bytes);
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prdTable->dba = LO32(address);
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prdTable->dbau = HI32(address);
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prdTable->res = 0;
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prdTable->dbc = bytes - 1;
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*prdCount += 1;
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prdTable++;
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address = (char *)address + bytes;
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size -= bytes;
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}
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sgTable++;
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sgCount--;
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}
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if (*prdCount == 0) {
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TRACE("AHCIPort::FillPrdTable: count is 0\n");
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return B_ERROR;
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}
|
||||
if (dataSize > 0) {
|
||||
TRACE("AHCIPort::FillPrdTable: sg table %ld bytes too small\n", dataSize);
|
||||
return B_ERROR;
|
||||
}
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::StartTransfer()
|
||||
{
|
||||
acquire_sem(fRequestSem);
|
||||
}
|
||||
|
||||
|
||||
status_t
|
||||
AHCIPort::WaitForTransfer(int *tfd, bigtime_t timeout)
|
||||
{
|
||||
status_t result = B_OK;
|
||||
if (acquire_sem_etc(fResponseSem, 1, B_RELATIVE_TIMEOUT, timeout) < B_OK) {
|
||||
fCommandsActive &= ~1;
|
||||
result = B_TIMED_OUT;
|
||||
} else {
|
||||
*tfd = fRegs->tfd;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::FinishTransfer()
|
||||
{
|
||||
release_sem(fRequestSem);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ScsiTestUnitReady(scsi_ccb *request)
|
||||
{
|
||||
TRACE("AHCIPort::ScsiTestUnitReady port %d\n", fIndex);
|
||||
request->subsys_status = SCSI_REQ_CMP;
|
||||
gSCSI->finished(request, 1);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ScsiInquiry(scsi_ccb *request)
|
||||
{
|
||||
TRACE("AHCIPort::ScsiInquiry port %d\n", fIndex);
|
||||
|
||||
scsi_cmd_inquiry *cmd = (scsi_cmd_inquiry *)request->cdb;
|
||||
scsi_res_inquiry scsiData;
|
||||
ata_res_identify_device ataData;
|
||||
|
||||
ASSERT(sizeof(ataData) == 512);
|
||||
|
||||
if (cmd->evpd || cmd->page_code || request->data_length < sizeof(scsiData)) {
|
||||
TRACE("invalid request\n");
|
||||
request->subsys_status = SCSI_REQ_ABORTED;
|
||||
gSCSI->finished(request, 1);
|
||||
return;
|
||||
}
|
||||
|
||||
sata_request sreq;
|
||||
sreq.set_data(&ataData, sizeof(ataData));
|
||||
sreq.set_ata_cmd(fIsATAPI ? 0xa1 : 0xec); // Identify (Packet) Device
|
||||
ExecuteSataRequest(&sreq);
|
||||
sreq.wait_for_completition();
|
||||
|
||||
if (sreq.completition_status() & ATA_ERR) {
|
||||
TRACE("identify device failed\n");
|
||||
request->subsys_status = SCSI_REQ_CMP_ERR;
|
||||
gSCSI->finished(request, 1);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
uint8 *data = (uint8*) &ataData;
|
||||
for (int i = 0; i < 512; i += 8) {
|
||||
TRACE(" %02x %02x %02x %02x %02x %02x %02x %02x\n", data[i], data[i+1], data[i+2], data[i+3], data[i+4], data[i+5], data[i+6], data[i+7]);
|
||||
}
|
||||
|
||||
|
||||
scsiData.device_type = fIsATAPI ? scsi_dev_CDROM : scsi_dev_direct_access;
|
||||
scsiData.device_qualifier = scsi_periph_qual_connected;
|
||||
scsiData.device_type_modifier = 0;
|
||||
scsiData.removable_medium = fIsATAPI;
|
||||
scsiData.ansi_version = 2;
|
||||
scsiData.ecma_version = 0;
|
||||
scsiData.iso_version = 0;
|
||||
scsiData.response_data_format = 2;
|
||||
scsiData.term_iop = false;
|
||||
scsiData.additional_length = sizeof(scsiData) - 4;
|
||||
scsiData.soft_reset = false;
|
||||
scsiData.cmd_queue = false;
|
||||
scsiData.linked = false;
|
||||
scsiData.sync = false;
|
||||
scsiData.write_bus16 = true;
|
||||
scsiData.write_bus32 = false;
|
||||
scsiData.relative_address = false;
|
||||
memcpy(scsiData.vendor_ident, ataData.model_number, sizeof(scsiData.vendor_ident));
|
||||
memcpy(scsiData.product_ident, ataData.model_number + 8, sizeof(scsiData.product_ident));
|
||||
memcpy(scsiData.product_rev, ataData.serial_number, sizeof(scsiData.product_rev));
|
||||
|
||||
if (!fIsATAPI) {
|
||||
bool lba = (ataData.words[49] & (1 << 9)) != 0;
|
||||
bool lba48 = (ataData.words[83] & (1 << 10)) != 0;
|
||||
uint32 sectors = *(uint32*)&ataData.words[60];
|
||||
uint64 sectors48 = *(uint64*)&ataData.words[100];
|
||||
fUse48BitCommands = lba && lba48;
|
||||
fSectorSize = 512;
|
||||
fSectorCount = !(lba || sectors) ? 0 : lba48 ? sectors48 : sectors;
|
||||
TRACE("lba %d, lba48 %d, fUse48BitCommands %d, sectors %lu, sectors48 %llu, size %llu\n",
|
||||
lba, lba48, fUse48BitCommands, sectors, sectors48, fSectorCount * fSectorSize);
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (fSectorCount < 0x0fffffff) {
|
||||
TRACE("disabling 48 bit commands\n");
|
||||
fUse48BitCommands = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
char modelNumber[sizeof(ataData.model_number) + 1];
|
||||
char serialNumber[sizeof(ataData.serial_number) + 1];
|
||||
char firmwareRev[sizeof(ataData.firmware_revision) + 1];
|
||||
|
||||
strlcpy(modelNumber, ataData.model_number, sizeof(modelNumber));
|
||||
strlcpy(serialNumber, ataData.serial_number, sizeof(serialNumber));
|
||||
strlcpy(firmwareRev, ataData.firmware_revision, sizeof(firmwareRev));
|
||||
|
||||
swap_words(modelNumber, sizeof(modelNumber) - 1);
|
||||
swap_words(serialNumber, sizeof(serialNumber) - 1);
|
||||
swap_words(firmwareRev, sizeof(firmwareRev) - 1);
|
||||
|
||||
TRACE("model number: %s\n", modelNumber);
|
||||
TRACE("serial number: %s\n", serialNumber);
|
||||
TRACE("firmware rev.: %s\n", firmwareRev);
|
||||
|
||||
if (sg_memcpy(request->sg_list, request->sg_count, &scsiData, sizeof(scsiData)) < B_OK) {
|
||||
request->subsys_status = SCSI_DATA_RUN_ERR;
|
||||
} else {
|
||||
request->subsys_status = SCSI_REQ_CMP;
|
||||
request->data_resid = request->data_length - sizeof(scsiData);
|
||||
}
|
||||
gSCSI->finished(request, 1);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ScsiSynchronizeCache(scsi_ccb *request)
|
||||
{
|
||||
TRACE("AHCIPort::ScsiSynchronizeCache port %d\n", fIndex);
|
||||
|
||||
sata_request *sreq = new(std::nothrow) sata_request(request);
|
||||
sreq->set_ata_cmd(fUse48BitCommands ? 0xea : 0xe7); // Flush Cache
|
||||
ExecuteSataRequest(sreq);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ScsiReadCapacity(scsi_ccb *request)
|
||||
{
|
||||
TRACE("AHCIPort::ScsiReadCapacity port %d\n", fIndex);
|
||||
|
||||
scsi_cmd_read_capacity *cmd = (scsi_cmd_read_capacity *)request->cdb;
|
||||
scsi_res_read_capacity scsiData;
|
||||
|
||||
if (cmd->pmi || cmd->lba || request->data_length < sizeof(scsiData)) {
|
||||
TRACE("invalid request\n");
|
||||
return;
|
||||
}
|
||||
|
||||
TRACE("SectorSize %lu, SectorCount 0x%llx\n", fSectorSize, fSectorCount);
|
||||
|
||||
if (fSectorCount > 0xffffffff)
|
||||
panic("ahci: SCSI emulation doesn't support harddisks larger than 2TB");
|
||||
|
||||
scsiData.block_size = B_HOST_TO_BENDIAN_INT32(fSectorSize);
|
||||
scsiData.lba = B_HOST_TO_BENDIAN_INT32(fSectorCount - 1);
|
||||
|
||||
if (sg_memcpy(request->sg_list, request->sg_count, &scsiData, sizeof(scsiData)) < B_OK) {
|
||||
request->subsys_status = SCSI_DATA_RUN_ERR;
|
||||
} else {
|
||||
request->subsys_status = SCSI_REQ_CMP;
|
||||
request->data_resid = request->data_length - sizeof(scsiData);
|
||||
}
|
||||
gSCSI->finished(request, 1);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ScsiReadWrite(scsi_ccb *request, uint64 lba, size_t sectorCount, bool isWrite)
|
||||
{
|
||||
RWTRACE("ScsiReadWrite: position %llu, size %lu, isWrite %d\n", lba * 512, sectorCount * 512, isWrite);
|
||||
|
||||
#if 0
|
||||
if (isWrite) {
|
||||
TRACE("write request ignored\n");
|
||||
request->subsys_status = SCSI_REQ_CMP;
|
||||
request->data_resid = 0;
|
||||
gSCSI->finished(request, 1);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
ASSERT(request->data_length == sectorCount * 512);
|
||||
sata_request *sreq = new(std::nothrow) sata_request(request);
|
||||
|
||||
if (fUse48BitCommands) {
|
||||
if (sectorCount > 65536)
|
||||
panic("ahci: ScsiReadWrite length too large, %lu sectors", sectorCount);
|
||||
if (lba > MAX_SECTOR_LBA_48)
|
||||
panic("achi: ScsiReadWrite position too large for 48-bit LBA\n");
|
||||
sreq->set_ata48_cmd(isWrite ? 0x35 : 0x25, lba, sectorCount);
|
||||
} else {
|
||||
if (sectorCount > 256)
|
||||
panic("ahci: ScsiReadWrite length too large, %lu sectors", sectorCount);
|
||||
if (lba > MAX_SECTOR_LBA_28)
|
||||
panic("achi: ScsiReadWrite position too large for normal LBA\n");
|
||||
sreq->set_ata28_cmd(isWrite ? 0xca : 0xc8, lba, sectorCount);
|
||||
}
|
||||
|
||||
ExecuteSataRequest(sreq, isWrite);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ExecuteSataRequest(sata_request *request, bool isWrite)
|
||||
{
|
||||
FLOW("ExecuteAtaRequest port %d\n", fIndex);
|
||||
|
||||
StartTransfer();
|
||||
|
||||
int prdEntrys;
|
||||
|
||||
if (request->ccb())
|
||||
FillPrdTable(fPRDTable, &prdEntrys, PRD_TABLE_ENTRY_COUNT, request->ccb()->sg_list, request->ccb()->sg_count, request->ccb()->data_length);
|
||||
else if (request->data() && request->size())
|
||||
FillPrdTable(fPRDTable, &prdEntrys, PRD_TABLE_ENTRY_COUNT, request->data(), request->size());
|
||||
else
|
||||
prdEntrys = 0;
|
||||
|
||||
FLOW("prdEntrys %d\n", prdEntrys);
|
||||
|
||||
memcpy((char *)fCommandTable->cfis, request->fis(), 20);
|
||||
fCommandList->prdtl_flags_cfl = 0;
|
||||
fCommandList->cfl = 5; // length is 20 bytes, in DWORDS
|
||||
if (isWrite)
|
||||
fCommandList->w = 1;
|
||||
fCommandList->prdtl = prdEntrys;
|
||||
fCommandList->prdbc = 0;
|
||||
|
||||
if (wait_until_clear(&fRegs->tfd, ATA_BSY | ATA_DRQ, 1000000) < B_OK) {
|
||||
TRACE("ExecuteAtaRequest port %d: device is busy\n", fIndex);
|
||||
FinishTransfer();
|
||||
request->abort();
|
||||
return;
|
||||
}
|
||||
|
||||
cpu_status cpu = disable_interrupts();
|
||||
acquire_spinlock(&fSpinlock);
|
||||
fRegs->ci = 1;
|
||||
FlushPostedWrites();
|
||||
fCommandsActive |= 1;
|
||||
release_spinlock(&fSpinlock);
|
||||
restore_interrupts(cpu);
|
||||
|
||||
int tfd;
|
||||
status_t status = WaitForTransfer(&tfd, 5000000);
|
||||
|
||||
FLOW("tfd %#x\n", tfd);
|
||||
FLOW("prdbc %ld\n", fCommandList->prdbc);
|
||||
FLOW("ci 0x%08lx\n", fRegs->ci);
|
||||
FLOW("is 0x%08lx\n", fRegs->is);
|
||||
FLOW("serr 0x%08lx\n", fRegs->serr);
|
||||
|
||||
/*
|
||||
TRACE("ci 0x%08lx\n", fRegs->ci);
|
||||
TRACE("ie 0x%08lx\n", fRegs->ie);
|
||||
TRACE("is 0x%08lx\n", fRegs->is);
|
||||
TRACE("cmd 0x%08lx\n", fRegs->cmd);
|
||||
TRACE("ssts 0x%08lx\n", fRegs->ssts);
|
||||
TRACE("sctl 0x%08lx\n", fRegs->sctl);
|
||||
TRACE("serr 0x%08lx\n", fRegs->serr);
|
||||
TRACE("sact 0x%08lx\n", fRegs->sact);
|
||||
TRACE("tfd 0x%08lx\n", fRegs->tfd);
|
||||
*/
|
||||
|
||||
size_t bytesTransfered = fCommandList->prdbc;
|
||||
|
||||
FinishTransfer();
|
||||
|
||||
if (status < B_OK) {
|
||||
TRACE("ExecuteAtaRequest port %d: device transfer timeout\n", fIndex);
|
||||
request->abort();
|
||||
} else
|
||||
request->finish(tfd, bytesTransfered);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ScsiExecuteRequest(scsi_ccb *request)
|
||||
{
|
||||
|
||||
// TRACE("AHCIPort::ScsiExecuteRequest port %d, opcode 0x%02x, length %u\n", fIndex, request->cdb[0], request->cdb_length);
|
||||
|
||||
if (request->cdb[0] == SCSI_OP_REQUEST_SENSE) {
|
||||
panic("ahci: SCSI_OP_REQUEST_SENSE not yet supported\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!fDevicePresent) {
|
||||
TRACE("no device present on port %d\n", fIndex);
|
||||
request->subsys_status = SCSI_DEV_NOT_THERE;
|
||||
gSCSI->finished(request, 1);
|
||||
return;
|
||||
}
|
||||
|
||||
request->subsys_status = SCSI_REQ_CMP;
|
||||
|
||||
switch (request->cdb[0]) {
|
||||
case SCSI_OP_TEST_UNIT_READY:
|
||||
ScsiTestUnitReady(request);
|
||||
break;
|
||||
case SCSI_OP_INQUIRY:
|
||||
ScsiInquiry(request);
|
||||
break;
|
||||
case SCSI_OP_READ_CAPACITY:
|
||||
ScsiReadCapacity(request);
|
||||
break;
|
||||
case SCSI_OP_SYNCHRONIZE_CACHE:
|
||||
ScsiSynchronizeCache(request);
|
||||
break;
|
||||
case SCSI_OP_READ_6:
|
||||
case SCSI_OP_WRITE_6:
|
||||
{
|
||||
scsi_cmd_rw_6 *cmd = (scsi_cmd_rw_6 *)request->cdb;
|
||||
uint32 position = ((uint32)cmd->high_lba << 16) | ((uint32)cmd->mid_lba << 8) | (uint32)cmd->low_lba;
|
||||
size_t length = cmd->length != 0 ? cmd->length : 256;
|
||||
bool isWrite = request->cdb[0] == SCSI_OP_WRITE_6;
|
||||
ScsiReadWrite(request, position, length, isWrite);
|
||||
break;
|
||||
}
|
||||
case SCSI_OP_READ_10:
|
||||
case SCSI_OP_WRITE_10:
|
||||
{
|
||||
scsi_cmd_rw_10 *cmd = (scsi_cmd_rw_10 *)request->cdb;
|
||||
uint32 position = B_BENDIAN_TO_HOST_INT32(cmd->lba);
|
||||
size_t length = B_BENDIAN_TO_HOST_INT16(cmd->length);
|
||||
bool isWrite = request->cdb[0] == SCSI_OP_WRITE_10;
|
||||
if (length) {
|
||||
ScsiReadWrite(request, position, length, isWrite);
|
||||
} else {
|
||||
TRACE("AHCIPort::ScsiExecuteRequest error: transfer without data!\n");
|
||||
request->subsys_status = SCSI_REQ_INVALID;
|
||||
gSCSI->finished(request, 1);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case SCSI_OP_READ_12:
|
||||
case SCSI_OP_WRITE_12:
|
||||
{
|
||||
scsi_cmd_rw_12 *cmd = (scsi_cmd_rw_12 *)request->cdb;
|
||||
uint32 position = B_BENDIAN_TO_HOST_INT32(cmd->lba);
|
||||
size_t length = B_BENDIAN_TO_HOST_INT32(cmd->length);
|
||||
bool isWrite = request->cdb[0] == SCSI_OP_WRITE_12;
|
||||
if (length) {
|
||||
ScsiReadWrite(request, position, length, isWrite);
|
||||
} else {
|
||||
TRACE("AHCIPort::ScsiExecuteRequest error: transfer without data!\n");
|
||||
request->subsys_status = SCSI_REQ_INVALID;
|
||||
gSCSI->finished(request, 1);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
TRACE("AHCIPort::ScsiExecuteRequest port %d unsupported request opcode 0x%02x\n", fIndex, request->cdb[0]);
|
||||
request->subsys_status = SCSI_REQ_ABORTED;
|
||||
gSCSI->finished(request, 1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uchar
|
||||
AHCIPort::ScsiAbortRequest(scsi_ccb *request)
|
||||
{
|
||||
|
||||
return SCSI_REQ_CMP;
|
||||
}
|
||||
|
||||
|
||||
uchar
|
||||
AHCIPort::ScsiTerminateRequest(scsi_ccb *request)
|
||||
{
|
||||
return SCSI_REQ_CMP;
|
||||
}
|
||||
|
||||
|
||||
uchar
|
||||
AHCIPort::ScsiResetDevice()
|
||||
{
|
||||
return SCSI_REQ_CMP;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
AHCIPort::ScsiGetRestrictions(bool *isATAPI, bool *noAutoSense, uint32 *maxBlocks)
|
||||
{
|
||||
*isATAPI = fIsATAPI;
|
||||
*noAutoSense = false;
|
||||
*maxBlocks = fUse48BitCommands ? 65536 : 256;
|
||||
TRACE("AHCIPort::ScsiGetRestrictions port %d: isATAPI %d, noAutoSense %d, maxBlocks %lu\n",
|
||||
fIndex, *isATAPI, *noAutoSense, *maxBlocks);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user