made code style more consistent with the rest of the driver
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33815 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
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ef831a1dc3
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@ -5,7 +5,6 @@ SetSubDirSupportedPlatformsBeOSCompatible ;
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UsePrivateHeaders graphics ;
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UsePrivateHeaders graphics ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders shared ;
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Addon intel_extreme.accelerant :
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Addon intel_extreme.accelerant :
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accelerant.cpp
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accelerant.cpp
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@ -7,7 +7,6 @@ UsePrivateHeaders [ FDirName kernel arch $(TARGET_ARCH) ] ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders drivers graphics kernel ;
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UsePrivateHeaders drivers graphics kernel ;
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UsePrivateHeaders shared ;
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KernelAddon <agp_gart>intel :
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KernelAddon <agp_gart>intel :
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intel_gart.cpp
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intel_gart.cpp
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@ -149,23 +149,21 @@ determine_memory_sizes(intel_info &info, size_t >tSize, size_t &stolenSize)
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break;
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break;
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}
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}
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} else if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x) {
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} else if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x) {
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switch (memoryConfig & G4X_GGC_GGMS_MASK) {
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switch (memoryConfig & G4X_GTT_MASK) {
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case G4X_GGMS_NONE:
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case G4X_GTT_NONE:
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gttSize = 0;
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gttSize = 0;
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break;
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break;
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case G4X_GGMS_NO_IVT_1M:
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case G4X_GTT_1M_NO_IVT:
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gttSize = 1 << 20;
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gttSize = 1 << 20;
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break;
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break;
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case G4X_GGMS_NO_IVT_2M:
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case G4X_GTT_2M_NO_IVT:
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case G4X_GTT_2M_IVT:
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gttSize = 2 << 20;
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gttSize = 2 << 20;
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break;
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break;
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case G4X_GGMS_IVT_2M:
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case G4X_GTT_3M_IVT:
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gttSize = 2 << 20;
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break;
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case G4X_GGMS_IVT_3M:
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gttSize = 3 << 20;
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gttSize = 3 << 20;
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break;
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break;
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case G4X_GGMS_IVT_4M:
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case G4X_GTT_4M_IVT:
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gttSize = 4 << 20;
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gttSize = 4 << 20;
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break;
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break;
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}
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}
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@ -205,33 +203,6 @@ determine_memory_sizes(intel_info &info, size_t >tSize, size_t &stolenSize)
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memorySize *= 8;
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memorySize *= 8;
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break;
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break;
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}
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}
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} else if (info.type == INTEL_TYPE_G4x) {
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switch (memoryConfig & G4X_GGC_GMS_MASK) {
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case G4X_GMS_32MB:
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memorySize *= 32;
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break;
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case G4X_GMS_64MB:
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memorySize *= 64;
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break;
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case G4X_GMS_128MB:
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memorySize *= 128;
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break;
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case G4X_GMS_256MB:
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memorySize *= 256;
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break;
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case G4X_GMS_96MB:
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memorySize *= 96;
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break;
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case G4X_GMS_160MB:
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memorySize *= 160;
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break;
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case G4X_GMS_224MB:
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memorySize *= 224;
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break;
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case G4X_GMS_352MB:
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memorySize *= 352;
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break;
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}
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} else if (info.type == INTEL_TYPE_85x
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} else if (info.type == INTEL_TYPE_85x
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|| (info.type & INTEL_TYPE_9xx) == INTEL_TYPE_9xx) {
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|| (info.type & INTEL_TYPE_9xx) == INTEL_TYPE_9xx) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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@ -259,6 +230,18 @@ determine_memory_sizes(intel_info &info, size_t >tSize, size_t &stolenSize)
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case i855_STOLEN_MEMORY_256M:
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case i855_STOLEN_MEMORY_256M:
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memorySize *= 256;
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memorySize *= 256;
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break;
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break;
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case G4X_STOLEN_MEMORY_96MB:
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memorySize *= 96;
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break;
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case G4X_STOLEN_MEMORY_160MB:
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memorySize *= 160;
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break;
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case G4X_STOLEN_MEMORY_224MB:
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memorySize *= 224;
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break;
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case G4X_STOLEN_MEMORY_352MB:
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memorySize *= 352;
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break;
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}
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}
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} else {
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} else {
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// TODO: error out!
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// TODO: error out!
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@ -329,12 +312,13 @@ intel_map(intel_info &info)
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if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK)
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if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK)
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return B_ERROR;
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return B_ERROR;
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if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x)
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if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
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info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
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if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x) {
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+ (2UL << 20);
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info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
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else if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
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+ (2UL << 20);
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info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
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} else
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else {
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info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
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} else {
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info.gtt_physical_base = read32(info.registers
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info.gtt_physical_base = read32(info.registers
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+ INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED;
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+ INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED;
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if (info.gtt_physical_base == 0) {
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if (info.gtt_physical_base == 0) {
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@ -5,7 +5,6 @@ SetSubDirSupportedPlatformsBeOSCompatible ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders graphics kernel ;
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UsePrivateHeaders graphics kernel ;
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UsePrivateHeaders shared ;
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KernelAddon intel_extreme :
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KernelAddon intel_extreme :
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driver.cpp
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driver.cpp
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@ -247,13 +247,13 @@ intel_extreme_init(intel_info &info)
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} else if (info.device_type.InGroup(INTEL_TYPE_G4x)) {
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} else if (info.device_type.InGroup(INTEL_TYPE_G4x)) {
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dprintf("G4x clock gating\n");
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dprintf("G4x clock gating\n");
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write32(info.registers + 0x6204, 0);
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write32(info.registers + 0x6204, 0);
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write32(info.registers + 0x6208, BIT(9) | BIT(7) | BIT(6));
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write32(info.registers + 0x6208, (1L << 9) | (1L << 7) | (1L << 6));
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write32(info.registers + 0x6210, 0);
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write32(info.registers + 0x6210, 0);
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uint32 dspclk_gate_val = BIT(28) | BIT(3) | BIT(2);
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uint32 dspclk_gate_val = (1L << 28) | (1L << 3) | (1L << 2);
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if ((info.device_type.type & INTEL_TYPE_MOBILE) == INTEL_TYPE_MOBILE) {
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if ((info.device_type.type & INTEL_TYPE_MOBILE) == INTEL_TYPE_MOBILE) {
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dprintf("G4x mobile clock gating\n");
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dprintf("G4x mobile clock gating\n");
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dspclk_gate_val |= BIT(18);
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dspclk_gate_val |= 1L << 18;
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}
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}
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write32(info.registers + 0x6200, dspclk_gate_val) ;
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write32(info.registers + 0x6200, dspclk_gate_val) ;
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