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accelerants: Fix warning introduced in hrev48265

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* Align types for compare
* Fixes builds
This commit is contained in:
Alexander von Gluck IV 2014-11-09 15:53:44 -06:00
parent 57bc65034a
commit 6ab4ff112a
4 changed files with 4 additions and 4 deletions
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2
src/add-ons/accelerants/ati/rage128_mode.cpp
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@ -223,7 +223,7 @@ CalculatePLLRegisters(const DisplayModeEx& mode, DisplayParams& params)
int bitValue = -1;
uint32 output_freq;
for (int j = 0; j < B_COUNT_OF(postDividers); j++) {
for (int j = 0; j < (int)B_COUNT_OF(postDividers); j++) {
output_freq = postDividers[j].divider * freq;
if (output_freq >= pll.min_pll_freq && output_freq <= pll.max_pll_freq) {
params.feedback_div = DivideWithRounding(pll.reference_div * output_freq,

2
src/add-ons/accelerants/s3/savage_mode.cpp
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@ -565,7 +565,7 @@ Savage_WriteMode(const DisplayModeEx& mode, const SavageRegRec& regRec)
WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11
for (int j = 0; j < B_COUNT_OF(regRec.CRTC); j++)
for (int j = 0; j < (int)B_COUNT_OF(regRec.CRTC); j++)
WriteCrtcReg(j, regRec.CRTC[j]);
// Setup HSYNC & VSYNC polarity.

2
src/add-ons/accelerants/s3/trio64_mode.cpp
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@ -178,7 +178,7 @@ Trio64_ModeInit(const DisplayModeEx& mode)
WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11
for (int k = 0; k < B_COUNT_OF(crtc); k++) {
for (int k = 0; k < (int)B_COUNT_OF(crtc); k++) {
WriteCrtcReg(k, crtc[k]);
}

2
src/add-ons/accelerants/s3/virge_mode.cpp
View File

@ -396,7 +396,7 @@ Virge_WriteMode(const DisplayModeEx& mode, VirgeRegRec& regRec)
WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11
for (int j = 0; j < B_COUNT_OF(regRec.CRTC); j++) {
for (int j = 0; j < (int)B_COUNT_OF(regRec.CRTC); j++) {
WriteCrtcReg(j, regRec.CRTC[j]);
}