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fix bridge control register size

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25551 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen 2008-05-18 21:21:39 +00:00
parent 63f68729a8
commit 694c3b75f4
3 changed files with 5 additions and 5 deletions
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4
headers/os/drivers/PCI.h
View File

@ -107,7 +107,7 @@ typedef struct pci_info {
ulong io_base_upper32;
ulong io_limit_upper32;
ushort secondary_status;
uchar bridge_control;
ushort bridge_control;
#endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */
} h2;
} u;
@ -242,7 +242,7 @@ struct pci_module_info {
#define PCI_io_limit0_2 0x30 /* (4 bytes) */
#define PCI_io_base1_2 0x34 /* (4 bytes) */
#define PCI_io_limit1_2 0x38 /* (4 bytes) */
#define PCI_bridge_control_2 0x3E /* (1 byte) */
#define PCI_bridge_control_2 0x3E /* (2 bytes) */
#define PCI_sub_vendor_id_2 0x40 /* (2 bytes) */
#define PCI_sub_device_id_2 0x42 /* (2 bytes) */

2
src/add-ons/kernel/bus_managers/pci/pci.cpp
View File

@ -1028,7 +1028,7 @@ PCI::ReadPciHeaderInfo(PCIDev *dev)
dev->info.u.h2.io_base_upper32 = ReadPciConfig(dev->domain, dev->bus, dev->dev, dev->func, PCI_io_base1_2, 4);
dev->info.u.h2.io_limit_upper32 = ReadPciConfig(dev->domain, dev->bus, dev->dev, dev->func, PCI_io_limit1_2, 4);
dev->info.u.h2.secondary_status = ReadPciConfig(dev->domain, dev->bus, dev->dev, dev->func, PCI_secondary_status_2, 2);
dev->info.u.h2.bridge_control = ReadPciConfig(dev->domain, dev->bus, dev->dev, dev->func, PCI_bridge_control_2, 1);
dev->info.u.h2.bridge_control = ReadPciConfig(dev->domain, dev->bus, dev->dev, dev->func, PCI_bridge_control_2, 2);
break;
}

4
src/add-ons/kernel/bus_managers/pci/pci_info.cpp
View File

@ -40,7 +40,7 @@ print_pci2pci_bridge_info(const pci_info *info, bool verbose)
info->u.h1.prefetchable_memory_base_upper32, info->u.h1.prefetchable_memory_base));
TRACE(("PCI: prefetchable_memory_limit_upper32 %08lx, prefetchable_memory_limit %04x\n",
info->u.h1.prefetchable_memory_limit_upper32, info->u.h1.prefetchable_memory_limit));
TRACE(("PCI: bridge_control %02x, secondary_status %04x\n",
TRACE(("PCI: bridge_control %04x, secondary_status %04x\n",
info->u.h1.bridge_control, info->u.h1.secondary_status));
TRACE(("PCI: interrupt_line %02x, interrupt_pin %02x\n",
info->u.h1.interrupt_line, info->u.h1.interrupt_pin));
@ -60,7 +60,7 @@ print_pci2cardbus_bridge_info(const pci_info *info, bool verbose)
info->u.h2.subsystem_id, info->u.h2.subsystem_vendor_id));
TRACE(("PCI: primary_bus %02x, secondary_bus %02x, subordinate_bus %02x, secondary_latency %02x\n",
info->u.h2.primary_bus, info->u.h2.secondary_bus, info->u.h2.subordinate_bus, info->u.h2.secondary_latency));
TRACE(("PCI: bridge_control %02x, secondary_status %04x\n",
TRACE(("PCI: bridge_control %04x, secondary_status %04x\n",
info->u.h2.bridge_control, info->u.h2.secondary_status));
TRACE(("PCI: memory_base_upper32 %08lx, memory_base %08lx\n",
info->u.h2.memory_base_upper32, info->u.h2.memory_base));