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OpenBSD-to-FreeBSD/Haiku compatibility headers.

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OpenBSD's and FreeBSD's kernel APIs are very similar, but there are
still some differences. Fortunately these are small enough that we
can take care of most of them with a header-only shim layer.

(The files and functions implemented by this commit were implemented
and tested against the modules and drivers imported and adapted in
the following commits. Some of this took quite a bit of time to get
right, especially where the APIs have diverged in very subtle ways.)
This commit is contained in:
Augustin Cavalier 2022-05-12 23:03:47 -04:00
parent 8548a4adc6
commit 668a169a62
24 changed files with 2122 additions and 0 deletions
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752
src/libs/compat/openbsd_network/compat/dev/pci/pcireg.h Normal file
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/* $OpenBSD: pcireg.h,v 1.60 2021/12/31 11:24:24 jsg Exp $ */
/* $NetBSD: pcireg.h,v 1.26 2000/05/10 16:58:42 thorpej Exp $ */
/*
* Copyright (c) 1995, 1996 Christopher G. Demetriou. All rights reserved.
* Copyright (c) 1994, 1996 Charles Hannum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Charles Hannum.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _DEV_PCI_PCIREG_H_
#define _DEV_PCI_PCIREG_H_
/*
* Standardized PCI configuration information
*
* XXX This is not complete.
*/
#define PCI_CONFIG_SPACE_SIZE 0x100
#define PCIE_CONFIG_SPACE_SIZE 0x1000
/*
* Device identification register; contains a vendor ID and a device ID.
*/
#define PCI_ID_REG 0x00
typedef u_int16_t pci_vendor_id_t;
typedef u_int16_t pci_product_id_t;
#define PCI_VENDOR_SHIFT 0
#define PCI_VENDOR_MASK 0xffff
#define PCI_VENDOR(id) \
(((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
#define PCI_PRODUCT_SHIFT 16
#define PCI_PRODUCT_MASK 0xffff
#define PCI_PRODUCT(id) \
(((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
#define PCI_ID_CODE(vid,pid) \
((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \
(((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT))
/*
* Command and status register.
*/
#define PCI_COMMAND_STATUS_REG 0x04
#define PCI_COMMAND_IO_ENABLE 0x00000001
#define PCI_COMMAND_MEM_ENABLE 0x00000002
#define PCI_COMMAND_MASTER_ENABLE 0x00000004
#define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
#define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
#define PCI_COMMAND_PALETTE_ENABLE 0x00000020
#define PCI_COMMAND_PARITY_ENABLE 0x00000040
#define PCI_COMMAND_STEPPING_ENABLE 0x00000080
#define PCI_COMMAND_SERR_ENABLE 0x00000100
#define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
#define PCI_COMMAND_INTERRUPT_DISABLE 0x00000400
#define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
#define PCI_STATUS_66MHZ_SUPPORT 0x00200000
#define PCI_STATUS_UDF_SUPPORT 0x00400000
#define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
#define PCI_STATUS_PARITY_ERROR 0x01000000
#define PCI_STATUS_DEVSEL_FAST 0x00000000
#define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
#define PCI_STATUS_DEVSEL_SLOW 0x04000000
#define PCI_STATUS_DEVSEL_MASK 0x06000000
#define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
#define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
#define PCI_STATUS_MASTER_ABORT 0x20000000
#define PCI_STATUS_SPECIAL_ERROR 0x40000000
#define PCI_STATUS_PARITY_DETECT 0x80000000
#define PCI_COMMAND_STATUS_BITS \
("\020\01IO\02MEM\03MASTER\04SPECIAL\05INVALIDATE\06PALETTE\07PARITY"\
"\010STEPPING\011SERR\012BACKTOBACK\025CAPLIST\026CLK66\027UDF"\
"\030BACK2BACK_STAT\031PARITY_STAT\032DEVSEL_MEDIUM\033DEVSEL_SLOW"\
"\034TARGET_TARGET_ABORT\035MASTER_TARGET_ABORT\036MASTER_ABORT"\
"\037SPECIAL_ERROR\040PARITY_DETECT")
/*
* PCI Class and Revision Register; defines type and revision of device.
*/
#define PCI_CLASS_REG 0x08
typedef u_int8_t pci_class_t;
typedef u_int8_t pci_subclass_t;
typedef u_int8_t pci_interface_t;
typedef u_int8_t pci_revision_t;
#define PCI_CLASS_SHIFT 24
#define PCI_CLASS_MASK 0xff
#define PCI_CLASS(cr) \
(((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
#define PCI_SUBCLASS_SHIFT 16
#define PCI_SUBCLASS_MASK 0xff
#define PCI_SUBCLASS(cr) \
(((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
#define PCI_INTERFACE_SHIFT 8
#define PCI_INTERFACE_MASK 0xff
#define PCI_INTERFACE(cr) \
(((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
#define PCI_REVISION_SHIFT 0
#define PCI_REVISION_MASK 0xff
#define PCI_REVISION(cr) \
(((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
/* base classes */
#define PCI_CLASS_PREHISTORIC 0x00
#define PCI_CLASS_MASS_STORAGE 0x01
#define PCI_CLASS_NETWORK 0x02
#define PCI_CLASS_DISPLAY 0x03
#define PCI_CLASS_MULTIMEDIA 0x04
#define PCI_CLASS_MEMORY 0x05
#define PCI_CLASS_BRIDGE 0x06
#define PCI_CLASS_COMMUNICATIONS 0x07
#define PCI_CLASS_SYSTEM 0x08
#define PCI_CLASS_INPUT 0x09
#define PCI_CLASS_DOCK 0x0a
#define PCI_CLASS_PROCESSOR 0x0b
#define PCI_CLASS_SERIALBUS 0x0c
#define PCI_CLASS_WIRELESS 0x0d
#define PCI_CLASS_I2O 0x0e
#define PCI_CLASS_SATCOM 0x0f
#define PCI_CLASS_CRYPTO 0x10
#define PCI_CLASS_DASP 0x11
#define PCI_CLASS_ACCELERATOR 0x12
#define PCI_CLASS_INSTRUMENTATION 0x13
#define PCI_CLASS_UNDEFINED 0xff
/* 0x00 prehistoric subclasses */
#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
/* 0x01 mass storage subclasses */
#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
#define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
#define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
#define PCI_SUBCLASS_MASS_STORAGE_SATA 0x06
#define PCI_INTERFACE_SATA_AHCI10 0x01
#define PCI_SUBCLASS_MASS_STORAGE_SAS 0x07
#define PCI_SUBCLASS_MASS_STORAGE_NVM 0x08
#define PCI_SUBCLASS_MASS_STORAGE_UFS 0x09
#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
/* 0x02 network subclasses */
#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
#define PCI_SUBCLASS_NETWORK_FDDI 0x02
#define PCI_SUBCLASS_NETWORK_ATM 0x03
#define PCI_SUBCLASS_NETWORK_ISDN 0x04
#define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
#define PCI_SUBCLASS_NETWORK_INFINIBAND 0x07
#define PCI_SUBCLASS_NETWORK_MISC 0x80
/* 0x03 display subclasses */
#define PCI_SUBCLASS_DISPLAY_VGA 0x00
#define PCI_SUBCLASS_DISPLAY_XGA 0x01
#define PCI_SUBCLASS_DISPLAY_3D 0x02
#define PCI_SUBCLASS_DISPLAY_MISC 0x80
/* 0x04 multimedia subclasses */
#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02
#define PCI_SUBCLASS_MULTIMEDIA_HDAUDIO 0x03
#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
/* 0x05 memory subclasses */
#define PCI_SUBCLASS_MEMORY_RAM 0x00
#define PCI_SUBCLASS_MEMORY_FLASH 0x01
#define PCI_SUBCLASS_MEMORY_MISC 0x80
/* 0x06 bridge subclasses */
#define PCI_SUBCLASS_BRIDGE_HOST 0x00
#define PCI_SUBCLASS_BRIDGE_ISA 0x01
#define PCI_SUBCLASS_BRIDGE_EISA 0x02
#define PCI_SUBCLASS_BRIDGE_MC 0x03
#define PCI_SUBCLASS_BRIDGE_PCI 0x04
#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
#define PCI_SUBCLASS_BRIDGE_STPCI 0x09
#define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
#define PCI_SUBCLASS_BRIDGE_AS 0x0b
#define PCI_SUBCLASS_BRIDGE_MISC 0x80
/* 0x07 communications subclasses */
#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02
#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
#define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04
#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05
#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
/* 0x08 system subclasses */
#define PCI_SUBCLASS_SYSTEM_PIC 0x00
#define PCI_SUBCLASS_SYSTEM_DMA 0x01
#define PCI_SUBCLASS_SYSTEM_TIMER 0x02
#define PCI_SUBCLASS_SYSTEM_RTC 0x03
#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04
#define PCI_SUBCLASS_SYSTEM_SDHC 0x05
#define PCI_SUBCLASS_SYSTEM_IOMMU 0x06
#define PCI_SUBCLASS_SYSTEM_ROOTCOMPEVENT 0x07
#define PCI_SUBCLASS_SYSTEM_MISC 0x80
/* 0x09 input subclasses */
#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
#define PCI_SUBCLASS_INPUT_MOUSE 0x02
#define PCI_SUBCLASS_INPUT_SCANNER 0x03
#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
#define PCI_SUBCLASS_INPUT_MISC 0x80
/* 0x0a dock subclasses */
#define PCI_SUBCLASS_DOCK_GENERIC 0x00
#define PCI_SUBCLASS_DOCK_MISC 0x80
/* 0x0b processor subclasses */
#define PCI_SUBCLASS_PROCESSOR_386 0x00
#define PCI_SUBCLASS_PROCESSOR_486 0x01
#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
/* 0x0c serial bus subclasses */
#define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
#define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
#define PCI_SUBCLASS_SERIALBUS_SSA 0x02
#define PCI_SUBCLASS_SERIALBUS_USB 0x03
#define PCI_SUBCLASS_SERIALBUS_FIBER 0x04
#define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
#define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06
#define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
#define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
#define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
/* 0x0d wireless subclasses */
#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
#define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01
#define PCI_SUBCLASS_WIRELESS_RF 0x10
#define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
#define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
#define PCI_SUBCLASS_WIRELESS_802_11A 0x20
#define PCI_SUBCLASS_WIRELESS_802_11B 0x21
#define PCI_SUBCLASS_WIRELESS_MISC 0x80
/* 0x0e I2O (Intelligent I/O) subclasses */
#define PCI_SUBCLASS_I2O_STANDARD 0x00
/* 0x0f satellite communication subclasses */
/* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */
#define PCI_SUBCLASS_SATCOM_TV 0x01
#define PCI_SUBCLASS_SATCOM_AUDIO 0x02
#define PCI_SUBCLASS_SATCOM_VOICE 0x03
#define PCI_SUBCLASS_SATCOM_DATA 0x04
/* 0x10 encryption/decryption subclasses */
#define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00
#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10
#define PCI_SUBCLASS_CRYPTO_MISC 0x80
/* 0x11 data acquisition and signal processing subclasses */
#define PCI_SUBCLASS_DASP_DPIO 0x00
#define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
#define PCI_SUBCLASS_DASP_SYNC 0x10
#define PCI_SUBCLASS_DASP_MGMT 0x20
#define PCI_SUBCLASS_DASP_MISC 0x80
/*
* PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
*/
#define PCI_BHLC_REG 0x0c
#define PCI_BIST_SHIFT 24
#define PCI_BIST_MASK 0xff
#define PCI_BIST(bhlcr) \
(((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
#define PCI_HDRTYPE_SHIFT 16
#define PCI_HDRTYPE_MASK 0xff
#define PCI_HDRTYPE(bhlcr) \
(((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
#define PCI_HDRTYPE_TYPE(bhlcr) \
(PCI_HDRTYPE(bhlcr) & 0x7f)
#define PCI_HDRTYPE_MULTIFN(bhlcr) \
((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
#define PCI_LATTIMER_SHIFT 8
#define PCI_LATTIMER_MASK 0xff
#define PCI_LATTIMER(bhlcr) \
(((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
#define PCI_CACHELINE_SHIFT 0
#define PCI_CACHELINE_MASK 0xff
#define PCI_CACHELINE(bhlcr) \
(((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
/* config registers for header type 0 devices */
#define PCI_MAPS 0x10
#define PCI_CARDBUSCIS 0x28
#define PCI_SUBVEND_0 0x2c
#define PCI_SUBDEV_0 0x2e
#define PCI_EXROMADDR_0 0x30
#define PCI_INTLINE 0x3c
#define PCI_INTPIN 0x3d
#define PCI_MINGNT 0x3e
#define PCI_MAXLAT 0x3f
/* config registers for header type 1 devices */
#define PCI_SECSTAT_1 0 /**/
#define PCI_PRIBUS_1 0x18
#define PCI_SECBUS_1 0x19
#define PCI_SUBBUS_1 0x1a
#define PCI_SECLAT_1 0x1b
#define PCI_IOBASEL_1 0x1c
#define PCI_IOLIMITL_1 0x1d
#define PCI_IOBASEH_1 0 /**/
#define PCI_IOLIMITH_1 0 /**/
#define PCI_MEMBASE_1 0x20
#define PCI_MEMLIMIT_1 0x22
#define PCI_PMBASEL_1 0x24
#define PCI_PMLIMITL_1 0x26
#define PCI_PMBASEH_1 0 /**/
#define PCI_PMLIMITH_1 0 /**/
#define PCI_BRIDGECTL_1 0 /**/
#define PCI_SUBVEND_1 0x34
#define PCI_SUBDEV_1 0x36
#define PCI_EXROMADDR_1 0x38
/* config registers for header type 2 devices */
#define PCI_SECSTAT_2 0x16
#define PCI_PRIBUS_2 0x18
#define PCI_SECBUS_2 0x19
#define PCI_SUBBUS_2 0x1a
#define PCI_SECLAT_2 0x1b
#define PCI_MEMBASE0_2 0x1c
#define PCI_MEMLIMIT0_2 0x20
#define PCI_MEMBASE1_2 0x24
#define PCI_MEMLIMIT1_2 0x28
#define PCI_IOBASE0_2 0x2c
#define PCI_IOLIMIT0_2 0x30
#define PCI_IOBASE1_2 0x34
#define PCI_IOLIMIT1_2 0x38
#define PCI_BRIDGECTL_2 0x3e
#define PCI_SUBVEND_2 0x40
#define PCI_SUBDEV_2 0x42
#define PCI_PCCARDIF_2 0x44
/*
* Mapping registers
*/
#define PCI_MAPREG_START 0x10
#define PCI_MAPREG_END 0x28
#define PCI_MAPREG_PPB_END 0x18
#define PCI_MAPREG_PCB_END 0x14
#define PCI_MAPREG_TYPE(mr) \
((mr) & PCI_MAPREG_TYPE_MASK)
#define PCI_MAPREG_TYPE_MASK 0x00000001
#define PCI_MAPREG_TYPE_MEM 0x00000000
#define PCI_MAPREG_TYPE_IO 0x00000001
#define PCI_MAPREG_MEM_TYPE(mr) \
((mr) & PCI_MAPREG_MEM_TYPE_MASK)
#define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
#define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
#define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
#define _PCI_MAPREG_TYPEBITS(reg) \
(PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO ? \
reg & PCI_MAPREG_TYPE_MASK : \
reg & (PCI_MAPREG_TYPE_MASK|PCI_MAPREG_MEM_TYPE_MASK))
#define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
(((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
#define PCI_MAPREG_MEM_ADDR(mr) \
((mr) & PCI_MAPREG_MEM_ADDR_MASK)
#define PCI_MAPREG_MEM_SIZE(mr) \
(PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
#define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
#define PCI_MAPREG_MEM64_ADDR(mr) \
((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
#define PCI_MAPREG_MEM64_SIZE(mr) \
(PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
#define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
#define PCI_MAPREG_IO_ADDR(mr) \
((mr) & PCI_MAPREG_IO_ADDR_MASK)
#define PCI_MAPREG_IO_SIZE(mr) \
(PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
#define PCI_MAPREG_IO_ADDR_MASK 0xfffffffe
/*
* Cardbus CIS pointer (PCI rev. 2.1)
*/
#define PCI_CARDBUS_CIS_REG 0x28
/*
* Subsystem identification register; contains a vendor ID and a device ID.
* Types/macros for PCI_ID_REG apply.
* (PCI rev. 2.1)
*/
#define PCI_SUBSYS_ID_REG 0x2c
/*
* Expansion ROM Base Address register
* (PCI rev. 2.0)
*/
#define PCI_ROM_REG 0x30
#define PCI_ROM_ENABLE 0x00000001
#define PCI_ROM_ADDR_MASK 0xfffff800
#define PCI_ROM_ADDR(mr) \
((mr) & PCI_ROM_ADDR_MASK)
#define PCI_ROM_SIZE(mr) \
(PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr))
/*
* capabilities link list (PCI rev. 2.2)
*/
#define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
#define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
#define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
#define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
#define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
#define PCI_CAP_RESERVED 0x00
#define PCI_CAP_PWRMGMT 0x01
#define PCI_CAP_AGP 0x02
#define PCI_CAP_VPD 0x03
#define PCI_CAP_SLOTID 0x04
#define PCI_CAP_MSI 0x05
#define PCI_CAP_CPCI_HOTSWAP 0x06
#define PCI_CAP_PCIX 0x07
#define PCI_CAP_HT 0x08
#define PCI_CAP_VENDSPEC 0x09
#define PCI_CAP_DEBUGPORT 0x0a
#define PCI_CAP_CPCI_RSRCCTL 0x0b
#define PCI_CAP_HOTPLUG 0x0c
#define PCI_CAP_AGP8 0x0e
#define PCI_CAP_SECURE 0x0f
#define PCI_CAP_PCIEXPRESS 0x10
#define PCI_CAP_MSIX 0x11
#define PCI_CAP_SATA 0x12
/*
* Vital Product Data; access via capability pointer (PCI rev 2.2).
*/
#define PCI_VPD_ADDRESS_MASK 0x7fff
#define PCI_VPD_ADDRESS_SHIFT 16
#define PCI_VPD_ADDRESS(ofs) \
(((ofs) & PCI_VPD_ADDRESS_MASK) << PCI_VPD_ADDRESS_SHIFT)
#define PCI_VPD_DATAREG(ofs) ((ofs) + 4)
#define PCI_VPD_OPFLAG 0x80000000
/*
* Message Signaled Interrupts; access via capability pointer.
*/
#define PCI_MSI_MC 0x00
#define PCI_MSI_MC_C64 0x00800000
#define PCI_MSI_MC_MME 0x00700000
#define PCI_MSI_MC_MMC 0x000e0000
#define PCI_MSI_MC_MSIE 0x00010000
#define PCI_MSI_MA 0x04
#define PCI_MSI_MAU32 0x08
#define PCI_MSI_MD32 0x08
#define PCI_MSI_MD64 0x0c
/*
* Power Management Control Status Register; access via capability pointer.
*/
#define PCI_PMCSR 0x04
#define PCI_PMCSR_STATE_MASK 0x0003
#define PCI_PMCSR_STATE_D0 0x0000
#define PCI_PMCSR_STATE_D1 0x0001
#define PCI_PMCSR_STATE_D2 0x0002
#define PCI_PMCSR_STATE_D3 0x0003
#define PCI_PMCSR_PME_STATUS 0x8000
#define PCI_PMCSR_PME_EN 0x0100
/*
* HyperTransport; access via capability pointer.
*/
#define PCI_HT_CAP(cr) ((((cr) >> 27) < 0x08) ? \
(((cr) >> 27) & 0x1c) : (((cr) >> 27) & 0x1f))
#define PCI_HT_CAP_SLAVE 0x00
#define PCI_HT_CAP_HOST 0x04
#define PCI_HT_CAP_INTR 0x10
#define PCI_HT_CAP_MSI 0x15
#define PCI_HT_MSI_ENABLED 0x00010000
#define PCI_HT_MSI_FIXED 0x00020000
#define PCI_HT_MSI_FIXED_ADDR 0xfee00000UL
#define PCI_HT_MSI_ADDR 0x04
#define PCI_HT_MSI_ADDR_HI32 0x08
#define PCI_HT_INTR_DATA 0x04
/*
* PCI Express; access via capability pointer.
*/
#define PCI_PCIE_XCAP 0x00
#define PCI_PCIE_XCAP_SI 0x01000000
#define PCI_PCIE_XCAP_VER(x) (((x) >> 16) & 0x0f)
#define PCI_PCIE_DCAP 0x04
#define PCI_PCIE_DCSR 0x08
#define PCI_PCIE_DCSR_ERO 0x00000010
#define PCI_PCIE_DCSR_ENS 0x00000800
#define PCI_PCIE_DCSR_MPS 0x00007000
#define PCI_PCIE_DCSR_CEE 0x00010000
#define PCI_PCIE_DCSR_NFE 0x00020000
#define PCI_PCIE_DCSR_FEE 0x00040000
#define PCI_PCIE_DCSR_URE 0x00080000
#define PCI_PCIE_LCAP 0x0c
#define PCI_PCIE_LCSR 0x10
#define PCI_PCIE_LCSR_ASPM_L0S 0x00000001
#define PCI_PCIE_LCSR_ASPM_L1 0x00000002
#define PCI_PCIE_LCSR_RL 0x00000020
#define PCI_PCIE_LCSR_CCC 0x00000040
#define PCI_PCIE_LCSR_ES 0x00000080
#define PCI_PCIE_LCSR_ECPM 0x00000100
#define PCI_PCIE_LCSR_CLS 0x000f0000
#define PCI_PCIE_LCSR_CLS_2_5 0x00010000
#define PCI_PCIE_LCSR_CLS_5 0x00020000
#define PCI_PCIE_LCSR_CLS_8 0x00030000
#define PCI_PCIE_LCSR_CLS_16 0x00040000
#define PCI_PCIE_LCSR_CLS_32 0x00050000
#define PCI_PCIE_LCSR_LT 0x08000000
#define PCI_PCIE_LCSR_SCC 0x10000000
#define PCI_PCIE_SLCAP 0x14
#define PCI_PCIE_SLCAP_ABP 0x00000001
#define PCI_PCIE_SLCAP_PCP 0x00000002
#define PCI_PCIE_SLCAP_MSP 0x00000004
#define PCI_PCIE_SLCAP_AIP 0x00000008
#define PCI_PCIE_SLCAP_PIP 0x00000010
#define PCI_PCIE_SLCAP_HPS 0x00000020
#define PCI_PCIE_SLCAP_HPC 0x00000040
#define PCI_PCIE_SLCSR 0x18
#define PCI_PCIE_SLCSR_ABE 0x00000001
#define PCI_PCIE_SLCSR_PFE 0x00000002
#define PCI_PCIE_SLCSR_MSE 0x00000004
#define PCI_PCIE_SLCSR_PDE 0x00000008
#define PCI_PCIE_SLCSR_CCE 0x00000010
#define PCI_PCIE_SLCSR_HPE 0x00000020
#define PCI_PCIE_SLCSR_ABP 0x00010000
#define PCI_PCIE_SLCSR_PFD 0x00020000
#define PCI_PCIE_SLCSR_MSC 0x00040000
#define PCI_PCIE_SLCSR_PDC 0x00080000
#define PCI_PCIE_SLCSR_CC 0x00100000
#define PCI_PCIE_SLCSR_MS 0x00200000
#define PCI_PCIE_SLCSR_PDS 0x00400000
#define PCI_PCIE_SLCSR_LACS 0x01000000
#define PCI_PCIE_RCSR 0x1c
#define PCI_PCIE_DCSR2 0x28
#define PCI_PCIE_DCSR2_LTREN 0x00000400
#define PCI_PCIE_LCAP2 0x2c
#define PCI_PCIE_LCSR2 0x30
#define PCI_PCIE_LCSR2_TLS 0x0000000f
#define PCI_PCIE_LCSR2_TLS_2_5 0x00000001
#define PCI_PCIE_LCSR2_TLS_5 0x00000002
#define PCI_PCIE_LCSR2_TLS_8 0x00000003
#define PCI_PCIE_LCSR2_TLS_16 0x00000004
#define PCI_PCIE_LCSR2_TLS_32 0x00000005
/*
* PCI Express; enhanced capabilities
*/
#define PCI_PCIE_ECAP 0x100
#define PCI_PCIE_ECAP_ID(x) (((x) & 0x0000ffff))
#define PCI_PCIE_ECAP_VER(x) (((x) >> 16) & 0x0f)
#define PCI_PCIE_ECAP_NEXT(x) (((x) >> 20) & 0xffc)
#define PCI_PCIE_ECAP_LAST 0x0
/*
* Extended Message Signaled Interrupts; access via capability pointer.
*/
#define PCI_MSIX_MC_MSIXE 0x80000000
#define PCI_MSIX_MC_FM 0x40000000
#define PCI_MSIX_MC_TBLSZ_MASK 0x07ff0000
#define PCI_MSIX_MC_TBLSZ_SHIFT 16
#define PCI_MSIX_MC_TBLSZ(reg) \
(((reg) & PCI_MSIX_MC_TBLSZ_MASK) >> PCI_MSIX_MC_TBLSZ_SHIFT)
#define PCI_MSIX_TABLE 0x04
#define PCI_MSIX_TABLE_BIR 0x00000007
#define PCI_MSIX_TABLE_OFF ~(PCI_MSIX_TABLE_BIR)
#define PCI_MSIX_MA(i) ((i) * 16 + 0)
#define PCI_MSIX_MAU32(i) ((i) * 16 + 4)
#define PCI_MSIX_MD(i) ((i) * 16 + 8)
#define PCI_MSIX_VC(i) ((i) * 16 + 12)
#define PCI_MSIX_VC_MASK 0x00000001
/*
* Interrupt Configuration Register; contains interrupt pin and line.
*/
#define PCI_INTERRUPT_REG 0x3c
typedef u_int8_t pci_intr_pin_t;
typedef u_int8_t pci_intr_line_t;
#define PCI_INTERRUPT_PIN_SHIFT 8
#define PCI_INTERRUPT_PIN_MASK 0xff
#define PCI_INTERRUPT_PIN(icr) \
(((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
#define PCI_INTERRUPT_LINE_SHIFT 0
#define PCI_INTERRUPT_LINE_MASK 0xff
#define PCI_INTERRUPT_LINE(icr) \
(((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
#define PCI_MIN_GNT_SHIFT 16
#define PCI_MIN_GNT_MASK 0xff
#define PCI_MIN_GNT(icr) \
(((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
#define PCI_MAX_LAT_SHIFT 24
#define PCI_MAX_LAT_MASK 0xff
#define PCI_MAX_LAT(icr) \
(((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
#define PCI_INTERRUPT_PIN_NONE 0x00
#define PCI_INTERRUPT_PIN_A 0x01
#define PCI_INTERRUPT_PIN_B 0x02
#define PCI_INTERRUPT_PIN_C 0x03
#define PCI_INTERRUPT_PIN_D 0x04
#define PCI_INTERRUPT_PIN_MAX 0x04
/*
* Vital Product Data resource tags.
*/
struct pci_vpd_smallres {
uint8_t vpdres_byte0; /* length of data + tag */
/* Actual data. */
} __packed;
struct pci_vpd_largeres {
uint8_t vpdres_byte0;
uint8_t vpdres_len_lsb; /* length of data only */
uint8_t vpdres_len_msb;
/* Actual data. */
} __packed;
#define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
#define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7)
#define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf)
#define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */
#define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */
#define PCI_VPDRES_TYPE_END_TAG 0xf /* small */
#define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */
#define PCI_VPDRES_TYPE_VPD 0x10 /* large */
struct pci_vpd {
uint8_t vpd_key0;
uint8_t vpd_key1;
uint8_t vpd_len; /* length of data only */
/* Actual data. */
} __packed;
/*
* Recommended VPD fields:
*
* PN Part number of assembly
* FN FRU part number
* EC EC level of assembly
* MN Manufacture ID
* SN Serial Number
*
* Conditionally recommended VPD fields:
*
* LI Load ID
* RL ROM Level
* RM Alterable ROM Level
* NA Network Address
* DD Device Driver Level
* DG Diagnostic Level
* LL Loadable Microcode Level
* VI Vendor ID/Device ID
* FU Function Number
* SI Subsystem Vendor ID/Subsystem ID
*
* Additional VPD fields:
*
* Z0-ZZ User/Product Specific
*/
#endif /* _DEV_PCI_PCIREG_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_DEV_PCI_PCIVAR_H_
#define _OBSD_COMPAT_DEV_PCI_PCIVAR_H_
#include_next <dev/pci/pcivar.h>
#include <sys/rman.h>
typedef u_int32_t pcireg_t;
struct pci_matchid {
pci_vendor_id_t pm_vid;
pci_product_id_t pm_pid;
};
typedef struct {
int rid;
} pci_intr_handle_t;
#define pci_conf_read(pct, pcitag, reg) \
pci_read_config(SC_DEV_FOR_PCI, reg, sizeof(pcireg_t))
#define pci_conf_write(pct, pcitag, reg, val) \
pci_write_config(SC_DEV_FOR_PCI, reg, val, sizeof(pcireg_t))
#define pci_get_capability(pct, pcitag, capability, offset, value) \
pci_get_capability_openbsd(SC_DEV_FOR_PCI, capability, offset, value)
#define pci_mapreg_type(pct, pcitag, reg) \
pci_mapreg_type_openbsd(SC_DEV_FOR_PCI, reg)
#define pci_mapreg_map(pa, reg, type, flags, tagp, handlep, basep, sizep, maxsize) \
pci_mapreg_map_openbsd(SC_DEV_FOR_PCI, reg, type, flags, tagp, handlep, basep, sizep, maxsize)
#define pci_intr_establish(pa, ih, level, func, arg, what) \
pci_intr_establish_openbsd(SC_DEV_FOR_PCI, ih, level, func, arg, what)
#define pci_intr_string(...) NULL
static int
pci_get_capability_openbsd(device_t dev, int capability, int* offset, pcireg_t* value)
{
int res = pci_find_cap(dev, capability, offset);
if (res != 0)
return 0;
if (value)
*value = pci_read_config(dev, *offset, sizeof(pcireg_t));
return 1;
}
static pcireg_t
pci_mapreg_type_openbsd(device_t dev, int reg)
{
return (_PCI_MAPREG_TYPEBITS(pci_read_config(dev, reg, sizeof(pcireg_t))));
}
static int
pci_mapreg_map_openbsd(device_t dev, int reg, pcireg_t type, int flags,
bus_space_tag_t* tagp, bus_space_handle_t* handlep, bus_addr_t* basep,
bus_size_t* sizep, bus_size_t maxsize)
{
struct resource* res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &reg, RF_ACTIVE);
if (res == NULL)
return -1;
*tagp = rman_get_bustag(res);
*handlep = rman_get_bushandle(res);
if (basep != NULL)
*basep = rman_get_start(res);
if (sizep != NULL)
*sizep = rman_get_size(res);
return 0;
}
static int
pci_intr_map_msix(device_t dev, int vec, pci_intr_handle_t* ihp)
{
if (vec != 0)
return -1;
int count = 1;
ihp->rid = 1;
return pci_alloc_msix(dev, &count);
}
static int
pci_intr_map_msi(device_t dev, pci_intr_handle_t* ihp)
{
int count = 1;
ihp->rid = 1;
return pci_alloc_msi(dev, &count);
}
static void*
pci_intr_establish_openbsd(device_t dev, pci_intr_handle_t ih, int level,
int(*func)(void*), void* arg, const char* what)
{
struct resource* irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &ih.rid,
RF_ACTIVE | (ih.rid != 0 ? 0 : RF_SHAREABLE));
if (irq == NULL)
return NULL;
int flags = INTR_TYPE_NET;
if ((level & IPL_MPSAFE) != 0)
flags |= INTR_MPSAFE;
void* ihp = NULL;
bus_setup_intr(dev, irq, flags, NULL, func, arg, &ihp);
return ihp;
}
#endif /* _OBSD_COMPAT_DEV_PCI_PCIVAR_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_MACHINE_BUS_H_
#define _OBSD_COMPAT_MACHINE_BUS_H_
#include_next <machine/bus.h>
#include <sys/bus_dma.h>
#define BUS_DMA_READ (BUS_DMA_NOWRITE)
#define BUS_DMA_WRITE (0)
struct bus_dmamap_obsd {
bus_dma_tag_t _dmat;
bus_dmamap_t _dmamp;
int _error;
int dm_nsegs;
bus_dma_segment_t dm_segs[];
};
typedef struct bus_dmamap_obsd* bus_dmamap_obsd_t;
#define bus_dmamap_t bus_dmamap_obsd_t
static int
bus_dmamap_create_obsd(bus_dma_tag_t tag, bus_size_t maxsize,
int nsegments, bus_size_t maxsegsz, bus_size_t boundary, bus_size_t alignment,
int flags, bus_dmamap_t* dmamp, int no_alloc_map)
{
*dmamp = calloc(sizeof(struct bus_dmamap_obsd) + (sizeof(bus_dma_segment_t) * nsegments), 1);
if ((*dmamp) == NULL)
return ENOMEM;
int error = bus_dma_tag_create(tag, alignment, boundary,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
maxsize, nsegments, maxsegsz, flags, NULL, NULL,
&(*dmamp)->_dmat);
if (error != 0)
return error;
if (!no_alloc_map)
error = bus_dmamap_create((*dmamp)->_dmat, flags, &(*dmamp)->_dmamp);
return error;
}
#define bus_dmamap_create(tag, maxsize, nsegments, maxsegsz, boundary, flags, dmamp) \
bus_dmamap_create_obsd(tag, maxsize, nsegments, maxsegsz, boundary, 1, flags, dmamp, 0)
static void
bus_dmamap_destroy_obsd(bus_dma_tag_t tag, bus_dmamap_t dmam)
{
bus_dmamap_destroy(dmam->_dmat, dmam->_dmamp);
bus_dma_tag_destroy(dmam->_dmat);
_kernel_free(dmam);
}
#define bus_dmamap_destroy bus_dmamap_destroy_obsd
static void
bus_dmamap_load_obsd_callback(void* arg, bus_dma_segment_t* segs, int nseg, int error)
{
bus_dmamap_t dmam = (bus_dmamap_t)arg;
dmam->_error = error;
dmam->dm_nsegs = nseg;
memcpy(dmam->dm_segs, segs, nseg * sizeof(bus_dma_segment_t));
}
static int
bus_dmamap_load_obsd(bus_dma_tag_t tag, bus_dmamap_t dmam, void *buf, bus_size_t buflen, struct proc *p, int flags)
{
int error = bus_dmamap_load(dmam->_dmat, dmam->_dmamp, buf, buflen,
bus_dmamap_load_obsd_callback, dmam, flags | BUS_DMA_NOWAIT);
if (error != 0)
return error;
return dmam->_error;
}
#define bus_dmamap_load bus_dmamap_load_obsd
static int
bus_dmamap_load_mbuf_obsd(bus_dma_tag_t tag, bus_dmamap_t dmam, struct mbuf *chain, int flags)
{
return bus_dmamap_load_mbuf_sg(dmam->_dmat, dmam->_dmamp, chain,
&dmam->dm_segs, &dmam->dm_nsegs, flags);
}
#define bus_dmamap_load_mbuf bus_dmamap_load_mbuf_obsd
static void
bus_dmamap_unload_obsd(bus_dma_tag_t tag, bus_dmamap_t dmam)
{
bus_dmamap_unload(dmam->_dmat, dmam->_dmamp);
}
#define bus_dmamap_unload bus_dmamap_unload_obsd
static void
bus_dmamap_sync_obsd(bus_dma_tag_t tag, bus_dmamap_t dmam, int ops)
{
bus_dmamap_sync(dmam->_dmat, dmam->_dmamp, ops);
}
#define bus_dmamap_sync(tag, dmam, offset, size, ops) bus_dmamap_sync_obsd(tag, dmam, ops)
#endif /* _OBSD_COMPAT_MACHINE_BUS_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_NET_IF_H_
#define _OBSD_COMPAT_NET_IF_H_
#include_next <net/if.h>
#define IFF_RUNNING IFF_DRV_RUNNING
#endif /* _OBSD_COMPAT_NET_IF_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_NET_IF_VAR_H_
#define _OBSD_COMPAT_NET_IF_VAR_H_
#include_next <net/if_var.h>
static inline int
if_input_openbsd(if_t ifp, struct mbuf_list* ml)
{
if (ml_empty(ml))
return 0;
struct mbuf* mb = ml->ml_head, *next = NULL;
int status = 0;
while (mb != NULL) {
// if_input takes only the first packet, it ignores mb->m_nextpkt.
next = mb->m_nextpkt;
int status = if_input(ifp, mb);
if (status != 0)
break;
mb = next;
next = NULL;
}
if (next != NULL)
m_freem(next);
ml_init(ml);
return status;
}
#define if_input if_input_openbsd
static int
ifq_enqueue(struct ifaltq *ifq, struct mbuf *m)
{
IF_ENQUEUE(ifq, m);
return 0;
}
static struct mbuf*
ifq_dequeue(struct ifaltq *ifq)
{
struct mbuf* m = NULL;
IF_DEQUEUE(ifq, m);
return m;
}
#endif /* _OBSD_COMPAT_NET_IF_VAR_H_ */

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src/libs/compat/openbsd_network/compat/netinet/if_ether.h Normal file
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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_NETINET_IF_ETHER_H_
#define _OBSD_COMPAT_NETINET_IF_ETHER_H_
#include_next <netinet/if_ether.h>
#include <net/if_arp.h>
#include <net/ethernet.h>
#include "if_ethersubr.h"
static const u_int8_t etheranyaddr[ETHER_ADDR_LEN] =
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
#define ETHER_IS_EQ(a1, a2) (memcmp((a1), (a2), ETHER_ADDR_LEN) == 0)
#define ETHERTYPE_EAPOL ETHERTYPE_PAE
#endif /* _OBSD_COMPAT_NETINET_IF_ETHER_H_ */

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/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1982, 1989, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)if_ethersubr.c 8.1 (Berkeley) 6/10/93
* $FreeBSD$
*/
static inline u_int32_t
ether_crc32_le_update(u_int32_t crc, const u_int8_t *buf, size_t len)
{
static const u_int32_t crctab[] = {
0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac,
0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c,
0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c,
0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c
};
size_t i;
for (i = 0; i < len; i++) {
crc ^= buf[i];
crc = (crc >> 4) ^ crctab[crc & 0xf];
crc = (crc >> 4) ^ crctab[crc & 0xf];
}
return (crc);
}
static inline u_int32_t
ether_crc32_be_update(u_int32_t crc, const u_int8_t *buf, size_t len)
{
static const u_int8_t rev[] = {
0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf
};
static const u_int32_t crctab[] = {
0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9,
0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005,
0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61,
0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd
};
size_t i;
u_int8_t data;
for (i = 0; i < len; i++) {
data = buf[i];
crc = (crc << 4) ^ crctab[(crc >> 28) ^ rev[data & 0xf]];
crc = (crc << 4) ^ crctab[(crc >> 28) ^ rev[data >> 4]];
}
return (crc);
}

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#include <null.h>

29
src/libs/compat/openbsd_network/compat/sys/device.h Normal file
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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_DEVICE_H_
#define _OBSD_COMPAT_SYS_DEVICE_H_
#include <sys/firmware.h>
static inline int
loadfirmware(const char *name, u_char **bufp, size_t *buflen)
{
struct firmware* fw = firmware_get(name);
if (fw == NULL)
return -1;
*bufp = fw->data;
*buflen = fw->datasize;
// Caller takes ownership of data.
fw->data = NULL;
firmware_put(fw, 0);
return 0;
}
#endif /* _OBSD_COMPAT_SYS_DEVICE_H_ */

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src/libs/compat/openbsd_network/compat/sys/endian.h Normal file
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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_ENDIAN_H_
#define _OBSD_COMPAT_SYS_ENDIAN_H_
#include_next <sys/endian.h>
/* original BSD names */
#define betoh16(x) be16toh(x)
#define betoh32(x) be32toh(x)
#define betoh64(x) be64toh(x)
#define letoh16(x) le16toh(x)
#define letoh32(x) le32toh(x)
#define letoh64(x) le64toh(x)
#define swap16(x) bswap16(x)
#define swap32(x) bswap32(x)
#define swap64(x) bswap64(x)
#endif /* _OBSD_COMPAT_SYS_ENDIAN_H_ */

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src/libs/compat/openbsd_network/compat/sys/malloc.h Normal file
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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_MALLOC_H_
#define _OBSD_COMPAT_SYS_MALLOC_H_
#include_next <sys/malloc.h>
#define malloc(size, base, flags) kernel_malloc(size, base, flags)
#define free(addr, type, freedsize) _kernel_free(addr)
#define M_CANFAIL (0)
#endif /* _OBSD_COMPAT_SYS_MALLOC_H_ */

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/* $OpenBSD: uipc_mbuf.c,v 1.283 2022/02/22 01:15:01 guenther Exp $ */
/* $NetBSD: uipc_mbuf.c,v 1.15.4.1 1996/06/13 17:11:44 cgd Exp $ */
/*
* Copyright (c) 1982, 1986, 1988, 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)uipc_mbuf.c 8.2 (Berkeley) 1/4/94
*/
/*
* @(#)COPYRIGHT 1.1 (NRL) 17 January 1995
*
* NRL grants permission for redistribution and use in source and binary
* forms, with or without modification, of the software and documentation
* created at NRL provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgements:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* This product includes software developed at the Information
* Technology Division, US Naval Research Laboratory.
* 4. Neither the name of the NRL nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THE SOFTWARE PROVIDED BY NRL IS PROVIDED BY NRL AND CONTRIBUTORS ``AS
* IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NRL OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of the US Naval
* Research Laboratory (NRL).
*/
#define mq_len(_mq) ml_len(&(_mq)->mq_list)
#define mq_empty(_mq) ml_empty(&(_mq)->mq_list)
#define mq_full(_mq) (mq_len((_mq)) >= (_mq)->mq_maxlen)
#define mq_drops(_mq) ((_mq)->mq_drops)
#define mq_set_maxlen(_mq, _l) ((_mq)->mq_maxlen = (_l))
static struct mbuf *
m_dup_pkt(struct mbuf *m0, unsigned int adj, int wait)
{
struct mbuf *m;
int len;
KASSERT(m0->m_flags & M_PKTHDR);
len = m0->m_pkthdr.len + adj;
if (len > MAXMCLBYTES) /* XXX */
return (NULL);
m = m_get(wait, m0->m_type);
if (m == NULL)
return (NULL);
if (m_dup_pkthdr(m, m0, wait) != 0)
goto fail;
if (len > MHLEN) {
MCLGETL(m, wait, len);
if (!ISSET(m->m_flags, M_EXT))
goto fail;
}
m->m_len = m->m_pkthdr.len = len;
m_adj(m, adj);
m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
return (m);
fail:
m_freem(m);
return (NULL);
}
/*
* Compute the amount of space available after the end of data in an mbuf.
* Read-only clusters never have space available.
*/
static int
m_trailingspace(struct mbuf *m)
{
if (M_READONLY(m))
return 0;
KASSERT(M_DATABUF(m) + M_SIZE(m) >= (m->m_data + m->m_len));
return M_DATABUF(m) + M_SIZE(m) - (m->m_data + m->m_len);
}
static void
ml_init(struct mbuf_list *ml)
{
ml->ml_head = ml->ml_tail = NULL;
ml->ml_len = 0;
}
static void
ml_enqueue(struct mbuf_list *ml, struct mbuf *m)
{
if (ml->ml_tail == NULL)
ml->ml_head = ml->ml_tail = m;
else {
ml->ml_tail->m_nextpkt = m;
ml->ml_tail = m;
}
m->m_nextpkt = NULL;
ml->ml_len++;
}
static void
ml_enlist(struct mbuf_list *mla, struct mbuf_list *mlb)
{
if (!ml_empty(mlb)) {
if (ml_empty(mla))
mla->ml_head = mlb->ml_head;
else
mla->ml_tail->m_nextpkt = mlb->ml_head;
mla->ml_tail = mlb->ml_tail;
mla->ml_len += mlb->ml_len;
ml_init(mlb);
}
}
static struct mbuf *
ml_dequeue(struct mbuf_list *ml)
{
struct mbuf *m;
m = ml->ml_head;
if (m != NULL) {
ml->ml_head = m->m_nextpkt;
if (ml->ml_head == NULL)
ml->ml_tail = NULL;
m->m_nextpkt = NULL;
ml->ml_len--;
}
return (m);
}
static struct mbuf *
ml_dechain(struct mbuf_list *ml)
{
struct mbuf *m0;
m0 = ml->ml_head;
ml_init(ml);
return (m0);
}
static unsigned int
ml_purge(struct mbuf_list *ml)
{
struct mbuf *m, *n;
unsigned int len;
for (m = ml->ml_head; m != NULL; m = n) {
n = m->m_nextpkt;
m_freem(m);
}
len = ml->ml_len;
ml_init(ml);
return (len);
}
static unsigned int
ml_hdatalen(struct mbuf_list *ml)
{
struct mbuf *m;
m = ml->ml_head;
if (m == NULL)
return (0);
KASSERT(ISSET(m->m_flags, M_PKTHDR));
return (m->m_pkthdr.len);
}
/*
* mbuf queues
*/
static void
mq_init(struct mbuf_queue *mq, u_int maxlen, int ipl)
{
mtx_init(&mq->mq_mtx, ipl);
ml_init(&mq->mq_list);
mq->mq_maxlen = maxlen;
}
static int
mq_push(struct mbuf_queue *mq, struct mbuf *m)
{
struct mbuf *dropped = NULL;
mtx_enter(&mq->mq_mtx);
if (mq_len(mq) >= mq->mq_maxlen) {
mq->mq_drops++;
dropped = ml_dequeue(&mq->mq_list);
}
ml_enqueue(&mq->mq_list, m);
mtx_leave(&mq->mq_mtx);
if (dropped)
m_freem(dropped);
return (dropped != NULL);
}
static int
mq_enqueue(struct mbuf_queue *mq, struct mbuf *m)
{
int dropped = 0;
mtx_enter(&mq->mq_mtx);
if (mq_len(mq) < mq->mq_maxlen)
ml_enqueue(&mq->mq_list, m);
else {
mq->mq_drops++;
dropped = 1;
}
mtx_leave(&mq->mq_mtx);
if (dropped)
m_freem(m);
return (dropped);
}
static struct mbuf *
mq_dequeue(struct mbuf_queue *mq)
{
struct mbuf *m;
mtx_enter(&mq->mq_mtx);
m = ml_dequeue(&mq->mq_list);
mtx_leave(&mq->mq_mtx);
return (m);
}
static int
mq_enlist(struct mbuf_queue *mq, struct mbuf_list *ml)
{
struct mbuf *m;
int dropped = 0;
mtx_enter(&mq->mq_mtx);
if (mq_len(mq) < mq->mq_maxlen)
ml_enlist(&mq->mq_list, ml);
else {
dropped = ml_len(ml);
mq->mq_drops += dropped;
}
mtx_leave(&mq->mq_mtx);
if (dropped) {
while ((m = ml_dequeue(ml)) != NULL)
m_freem(m);
}
return (dropped);
}
static void
mq_delist(struct mbuf_queue *mq, struct mbuf_list *ml)
{
mtx_enter(&mq->mq_mtx);
*ml = mq->mq_list;
ml_init(&mq->mq_list);
mtx_leave(&mq->mq_mtx);
}
static struct mbuf *
mq_dechain(struct mbuf_queue *mq)
{
struct mbuf *m0;
mtx_enter(&mq->mq_mtx);
m0 = ml_dechain(&mq->mq_list);
mtx_leave(&mq->mq_mtx);
return (m0);
}
static unsigned int
mq_purge(struct mbuf_queue *mq)
{
struct mbuf_list ml;
mq_delist(mq, &ml);
return (ml_purge(&ml));
}
static unsigned int
mq_hdatalen(struct mbuf_queue *mq)
{
unsigned int hdatalen;
mtx_enter(&mq->mq_mtx);
hdatalen = ml_hdatalen(&mq->mq_list);
mtx_leave(&mq->mq_mtx);
return (hdatalen);
}

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_MBUF_H_
#define _OBSD_COMPAT_SYS_MBUF_H_
#include <sys/systm.h>
/* FreeBSD KASSERT */
#undef KASSERT
#define KASSERT KASSERT_FREEBSD
#include_next <sys/mbuf.h>
/* back to OpenBSD KASSERT */
#undef KASSERT
#define KASSERT KASSERT_OPENBSD
#include <sys/mutex.h>
#define ph_cookie PH_loc.ptr
#define M_READONLY(m) (0)
#define M_DATABUF(m) ((m)->m_flags & M_EXT ? (m)->m_ext.ext_buf : \
(m)->m_flags & M_PKTHDR ? (m)->m_pktdat : (m)->m_dat)
#define MAXMCLBYTES MJUM16BYTES
#define MCLGETL m_cljget
struct mbuf_list {
struct mbuf *ml_head;
struct mbuf *ml_tail;
u_int ml_len;
};
#define MBUF_LIST_INITIALIZER() { NULL, NULL, 0 }
#define ml_len(_ml) ((_ml)->ml_len)
#define ml_empty(_ml) ((_ml)->ml_len == 0)
struct mbuf_queue {
struct mutex mq_mtx;
struct mbuf_list mq_list;
u_int mq_maxlen;
u_int mq_drops;
};
/* FreeBSD methods not compatible with their OpenBSD counterparts */
#define m_defrag(mbuf, how) __m_defrag_unimplemented()
#include "mbuf-obsd.h"
#endif /* _OBSD_COMPAT_SYS_MBUF_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_MUTEX_H_
#define _OBSD_COMPAT_SYS_MUTEX_H_
#include_next <sys/mutex.h>
struct mutex_openbsd {
struct mtx mtx;
};
#define mutex mutex_openbsd
static inline void
mtx_init_openbsd(struct mutex* mtx, int wantipl)
{
mtx_init(&mtx->mtx, "OpenBSD mutex", NULL,
wantipl == IPL_NONE ? 0 : MTX_SPIN);
}
#define mtx_init(mutex, wantipl) mtx_init_openbsd(mutex, wantipl)
static inline void
mtx_enter(struct mutex* mtx)
{
mtx_lock(&mtx->mtx);
}
static inline void
mtx_leave(struct mutex* mtx)
{
mtx_unlock(&mtx->mtx);
}
#endif /* _OBSD_COMPAT_SYS_MUTEX_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_PARAM_H_
#define _OBSD_COMPAT_SYS_PARAM_H_
#include_next <sys/param.h>
/* #pragma mark - bit manipulation */
#define SET(t, f) ((t) |= (f))
#define CLR(t, f) ((t) &= ~(f))
#define ISSET(t, f) ((t) & (f))
#endif /* _OBSD_COMPAT_SYS_PARAM_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_REFCNT_H_
#define _OBSD_COMPAT_SYS_REFCNT_H_
#include <sys/systm.h>
struct refcnt {
int32 r_refs;
};
#define REFCNT_INITIALIZER() { .r_refs = 1 }
static void
refcnt_init(struct refcnt* r)
{
atomic_set(&r->r_refs, 1);
}
static void
refcnt_take(struct refcnt* r)
{
int32 refs;
refs = atomic_add(&r->r_refs, 1);
KASSERT(refs != 0);
(void)refs;
}
static int
refcnt_rele(struct refcnt* r)
{
int32 refs;
refs = atomic_add(&r->r_refs, -1) - 1;
KASSERT(refs >= 0);
if (refs == 0)
return 1;
return 0;
}
static void
refcnt_rele_wake(struct refcnt* r)
{
if (refcnt_rele(r))
wakeup_one(r);
}
static void
refcnt_finalize(struct refcnt* r, const char* wmesg)
{
refcnt_rele(r);
while (r->r_refs > 0)
tsleep(r, PWAIT, wmesg, 0);
}
#endif /* _OBSD_COMPAT_SYS_REFCNT_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_RWLOCK_H_
#define _OBSD_COMPAT_SYS_RWLOCK_H_
#include <sys/mutex.h>
struct rwlock_openbsd {
struct rw_lock lock;
};
#define rwlock rwlock_openbsd
static inline void
rw_init_flags(struct rwlock* rwl, const char* name, int flags)
{
rw_lock_init(&rwl->lock, name);
}
#define rw_init(rwl, name) rw_init_flags(rwl, name, 0)
#define RW_WRITE 0x0001UL
#define RW_READ 0x0002UL
#define RW_OPMASK 0x0007UL
#define RW_INTR 0x0010UL
static int
rw_enter(struct rwlock* rwl, int flags)
{
const int op = (flags & RW_OPMASK);
const int giant = mtx_owned(&Giant);
if (giant)
mtx_unlock(&Giant);
int status;
if (op == RW_WRITE)
status = rw_lock_write_lock(&rwl->lock);
else if (op == RW_READ)
status = rw_lock_read_lock(&rwl->lock);
else
panic("bad rw op");
if (giant)
mtx_lock(&Giant);
return status;
}
static inline int
rw_enter_write(struct rwlock* rwl)
{
return rw_enter(rwl, RW_WRITE);
}
static inline void
rw_exit(struct rwlock* rwl)
{
rw_lock_write_unlock(&rwl->lock);
}
static inline void
rw_assert_wrlock(struct rwlock* rwl)
{
#if KDEBUG
if (rwl->lock.holder != find_thread(NULL))
panic("rw_assert_wrlock failed!");
#endif
}
#endif /* _OBSD_COMPAT_SYS_RWLOCK_H_ */

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#include <stdint.h>

97
src/libs/compat/openbsd_network/compat/sys/systm.h Normal file
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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_SYSTM_H_
#define _OBSD_COMPAT_SYS_SYSTM_H_
#include_next <sys/systm.h>
#include <sys/kernel.h>
#include <int.h>
#define INFSLP UINT64_MAX
static inline void
explicit_bzero(void *buf, size_t len)
{
memset(buf, 0, len);
}
#define tsleep(identifier, priority, wmesg, timeout) \
msleep(identifier, &Giant, priority, wmesg, timeout)
#define tsleep_nsec(identifier, priority, wmesg, nsecs) \
tsleep(identifier, priority, wmesg, USEC_2_TICKS(nsecs / 1000))
#ifdef INVARIANTS
#define DIAGNOSTIC
#endif
#ifdef DIAGNOSTIC
#define KASSERT_OPENBSD(x) ASSERT_ALWAYS(x)
#define KASSERTMSG(x, format, args...) ASSERT_ALWAYS_PRINT(x, format, args)
#else
#define KASSERT_OPENBSD(x)
#define KASSERTMSG(x, format, args...)
#endif
#undef KASSERT
#define KASSERT KASSERT_OPENBSD
/* #pragma mark - interrupts */
#define IPL_NONE 0
#define IPL_HIGH 1
#define IPL_NET IPL_NONE
#define IPL_MPSAFE 0x100
#define splsoft() splraise(IPL_SOFT)
#define splsoftclock() splraise(IPL_SOFTCLOCK)
#define splsoftnet() splraise(IPL_SOFTNET)
#define splsofttty() splraise(IPL_SOFTTTY)
#define splbio() splraise(IPL_BIO)
#define splnet() splraise(IPL_NET)
#define spltty() splraise(IPL_TTY)
#define splvm() splraise(IPL_VM)
#define splaudio() splraise(IPL_AUDIO)
#define splclock() splraise(IPL_CLOCK)
#define splsched() splraise(IPL_SCHED)
#define splstatclock() splraise(IPL_STATCLOCK)
#define splhigh() splraise(IPL_HIGH)
static inline int
splraise(int ipl)
{
if (ipl == IPL_NONE)
return 0;
return disable_interrupts();
}
static inline void
splx(int ipl)
{
restore_interrupts(ipl);
}
static void
splassert(int ipl)
{
const int ints = are_interrupts_enabled();
if (ints && ipl != IPL_NONE)
panic("splassert: interrupts enabled but should be disabled");
else if (!ints && ipl == IPL_NONE)
panic("splassert: interrupts disabled but should be enabled");
}
#endif /* _OBSD_COMPAT_SYS_SYSTM_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_TASK_H_
#define _OBSD_COMPAT_SYS_TASK_H_
#include <sys/_task.h>
#include <sys/taskqueue.h>
struct taskq {
struct taskqueue* tq;
};
#define systq (struct taskq*)(0x1)
static void
task_set(struct task *t, void (*fn)(void *), void *arg)
{
t->ta_priority = 0;
t->ta_handler = fn;
t->ta_argument = arg;
}
static int
task_pending(struct task *t)
{
return t->ta_pending > 0;
}
static int
task_add(struct taskq* tasq, struct task *w)
{
struct taskqueue* tq = (tasq == systq) ? taskqueue_fast : tasq->tq;
if (tq == taskqueue_fast)
w->ta_flags |= TASK_NEEDSGIANT;
if (task_pending(w))
return 0;
return (taskqueue_enqueue_fast(tq, w) == 0);
}
static struct taskq*
taskq_create(const char* name, unsigned int nthreads, int ipl, unsigned int flags)
{
// For now, just use the system taskqueue.
return systq;
}
static int
task_del(struct taskq* tasq, struct task *w)
{
struct taskqueue* tq = (tasq == systq) ? taskqueue_fast : tasq->tq;
if (!task_pending(w))
return 0;
return (taskqueue_cancel(tq, w, NULL) == 0);
}
#endif /* _OBSD_COMPAT_SYS_TASK_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_TIME_H_
#define _OBSD_COMPAT_SYS_TIME_H_
#include_next <sys/time.h>
static inline time_t
getuptime()
{
struct timeval tv;
getmicrouptime(&tv);
return tv.tv_sec;
}
static inline void
USEC_TO_TIMEVAL(uint64_t us, struct timeval *tv)
{
tv->tv_sec = us / 1000000;
tv->tv_usec = us % 1000000;
}
static inline uint64_t
SEC_TO_NSEC(uint64_t sec)
{
if (sec > UINT64_MAX / 1000000000ULL)
return UINT64_MAX;
return sec * 1000000000ULL;
}
static inline uint64_t
MSEC_TO_NSEC(uint64_t ms)
{
if (ms > UINT64_MAX / 1000000ULL)
return UINT64_MAX;
return ms * 1000000ULL;
}
#endif /* _OBSD_COMPAT_SYS_TIME_H_ */

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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_TIMEOUT_H_
#define _OBSD_COMPAT_SYS_TIMEOUT_H_
#include <sys/callout.h>
struct timeout {
struct callout c;
};
static inline void
timeout_set(struct timeout *to, void (*fn)(void *), void *arg)
{
callout_init(&to->c, 0);
callout_reset(&to->c, -1, fn, arg);
}
static inline int
timeout_pending(struct timeout *to)
{
return callout_pending(&to->c);
}
static inline int
timeout_add_usec(struct timeout *to, int usec)
{
return callout_schedule(&to->c, USEC_2_TICKS(usec));
}
static inline int
timeout_add_msec(struct timeout *to, int msec)
{
return timeout_add_usec(to, msec * 1000);
}
static inline int
timeout_add_sec(struct timeout *to, int sec)
{
return timeout_add_msec(to, sec * 1000);
}
static inline int
timeout_del(struct timeout *to)
{
return callout_stop(&to->c);
}
#endif /* _OBSD_COMPAT_SYS_TIMEOUT_H_ */

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#include_next <sys/types.h>
#include <sys/endian.h>

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src/libs/compat/openbsd_network/compat/sys/ucred.h Normal file
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/*
* Copyright 2022, Haiku, Inc. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef _OBSD_COMPAT_SYS_UCRED_H_
#define _OBSD_COMPAT_SYS_UCRED_H_
#include <sys/priv.h>
#define suser(...) priv_check(NULL, PRIV_DRIVER)
#endif /* _OBSD_COMPAT_SYS_UCRED_H_ */