* add function to make pll flag adjustments
* bug fix of improper unit conversion git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42858 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -74,7 +74,7 @@ pll_limit_probe(pll_info *pll)
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pll->pllOutMax
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= B_LENDIAN_TO_HOST_INT32(
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firmwareInfo->info.ulMaxPixelClockPLL_Output) * 10;
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firmwareInfo->info.ulMaxPixelClockPLL_Output);
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if (tableMinor >= 4) {
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pll->lcdPllOutMin
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@ -108,11 +108,10 @@ pll_limit_probe(pll_info *pll)
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pll->minFeedbackDiv = FB_DIV_MIN;
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pll->maxFeedbackDiv = FB_DIV_LIMIT;
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// pll->pllInMin = B_LENDIAN_TO_HOST_INT16(
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// firmware_info->info.usMinPixelClockPLL_Input) * 10;
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//
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// pll->pllInMax = B_LENDIAN_TO_HOST_INT16(
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// firmware_info->info.usMaxPixelClockPLL_Input) * 10;
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pll->pllInMin = B_LENDIAN_TO_HOST_INT16(
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firmwareInfo->info.usMinPixelClockPLL_Input) * 10;
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pll->pllInMax = B_LENDIAN_TO_HOST_INT16(
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firmwareInfo->info.usMaxPixelClockPLL_Input) * 10;
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TRACE("%s: referenceFreq: %" B_PRIu16 "; pllOutMin: %" B_PRIu16 "; "
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" pllOutMax: %" B_PRIu16 "; pllInMin: %" B_PRIu16 ";"
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@ -128,17 +127,17 @@ pll_compute_post_divider(pll_info *pll)
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{
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radeon_shared_info &info = *gInfo->shared_info;
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// if RADEON_PLL_USE_POST_DIV
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// return pll->post_div;
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if ((pll->flags & PLL_USE_POST_DIV) != 0)
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return;
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uint32 vco;
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if (info.device_chipset < (RADEON_R700 | 0x70)) {
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if (0) // TODO : RADEON_PLL_IS_LCD
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if ((pll->flags & PLL_IS_LCD) != 0)
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vco = pll->lcdPllOutMin;
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else
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vco = pll->pllOutMin;
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} else {
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if (0) // TODO : RADEON_PLL_IS_LCD
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if ((pll->flags & PLL_IS_LCD) != 0)
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vco = pll->lcdPllOutMax;
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else
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vco = pll->pllOutMin;
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@ -271,11 +270,36 @@ union adjust_pixel_clock {
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};
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void
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pll_setup_flags(pll_info *pll, uint8 crtcID)
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{
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uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
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uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
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pll->flags |= PLL_PREFER_LOW_REF_DIV;
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if ((encoderFlags & ATOM_DEVICE_LCD_SUPPORT) != 0) {
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pll->flags |= PLL_IS_LCD;
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// TODO: Spread Spectrum PLL
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// use reference divider for spread spectrum
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if (0) { // SS enabled
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if (0) { // if we have a SS reference divider
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pll->flags |= PLL_USE_REF_DIV;
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//pll->reference_div = ss->refdiv;
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pll->flags |= PLL_USE_FRAC_FB_DIV;
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}
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}
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}
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if ((encoderFlags & ATOM_DEVICE_TV_SUPPORT) != 0)
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pll->flags |= PLL_PREFER_CLOSEST_LOWER;
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}
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status_t
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pll_adjust(pll_info *pll, uint8 crtcID)
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{
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pll->flags |= PLL_PREFER_LOW_REF_DIV;
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// TODO : PLL flags
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radeon_shared_info &info = *gInfo->shared_info;
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@ -396,10 +420,12 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
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pll->pixelClock = pixelClock;
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pll->id = pllID;
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pll_setup_flags(pll, crtcID);
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// set up any special flags
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pll_adjust(pll, crtcID);
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// get any needed clock adjustments, set reference/post dividers, set flags
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// get any needed clock adjustments, set reference/post dividers
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pll_compute(pll);
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// compute dividers, set flags
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// compute dividers
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int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
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union set_pixel_clock args;
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@ -84,9 +84,10 @@ struct pll_info {
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};
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status_t pll_limit_probe(pll_info *pll);
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status_t pll_adjust(pll_info *pll, uint8 crtcID);
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status_t pll_compute(pll_info *pll);
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void pll_setup_flags(pll_info *pll, uint8 crtcID);
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status_t pll_limit_probe(pll_info *pll);
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status_t pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID);
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