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module info/update

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8121 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-06-22 09:56:11 +00:00
parent 407c481dd1
commit 5f1edbfbd1
5 changed files with 46 additions and 284 deletions
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1
src/add-ons/accelerants/nvidia/engine/Jamfile
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@ -12,6 +12,7 @@ StaticLibrary nvidia_engine :
nv_dac.c
nv_dac2.c
nv_general.c
nv_agp.c
nv_globals.c
nv_i2c.c
nv_info.c

12
src/add-ons/accelerants/nvidia/engine/nv_bes.c
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@ -466,7 +466,7 @@ status_t nv_configure_bes
if (((my_ov.v_start + my_ov.height) - 1) > (ob->height - 1))
my_ov.height = (((ob->height - 1) - my_ov.v_start) + 1);
LOG(6,("Overlay: inputbuffer view (zoom) left %d, top %d, width %d, height %d\n",
LOG(4,("Overlay: inputbuffer view (zoom) left %d, top %d, width %d, height %d\n",
my_ov.h_start, my_ov.v_start, my_ov.width, my_ov.height));
/* save for nv_bes_calc_move_overlay() */
@ -478,9 +478,9 @@ status_t nv_configure_bes
/********************************
*** setup horizontal scaling ***
********************************/
LOG(6,("Overlay: total input picture width = %d, height = %d\n",
LOG(4,("Overlay: total input picture width = %d, height = %d\n",
(ob->width - si->overlay.myBufInfo[offset].slopspace), ob->height));
LOG(6,("Overlay: output picture width = %d, height = %d\n", ow->width, ow->height));
LOG(4,("Overlay: output picture width = %d, height = %d\n", ow->width, ow->height));
/* determine interval representation value, taking zoom into account */
if (ow->flags & B_OVERLAY_HORIZONTAL_FILTERING)
@ -668,9 +668,9 @@ status_t nv_configure_bes
*** log color keying info ***
*****************************/
LOG(6,("Overlay: key_red %d, key_green %d, key_blue %d, key_alpha %d\n",
LOG(4,("Overlay: key_red %d, key_green %d, key_blue %d, key_alpha %d\n",
ow->red.value, ow->green.value, ow->blue.value, ow->alpha.value));
LOG(6,("Overlay: mask_red %d, mask_green %d, mask_blue %d, mask_alpha %d\n",
LOG(4,("Overlay: mask_red %d, mask_green %d, mask_blue %d, mask_alpha %d\n",
ow->red.mask, ow->green.mask, ow->blue.mask, ow->alpha.mask));
@ -678,7 +678,7 @@ status_t nv_configure_bes
*** log flags ***
*****************/
LOG(6,("Overlay: ow->flags is $%08x\n",ow->flags));
LOG(4,("Overlay: ow->flags is $%08x\n",ow->flags));
/* BTW: horizontal and vertical filtering are fixed and turned on for GeForce overlay. */

275
src/add-ons/accelerants/nvidia/engine/nv_general.c
View File

@ -6,14 +6,11 @@
#define MODULE_BIT 0x00008000
#include <unistd.h>
#include "nv_std.h"
static status_t test_ram(void);
static status_t nvxx_general_powerup (void);
static status_t nv_general_bios_to_powergraphics(void);
static status_t nv_general_setup_agp(void);
static void nv_general_list_AGP_caps(agp_info ai);
static void nv_dump_configuration_space (void)
{
@ -1135,7 +1132,7 @@ static status_t nv_general_bios_to_powergraphics()
if (si->ps.secondary_head) DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeefff));
/* setup AGP */
nv_general_setup_agp();
nv_agp_setup();
/* turn screen one on */
head1_dpms(true, true, true);
@ -1143,276 +1140,6 @@ static status_t nv_general_bios_to_powergraphics()
return B_OK;
}
static status_t nv_general_setup_agp(void)
{
char path[MAXPATHLEN];
int agp_fd;
agp_info ai_card, ai_bridge;
uint8 rq_depth_card, rq_depth_bridge;
/* check for card's AGP capabilities and list them */
ai_card.config.agp_cap_id = CFGR(AGPREF);
ai_card.config.agp_stat = CFGR(AGPSTAT);
ai_card.config.agp_cmd = CFGR(AGPCMD);
if ((ai_card.config.agp_cap_id & 0x00ff0000) && ((ai_card.config.agp_cap_id & AGP_id_mask) == AGP_id))
{
LOG(4,("INIT: graphicscard is AGP type, supporting specification %d.%d;\n",
((ai_card.config.agp_cap_id & AGP_rev_major) >> AGP_rev_major_shift),
((ai_card.config.agp_cap_id & AGP_rev_minor) >> AGP_rev_minor_shift)));
nv_general_list_AGP_caps(ai_card);
/* check for motherboard AGP host bridge */
/* open the BeOS AGP kernel driver, the permissions aren't important */
strcpy(path, "/dev/graphics/agp/1");
agp_fd = open(path, B_READ_WRITE);
if (agp_fd < 0)
{
LOG(4,("INIT: cannot open AGP host bridge driver, aborting!\n"));
/* program card for PCI access */
CFGW(AGPCMD, 0x00000000);
return B_ERROR;
}
/* get host bridge info */
ioctl(agp_fd, GET_CONFIG, &ai_bridge);
LOG(4,("INIT: AGP host bridge found, vendorID $%04x, deviceID $%04x\n",
ai_bridge.dev.vendor_id, ai_bridge.dev.device_id));
if (ai_bridge.status != B_OK)
{
LOG(4,("INIT: host bridge failed to respond correctly, aborting AGP setup!\n"));
/* close host bridge driver */
close(agp_fd);
/* program card for PCI access */
CFGW(AGPCMD, 0x00000000);
return B_ERROR;
}
/* list host bridge capabilities */
LOG(4,("INIT: host bridge supports specification %d.%d;\n",
((ai_bridge.config.agp_cap_id & AGP_rev_major) >> AGP_rev_major_shift),
((ai_bridge.config.agp_cap_id & AGP_rev_minor) >> AGP_rev_minor_shift)));
nv_general_list_AGP_caps(ai_bridge);
/* abort if specified by user in nv.settings */
if (si->settings.force_pci)
{
/* user specified not to use AGP */
LOG(4,("INIT: forcing PCI mode (specified in nv.settings).\n"));
/* close host bridge driver */
close(agp_fd);
/* program card for PCI access */
CFGW(AGPCMD, 0x00000000);
return B_OK;
}
/* find out shared AGP capabilities of card and host bridge */
if ((ai_card.config.agp_stat & AGP_rate_rev) !=
(ai_bridge.config.agp_stat & AGP_rate_rev))
{
LOG(4,("INIT: compatibility problem detected, aborting AGP setup!\n"));
/* close host bridge driver */
close(agp_fd);
/* program card for PCI access */
CFGW(AGPCMD, 0x00000000);
return B_ERROR;
}
/* both card and bridge are set to the same standard */
/* (which is as it should be!) */
LOG(4,("INIT: enabling AGP\n"));
/* select highest AGP mode */
if (!(ai_bridge.config.agp_stat & AGP_rate_rev))
{
/* AGP 2.0 scheme applies */
if ((ai_card.config.agp_stat & AGP_2_4x) &&
(ai_bridge.config.agp_stat & AGP_2_4x))
{
LOG(4,("INIT: using AGP 2.0 4x mode\n"));
ai_card.config.agp_cmd = AGP_2_4x;
ai_bridge.config.agp_cmd = AGP_2_4x;
}
else
{
if ((ai_card.config.agp_stat & AGP_2_2x) &&
(ai_bridge.config.agp_stat & AGP_2_2x))
{
LOG(4,("INIT: using AGP 2.0 2x mode\n"));
ai_card.config.agp_cmd = AGP_2_2x;
ai_bridge.config.agp_cmd = AGP_2_2x;
}
else
{
LOG(4,("INIT: using AGP 2.0 1x mode\n"));
ai_card.config.agp_cmd = AGP_2_1x;
ai_bridge.config.agp_cmd = AGP_2_1x;
}
}
}
else
{
/* AGP 3.0 scheme applies */
if ((ai_card.config.agp_stat & AGP_3_8x) &&
(ai_bridge.config.agp_stat & AGP_3_8x))
{
LOG(4,("INIT: using AGP 3.0 8x mode\n"));
ai_card.config.agp_cmd = AGP_3_8x;
ai_bridge.config.agp_cmd = AGP_3_8x;
}
else
{
LOG(4,("INIT: using AGP 3.0 4x mode\n"));
ai_card.config.agp_cmd = AGP_3_4x;
ai_bridge.config.agp_cmd = AGP_3_4x;
}
}
/* activate sideband adressing if possible */
if ((ai_card.config.agp_stat & AGP_SBA) &&
(ai_bridge.config.agp_stat & AGP_SBA))
{
LOG(4,("INIT: enabling sideband adressing (SBA)\n"));
ai_card.config.agp_cmd |= AGP_SBA;
ai_bridge.config.agp_cmd |= AGP_SBA;
}
/* activate fast writes if possible */
if ((ai_card.config.agp_stat & AGP_FW) &&
(ai_bridge.config.agp_stat & AGP_FW))
{
LOG(4,("INIT: enabling fast writes (FW)\n"));
ai_card.config.agp_cmd |= AGP_FW;
ai_bridge.config.agp_cmd |= AGP_FW;
}
/* setup maximum request depth supported */
/* note:
* this is writable only in the graphics card */
rq_depth_card = ((ai_card.config.agp_stat & AGP_RQ) >> AGP_RQ_shift);
rq_depth_bridge = ((ai_bridge.config.agp_stat & AGP_RQ) >> AGP_RQ_shift);
if (rq_depth_card < rq_depth_bridge)
{
ai_card.config.agp_cmd |= (rq_depth_card << AGP_RQ_shift);
LOG(4,("INIT: max. AGP queued request depth will be set to %d\n",
(rq_depth_card + 1)));
}
else
{
ai_card.config.agp_cmd |= (rq_depth_bridge << AGP_RQ_shift);
LOG(4,("INIT: max. AGP queued request depth will be set to %d\n",
(rq_depth_bridge + 1)));
}
/* set the enable AGP bits */
/* note:
* the AGP standard defines that this bit may be written to the AGPCMD
* registers simultanously with the other bits if a single 32bit write
* to each register is used. */
ai_card.config.agp_cmd |= AGP_enable;
ai_bridge.config.agp_cmd |= AGP_enable;
/* finally program both the host bridge and the graphics card! */
/* note:
* the AGP standard defines that the host bridge should be enabled first. */
ioctl(agp_fd, SET_CONFIG, &ai_bridge);
CFGW(AGPCMD, ai_card.config.agp_cmd);
LOG(4,("INIT: graphics card AGPCMD register readback $%08x\n", CFGR(AGPCMD)));
/* close host bridge driver */
close(agp_fd);
}
else
{
LOG(4,("INIT: graphicscard is PCI type.\n"));
}
}
static void nv_general_list_AGP_caps(agp_info ai)
{
/*
list capabilities
*/
/* the mainboard and graphicscard determine AGP version used on power-up/reset */
if (!(ai.config.agp_stat & AGP_rate_rev))
{
/* AGP 2.0 scheme applies */
if (ai.config.agp_stat & AGP_2_1x)
{
LOG(4,("INIT: AGP 2.0 1x mode is available\n"));
}
if (ai.config.agp_stat & AGP_2_2x)
{
LOG(4,("INIT: AGP 2.0 2x mode is available\n"));
}
if (ai.config.agp_stat & AGP_2_4x)
{
LOG(4,("INIT: AGP 2.0 4x mode is available\n"));
}
}
else
{
/* AGP 3.0 scheme applies */
if (ai.config.agp_stat & AGP_3_4x)
{
LOG(4,("INIT: AGP 3.0 4x mode is available\n"));
}
if (ai.config.agp_stat & AGP_3_8x)
{
LOG(4,("INIT: AGP 3.0 8x mode is available\n"));
}
}
if (ai.config.agp_stat & AGP_FW) LOG(4,("INIT: fastwrite transfers are supported\n"));
if (ai.config.agp_stat & AGP_SBA) LOG(4,("INIT: sideband adressing is supported\n"));
LOG(4,("INIT: %d queued AGP requests can be handled.\n",
(((ai.config.agp_stat & AGP_RQ) >> AGP_RQ_shift) + 1)));
/*
list current settings
*/
LOG(4,("INIT: listing current active settings:\n"));
/* the mainboard and graphicscard determine AGP version used on power-up/reset */
if (!(ai.config.agp_stat & AGP_rate_rev))
{
/* AGP 2.0 scheme applies */
if (ai.config.agp_cmd & AGP_2_1x)
{
LOG(4,("INIT: AGP 2.0 1x mode is set\n"));
}
if (ai.config.agp_cmd & AGP_2_2x)
{
LOG(4,("INIT: AGP 2.0 2x mode is set\n"));
}
if (ai.config.agp_cmd & AGP_2_4x)
{
LOG(4,("INIT: AGP 2.0 4x mode is set\n"));
}
}
else
{
/* AGP 3.0 scheme applies */
if (ai.config.agp_cmd & AGP_3_4x)
{
LOG(4,("INIT: AGP 3.0 4x mode is set\n"));
}
if (ai.config.agp_cmd & AGP_3_8x)
{
LOG(4,("INIT: AGP 3.0 8x mode is set\n"));
}
}
if (ai.config.agp_cmd & AGP_FW) LOG(4,("INIT: fastwrite transfers are enabled\n"));
if (ai.config.agp_cmd & AGP_SBA) LOG(4,("INIT: sideband adressing is enabled\n"));
LOG(4,("INIT: max. AGP queued request depth is set to %d.\n",
(((ai.config.agp_cmd & AGP_RQ) >> AGP_RQ_shift) + 1)));
}
/* Check if mode virtual_size adheres to the cards _maximum_ contraints, and modify
* virtual_size to the nearest valid maximum for the mode on the card if not so.
* Also: check if virtual_width adheres to the cards granularity constraints, and

3
src/add-ons/accelerants/nvidia/engine/nv_proto.h
View File

@ -8,6 +8,9 @@ status_t nv_general_head_select(bool);
status_t nv_general_wait_retrace(void);
status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode);
/* AGP functions */
status_t nv_agp_setup(void);
/* apsed: logging macros */
#define MSG(args) do { /* if needed or si->settings with si NULL */ \
nv_log args; \

39
src/add-ons/kernel/drivers/graphics/nvidia/nv.settings
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@ -11,12 +11,43 @@
usebios false # if true rely on bios to coldstart the card: not functional (yet)
#memory 2 # in MB, override builtin memory size detection
hardcursor true # if true use on-chip cursor capabilities
#logmask 0x00000000 # nothing logged, except errors, is default
#logmask 0x80000000 # log card physical features
#logmask 0x80000000 # log following mask
#logmask 0x00000000 # nothing logged, is default
#logmask 0x08000604 # log overlay use in full
#logmask 0xffffffff # log everything
dumprom false # dump bios rom in ~/nv.rom: probably not functional yet
switchhead false # switch head assignment (dualhead cards only)
force_pci false # block AGP mode use if true (AGP cards only)
#--------- that's all.
#--------- that's all.
#logmask setup info:
#log level select:
#logmask 0x0000000x # lowest digit: bitmask to select logging level.
#log modules select:
#logmask 0xxxxxxxx0 # highest 7 digits: bitmask to select individual modules to log.
#log modules:
#logmask 0x00000100 # engine: agp
#logmask 0x00000200 # engine: bes
#logmask 0x00000400 # overlay
#logmask 0x00000800 # engine: support
#logmask 0x00001000 # engine: dac2
#logmask 0x00002000 # engine: info
#logmask 0x00004000 # engine: i2c
#logmask 0x00008000 # engine: general
#logmask 0x00010000 # engine: dac1
#logmask 0x00020000 # engine: crtc2
#logmask 0x00040000 # engine: crtc1
#logmask 0x00080000 # engine: acc
#logmask 0x00100000 # engine: brooktree tv
#logmask 0x00200000 # set displaymode
#logmask 0x00400000 # propose displaymode
#logmask 0x00800000 # init accelerant
#logmask 0x01000000 # get timing constraints
#logmask 0x02000000 # get mode info
#logmask 0x04000000 # get device info
#logmask 0x08000000 # get accelerant hook
#logmask 0x10000000 # engine management
#logmask 0x20000000 # cursor
#logmask 0x40000000 # acceleration