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boot/efi/arm: enable caches before jump to kernel

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Set bits 12 and 2 in SCTLR to enable i-cache and d-cache.
Set cacheability flags in TTBR0 to enable coherent page table walks.

Change-Id: I7f62255b9e49035524ecf87bed12a60dd405f3c8
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5178
Reviewed-by: Fredrik Holmqvist <fredrik.holmqvist@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
This commit is contained in:
David Karoly 2022-04-02 14:41:02 +02:00 committed by Adrien Destugues
parent fdaa57a70d
commit 5e6e52cfd4
1 changed files with 14 additions and 5 deletions
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19
src/system/boot/platform/efi/arch/arm/entry.S
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@ -67,7 +67,14 @@ _pl1_entry:
MCR p15, 0, r1, c8, c7, 0
// set TTBR0
MCR p15, 0, r5, c2, c0, 0
// cacheability attributes for the page tables are:
// Normal Memory, Inner/Outer Write-Back no Write-Allocate Cacheable
// Note that this relies on ARMv7 multiprocessing extensions
// on uniprocessors we need only the flag 0x01 i.e. Inner Cacheable
orr r5, r5, #0x59
mcr p15, 0, r5, c2, c0, 0
// initialize TTBCR to zero (no LPAE, use only TTBR0)
MCR p15, 0, r1, c2, c0, 2
@ -79,10 +86,12 @@ _pl1_entry:
mov r9, #0xffffffff
MCR p15, 0, r9, c3, c0, 0
// enable MMU
MRC p15, 0, r9, c1, c0, 0
orr r9, r9, #1
MCR p15, 0, r9, c1, c0, 0
// enable MMU and caches
mrc p15, 0, r9, c1, c0, 0
orr r9, r9, #0x00001000 // i-cache enabled
orr r9, r9, #0x00000004 // d-cache enabled
orr r9, r9, #0x00000001 // MMU enabled
mcr p15, 0, r9, c1, c0, 0
// set the kernel stack
mov sp,r3