verified CX25871 on NV11 working OK. Tweaked it's horizontal TVpicture position for PAL VCD and NTSC DVD to be indeed overscanning on all sides on a 4:3 TV. Enabled TVout upto/including NV15, still assuming TVout is on primary head for dualhead cards (will fix that asap I hope). Newer cards with BT/CX still only display the testimage if TVout is enabled. Fixed 'random horizontal position of TVout picture' on NV11.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14454 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
4daad1792e
commit
5cadaa5f63
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@ -612,8 +612,19 @@ static uint8 BT_init_NTSC720()
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// 6. Modify the RIVA (BeScreen) h_sync_start setting somewhat to get stable centered picture possible on TV AND!:
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// 7. Make sure you update the Chrontel horizontal Phase setting also then!
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buffer[7] = 0x28; //scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV
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//(guideline for initial setting: (h_blank_o / h_clk_0) * 63.55556uS = 9.5uS for NTSC)
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if (si->ps.tv_encoder.type >= CX25870)//set CX value
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{
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/* confirmed on NV11 using 4:3 TV */
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//fixme: checkout wstv.. (was 0x28)
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buffer[7] = 0x0c; //scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV
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//(guideline for initial setting: (h_blank_o / h_clk_0) * 63.55556uS = 9.5uS for NTSC)
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}
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else //set BT value
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{
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/* confirmed on TNT1 using 4:3 TV and 16:9 TV */
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buffer[7] = 0x28; //scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV
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//(guideline for initial setting: (h_blank_o / h_clk_0) * 63.55556uS = 9.5uS for NTSC)
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}
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buffer[8] = 0x18; //try-out; scope: checked against other modes, looks OK. v_blank_o: 1e active line ('pixel')
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buffer[9] = 0xf2; //v_active_o: = (active output lines + 2) / field (on TV)
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@ -704,12 +715,13 @@ static uint8 BT_init_PAL800_OS()
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if (si->ps.tv_encoder.type >= CX25870)//set CX value
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{
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//fixme if needed: (added 0x10 for BT)..
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buffer[7] = 0xf4;
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/* confirmed on NV11 using 4:3 TV */
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//fixme: checkout wstv.. (was 0xf4)
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buffer[7] = 0xf0;
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buffer[8] = 0x17;
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}
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else
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{ //set BT value
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else //set BT value
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{
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/* confirmed on TNT1 using 4:3 TV and 16:9 TV */
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buffer[7] = 0xd0;//scope: tuned. lsb h_blank_o: h_blank_o = horizontal viewport location on TV
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//(guideline for initial setting: (h_blank_o / h_clk_0) * 64.0uS = 10.0uS for PAL)
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@ -1530,7 +1542,8 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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}
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else
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{
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//fixme if needed (added 8 for BT)..
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/* confirmed on TNT1 using 4:3 TV */
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//fixme: checkout wstv..
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target->timing.h_sync_start = 848; //set for centered TV output
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target->timing.h_sync_end = 848+20; //delta is BT H_BLANKI
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}
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@ -1544,8 +1557,19 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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case NTSC720:
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/* (tested on TNT2 with BT869) */
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target->timing.h_display = 720; //H_ACTIVE
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target->timing.h_sync_start = 744; //do not change!
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target->timing.h_sync_end = 744+144; //delta is H_sync_pulse
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if (si->ps.tv_encoder.type <= BT869)
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{
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/* confirmed on TNT1 using 4:3 TV and 16:9 TV */
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target->timing.h_sync_start = 744; //do not change!
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target->timing.h_sync_end = 744+144; //delta is H_sync_pulse
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}
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else
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{
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/* confirmed on NV11 using 4:3 TV */
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//fixme: checkout wstv (was 744)..
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target->timing.h_sync_start = 728; //do not change!
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target->timing.h_sync_end = 728+160; //delta is H_sync_pulse
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}
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target->timing.h_total = 888; //BT H_TOTAL
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target->timing.v_display = 480; //V_ACTIVEI
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target->timing.v_sync_start = 490; //set for centered sync pulse
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@ -1581,27 +1605,24 @@ static status_t BT_start_tvout(void)
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set_crtc_owner(0);
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/* CAUTION:
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* On the TNT1, TV_SETUP and PLLSEL cannot be read (sometimes), but
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* write actions do succeed ... (tested on both ISA and PCI bus!) */
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* On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but
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* write actions do succeed ...
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* This is confirmed for both ISA and PCI access, on NV04 and NV11. */
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/* setup TVencoder connection */
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/* b1-0 = %01: encoder type is MASTER;
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* b24 = 1: VIP datapos is b0-7 */
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//fixme if needed: setup completely instead of relying on pre-init by BIOS..
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//(it seems to work OK on TNT1 although read reg. doesn't seem to work)
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//(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work)
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DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000002) | 0x01000001));
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/* tell GPU to use pixelclock from TVencoder instead of using internal source */
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/* (nessecary or display will 'shiver' on both TV and VGA.) */
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if (si->ps.secondary_head)
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{
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DACW(PLLSEL, (DACR(PLLSEL) | 0x00030000));
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}
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//fixme: assuming TVout is on primary head!!
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DACW(PLLSEL, 0x20030f00);
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else
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{
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/* confirmed PLLSEL to be a write-only register on TNT1! */
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DACW(PLLSEL, 0x00030700);
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}
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/* Set overscan color to 'black' */
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/* note:
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@ -1655,20 +1676,23 @@ status_t BT_stop_tvout(void)
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/* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */
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if (!(si->ps.slaved_tmds1)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03));
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//fixme: checkout...
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//CAUTION:
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//On the TNT1, these memadresses apparantly cannot be read (sometimes)!;
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//write actions do succeed though... (tested only on ISA bus yet..)
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/* CAUTION:
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* On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but
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* write actions do succeed ...
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* This is confirmed for both ISA and PCI access, on NV04 and NV11. */
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/* setup TVencoder connection */
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/* b1-0 = %00: encoder type is SLAVE;
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* b24 = 1: VIP datapos is b0-7 */
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//fixme if needed: setup completely instead of relying on pre-init by BIOS..
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//(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work)
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DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000003) | 0x01000000));
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/* tell GPU to use pixelclock from internal source instead of using TVencoder */
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DACW(PLLSEL, 0x10000700);
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if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));
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if (si->ps.secondary_head)
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DACW(PLLSEL, 0x30000f00);
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else
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DACW(PLLSEL, 0x10000700);
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/* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of
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* H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */
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@ -1771,8 +1795,8 @@ status_t BT_setmode(display_mode target)
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/* setup GPU CRTC timing */
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head1_set_timing(tv_target);
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//fixme: only testing singlehead cards for now...
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if (si->ps.secondary_head)
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//fixme: only testing older cards for now...
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if (si->ps.secondary_head && (si->ps.card_type > NV15))
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{
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BT_testsignal();
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return B_OK;
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@ -1341,8 +1341,11 @@ static status_t nv_general_bios_to_powergraphics()
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if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100);
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/* enable programmable PLLs */
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DACW(PLLSEL, 0x10000700);
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if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));
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/* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */
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if (si->ps.secondary_head)
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DACW(PLLSEL, 0x30000f00);
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else
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DACW(PLLSEL, 0x10000700);
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/* turn on DAC and make sure detection testsignal routing is disabled
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* (b16 = disable DAC,
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