Fake pci bus manager for m68k.
We will fake hardcoded devices depending on the platform. Hopefully that will help some generic drivers (ide) to work without major modification. Synced to r22648. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22655 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
François Revol
parent
188b43270e
commit
5bbe87abba
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SubDir HAIKU_TOP src add-ons kernel bus_managers pci arch m68k ;
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SubDirHdrs [ FDirName $(SUBDIR) $(DOTDOT) $(DOTDOT) ] ;
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UsePrivateHeaders kernel [ FDirName kernel arch $(TARGET_ARCH) ]
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[ FDirName kernel boot platform $(HAIKU_BOOT_PLATFORM) ] ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) amiga ] ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) apple ] ;
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SEARCH_SOURCE += [ FDirName $(SUBDIR) atari ] ;
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KernelStaticLibrary pci_arch_bus_manager :
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pci_controller.cpp
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pci_io.c
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# platforms
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pci_amiga.cpp
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pci_apple.cpp
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pci_atari.cpp
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;
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/*
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* Copyright 2007, François Revol <revol@free.fr>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#include "pci_amiga.h"
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#include <stdlib.h>
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#include <string.h>
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#include <KernelExport.h>
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status_t
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m68k_amiga_pci_controller_init(void)
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{
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return B_OK;
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}
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// #pragma mark - support functions
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/*
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* Copyright 2007, François Revol <revol@free.fr>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#ifndef PCI_BUS_MANAGER_M68K_AMIGA_H
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#define PCI_BUS_MANAGER_M68K_AMIGA_H
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#include <SupportDefs.h>
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status_t m68k_amiga_pci_controller_init(void);
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#endif // PCI_BUS_MANAGER_M68K_AMIGA_H
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/*
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* Copyright 2007, François Revol <revol@free.fr>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#include "pci_apple.h"
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#include <stdlib.h>
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#include <string.h>
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#include <KernelExport.h>
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status_t
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m68k_apple_pci_controller_init(void)
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{
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return B_OK;
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}
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// #pragma mark - support functions
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/*
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* Copyright 2007, François Revol <revol@free.fr>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#ifndef PCI_BUS_MANAGER_M68K_APPLE_H
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#define PCI_BUS_MANAGER_M68K_APPLE_H
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#include <SupportDefs.h>
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status_t m68k_apple_pci_controller_init(void);
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#endif // PCI_BUS_MANAGER_M68K_APPLE_H
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/*
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* Copyright 2007, François Revol <revol@free.fr>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#include "pci_atari.h"
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#include <stdlib.h>
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#include <string.h>
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#include <KernelExport.h>
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#include <PCI.h>
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#include "pci_controller.h"
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//XXX:find one and put in shared priv header!
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// 0x68xx is free according to pci.ids
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// 68fx (f=fake) x = 0:amiga, 1:apple, 2:atari
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#define FAKEV 0x68f2
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// bus number
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#define BN 0
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// default line size
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#define DLL 1
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// default latency
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#define DL 0
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// default bist
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#define DB 0
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#define PEI {0}
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#define INVV 0xffff //0x0000 ??
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#define INVD 0xffff
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struct fake_pci_device {
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pci_info info;
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};
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static struct fake_pci_device gFakePCIDevices[] = {
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{ {FAKEV, 0x0000, BN, 0, 0, 0, 0xff, PCI_host, PCI_bridge, DLL, DL, DB, 0, PEI }}, /* cpu */
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{ {FAKEV, 0x0001, BN, 1, 0, 0, 0xff, 0x68/*fake*/, PCI_processor, DLL, DL, DB, 0, PEI }}, /* cpu */
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{ {FAKEV, 0x0002, BN, 2, 0, 0, 0xff, PCI_display_other, PCI_display, DLL, DL, DB, 0, $FFFF8200, PEI }}, /* gfx */
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{ {FAKEV, 0x0003, BN, 3, 0, 0, 0xff, PCI_ide, PCI_mass_storage, DLL, DL, DB, 0, $FFF00000, PEI }}, /* ide */
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{ {FAKEV, 0x0004, BN, 4, 0, 0, 0xff, PCI_scsi, PCI_mass_storage, DLL, DL, DB, 0, PEI }}, /* scsi */
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{ {FAKEV, 0x0005, BN, 5, 0, 0, 0xff, 0x, PCI_multimedia, DLL, DL, DB, 0x00, 0, $FFFF8900, PEI }}, /* snd */
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//UART ?
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//centronics?
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{ {INVV, INVD} }
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};
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#define FAKE_DEVICES_COUNT ((sizeof(gFakePCIDevices)/sizeof(struct fake_pci_device)-1)
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#define out8rb(address, value) m68k_out8((vuint8*)(address), value)
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#define out16rb(address, value) m68k_out16_reverse((vuint16*)(address), value)
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#define out32rb(address, value) m68k_out32_reverse((vuint32*)(address), value)
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#define in8rb(address) m68k_in8((const vuint8*)(address))
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#define in16rb(address) m68k_in16_reverse((const vuint16*)(address))
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#define in32rb(address) m68k_in32_reverse((const vuint32*)(address))
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static int m68k_atari_enable_config(struct m68k_atari_host_bridge *bridge,
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uint8 bus, uint8 slot, uint8 function, uint8 offset);
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static status_t m68k_atari_read_pci_config(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 offset, uint8 size, uint32 *value);
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static status_t m68k_atari_write_pci_config(void *cookie, uint8 bus,
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uint8 device, uint8 function, uint8 offset, uint8 size,
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uint32 value);
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static status_t m68k_atari_get_max_bus_devices(void *cookie, int32 *count);
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static status_t m68k_atari_read_pci_irq(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 pin, uint8 *irq);
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static status_t m68k_atari_write_pci_irq(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 pin, uint8 irq);
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static pci_controller sM68kAtariPCIController = {
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m68k_atari_read_pci_config,
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m68k_atari_write_pci_config,
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m68k_atari_get_max_bus_devices,
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m68k_atari_read_pci_irq,
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m68k_atari_write_pci_irq,
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};
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static status_t
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m68k_atari_read_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function,
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uint8 offset, uint8 size, uint32 *value)
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{
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struct fake_pci_device *devices = (struct fake_pci_device *)cookie;
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struct fake_pci_device *dev;
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if (bus != 0)
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return EINVAL;
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if (device >= FAKE_DEVICES_COUNT)
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return EINVAL;
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if (function != 0)
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return EINVAL;
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dev = &devices[device];
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#define O(pn,n,s) \
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case pn: \
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if (size != s) { \
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panic("invalid pci config size %d for offset %d", size, offset); \
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return EINVAL; \
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*value = dev->n; \
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return B_OK
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if (1) {
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switch (offset) {
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O(PCI_vendor_id, vendor_id, 2);
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O(PCI_device_id, device_id, 2);
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O(PCI_revision, revision, 1);
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O(PCI_class_api, class_api, 1);
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O(PCI_class_sub, class_sub, 1);
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O(PCI_class_base, class_base, 1);
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O(PCI_line_size, line_size, 1);
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O(PCI_latency, latency, 1);
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O(PCI_header_type, header_type, 1);
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O(PCI_bist, bist, 1);
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}
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}
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//#undef O
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#if 0
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#define PCI_command 0x04 /* (2 byte) command */
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#define PCI_status 0x06 /* (2 byte) status */
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#endif
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if (dev->header_type == 0x00 || dev->header_type == 0x01) {
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switch (offset) {
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case PCI_base_registers:
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return EINVAL;
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O(PCI_interrupt_line, h0.interrupt_line, 1);
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O(PCI_interrupt_pin, h0.interrupt_pin, 1);
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default:
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break;
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}
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if (dev->header_type == 0x00) {
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switch (offset) {
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default:
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break;
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}
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if (dev->header_type == 0x01) {
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switch (offset) {
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O(PCI_primary_bus, h1.primary_bus, 1);
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O(PCI_secondary_bus, h1.secondary_bus, 1);
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O(PCI_subordinate_bus, h1.subordinate_bus, 1);
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O(PCI_secondary_latency, h1.secondary_latency, 1);
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default:
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break;
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}
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*value = 0xffffffff;
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panic("invalid pci config offset %d", offset);
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return EINVAL;
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//return B_OK;
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}
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static status_t m68k_atari_write_pci_config(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 offset, uint8 size, uint32 value)
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{
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#if 0
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if (m68k_atari_enable_config(bridge, bus, device, function, offset)) {
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switch (size) {
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case 1:
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out8rb(caoff, (uint8)value);
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(void)in8rb(caoff);
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break;
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case 2:
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out16rb(caoff, (uint16)value);
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(void)in16rb(caoff);
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break;
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case 4:
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out32rb(caoff, value);
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(void)in32rb(caoff);
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break;
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}
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}
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#endif
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panic("write pci config dev %d offset %d", device, offset);
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return B_OK;
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}
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static status_t m68k_atari_get_max_bus_devices(void *cookie, int32 *count)
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{
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*count = 32;
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return B_OK;
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}
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static status_t m68k_atari_read_pci_irq(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 pin, uint8 *irq)
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{
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return B_ERROR;
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}
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static status_t m68k_atari_write_pci_irq(void *cookie, uint8 bus, uint8 device,
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uint8 function, uint8 pin, uint8 irq)
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{
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return B_ERROR;
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}
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// #pragma mark -
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static int
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m68k_atari_enable_config(struct m68k_atari_host_bridge *bridge, uint8 bus,
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uint8 slot, uint8 function, uint8 offset)
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{
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// uint32 pass;
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// if (resource_int_value(device_get_name(sc->sc_dev),
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// device_get_unit(sc->sc_dev), "skipslot", &pass) == 0) {
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// if (pass == slot)
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// return (0);
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// }
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uint32 cfgval;
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if (bridge->bus == bus) {
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/*
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* No slots less than 11 on the primary bus
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*/
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if (slot < 11)
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return (0);
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cfgval = (1 << slot) | (function << 8) | (offset & 0xfc);
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} else {
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cfgval = (bus << 16) | (slot << 11) | (function << 8) |
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(offset & 0xfc) | 1;
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}
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do {
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out32rb(bridge->address_registers, cfgval);
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} while (in32rb(bridge->address_registers) != cfgval);
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return (1);
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}
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// #pragma mark -
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status_t
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m68k_atari_pci_controller_init(void)
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{
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status_t error = pci_controller_add(&sM68kAtariPCIController, /*cookie*/);
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/* if (error != B_OK)
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free(bridge);*/
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return error;
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}
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// #pragma mark - support functions
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/*
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* Copyright 2007, François Revol <revol@free.fr>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#ifndef PCI_BUS_MANAGER_M68K_ATARI_H
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#define PCI_BUS_MANAGER_M68K_ATARI_H
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#include <SupportDefs.h>
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status_t m68k_atari_pci_controller_init(void);
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#endif // PCI_BUS_MANAGER_M68K_ATARI_H
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/*
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* Copyright 2006, Ingo Weinhold <bonefish@cs.tu-berlin.de>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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#ifndef PCI_BUS_MANAGER_PPC_OPEN_FIRMWARE_PRIV_H
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#define PCI_BUS_MANAGER_PPC_OPEN_FIRMWARE_PRIV_H
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#include <stdlib.h>
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#include <string.h>
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#include <SupportDefs.h>
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struct StringArrayPropertyValue;
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// implementations
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status_t ppc_openfirmware_probe_uninorth(int deviceNode,
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const StringArrayPropertyValue &compatibleValue);
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// property support
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struct PropertyValue {
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PropertyValue()
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: value(NULL)
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{
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}
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~PropertyValue()
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{
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free(value);
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}
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char *value;
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int length;
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};
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struct StringArrayPropertyValue : PropertyValue {
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char *NextElement(int &cookie) const;
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bool ContainsElement(const char *value) const;
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};
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status_t openfirmware_get_property(int package, const char *propertyName,
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PropertyValue &value);
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#endif // PCI_BUS_MANAGER_PPC_OPEN_FIRMWARE_PRIV_H
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/*
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* Copyright 2006, Ingo Weinhold <bonefish@cs.tu-berlin.de>.
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* All rights reserved. Distributed under the terms of the MIT License.
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*/
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/*-
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* Copyright (C) 2002 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <KernelExport.h>
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#include <platform/openfirmware/devices.h>
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#include <platform/openfirmware/openfirmware.h>
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#include <platform/openfirmware/pci.h>
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#include "pci_controller.h"
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#include "pci_io.h"
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#include "pci_openfirmware_priv.h"
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struct uninorth_range {
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uint32 pci_hi;
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uint32 pci_mid;
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uint32 pci_lo;
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uint32 host;
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uint32 size_hi;
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uint32 size_lo;
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};
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struct uninorth_host_bridge {
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int device_node;
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addr_t address_registers;
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addr_t data_registers;
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uint32 bus;
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struct uninorth_range ranges[6];
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int range_count;
|
||||
};
|
||||
|
||||
|
||||
#define out8rb(address, value) ppc_out8((vuint8*)(address), value)
|
||||
#define out16rb(address, value) ppc_out16_reverse((vuint16*)(address), value)
|
||||
#define out32rb(address, value) ppc_out32_reverse((vuint32*)(address), value)
|
||||
#define in8rb(address) ppc_in8((const vuint8*)(address))
|
||||
#define in16rb(address) ppc_in16_reverse((const vuint16*)(address))
|
||||
#define in32rb(address) ppc_in32_reverse((const vuint32*)(address))
|
||||
|
||||
|
||||
static int uninorth_enable_config(struct uninorth_host_bridge *bridge,
|
||||
uint8 bus, uint8 slot, uint8 function, uint8 offset);
|
||||
|
||||
static status_t uninorth_read_pci_config(void *cookie, uint8 bus, uint8 device,
|
||||
uint8 function, uint8 offset, uint8 size, uint32 *value);
|
||||
static status_t uninorth_write_pci_config(void *cookie, uint8 bus,
|
||||
uint8 device, uint8 function, uint8 offset, uint8 size,
|
||||
uint32 value);
|
||||
static status_t uninorth_get_max_bus_devices(void *cookie, int32 *count);
|
||||
static status_t uninorth_read_pci_irq(void *cookie, uint8 bus, uint8 device,
|
||||
uint8 function, uint8 pin, uint8 *irq);
|
||||
static status_t uninorth_write_pci_irq(void *cookie, uint8 bus, uint8 device,
|
||||
uint8 function, uint8 pin, uint8 irq);
|
||||
|
||||
static pci_controller sUniNorthPCIController = {
|
||||
uninorth_read_pci_config,
|
||||
uninorth_write_pci_config,
|
||||
uninorth_get_max_bus_devices,
|
||||
uninorth_read_pci_irq,
|
||||
uninorth_write_pci_irq,
|
||||
};
|
||||
|
||||
|
||||
static status_t
|
||||
uninorth_read_pci_config(void *cookie, uint8 bus, uint8 device, uint8 function,
|
||||
uint8 offset, uint8 size, uint32 *value)
|
||||
{
|
||||
uninorth_host_bridge *bridge = (uninorth_host_bridge*)cookie;
|
||||
|
||||
addr_t caoff = bridge->data_registers + (offset & 0x07);
|
||||
|
||||
if (uninorth_enable_config(bridge, bus, device, function, offset) != 0) {
|
||||
switch (size) {
|
||||
case 1:
|
||||
*value = in8rb(caoff);
|
||||
break;
|
||||
case 2:
|
||||
*value = in16rb(caoff);
|
||||
break;
|
||||
case 4:
|
||||
*value = in32rb(caoff);
|
||||
break;
|
||||
default:
|
||||
*value = 0xffffffff;
|
||||
break;
|
||||
}
|
||||
} else
|
||||
*value = 0xffffffff;
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
static status_t uninorth_write_pci_config(void *cookie, uint8 bus, uint8 device,
|
||||
uint8 function, uint8 offset, uint8 size, uint32 value)
|
||||
{
|
||||
uninorth_host_bridge *bridge = (uninorth_host_bridge*)cookie;
|
||||
|
||||
addr_t caoff = bridge->data_registers + (offset & 0x07);
|
||||
|
||||
if (uninorth_enable_config(bridge, bus, device, function, offset)) {
|
||||
switch (size) {
|
||||
case 1:
|
||||
out8rb(caoff, (uint8)value);
|
||||
(void)in8rb(caoff);
|
||||
break;
|
||||
case 2:
|
||||
out16rb(caoff, (uint16)value);
|
||||
(void)in16rb(caoff);
|
||||
break;
|
||||
case 4:
|
||||
out32rb(caoff, value);
|
||||
(void)in32rb(caoff);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
static status_t uninorth_get_max_bus_devices(void *cookie, int32 *count)
|
||||
{
|
||||
*count = 32;
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
static status_t uninorth_read_pci_irq(void *cookie, uint8 bus, uint8 device,
|
||||
uint8 function, uint8 pin, uint8 *irq)
|
||||
{
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
|
||||
static status_t uninorth_write_pci_irq(void *cookie, uint8 bus, uint8 device,
|
||||
uint8 function, uint8 pin, uint8 irq)
|
||||
{
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
|
||||
// #pragma mark -
|
||||
|
||||
|
||||
static int
|
||||
uninorth_enable_config(struct uninorth_host_bridge *bridge, uint8 bus,
|
||||
uint8 slot, uint8 function, uint8 offset)
|
||||
{
|
||||
// uint32 pass;
|
||||
// if (resource_int_value(device_get_name(sc->sc_dev),
|
||||
// device_get_unit(sc->sc_dev), "skipslot", &pass) == 0) {
|
||||
// if (pass == slot)
|
||||
// return (0);
|
||||
// }
|
||||
|
||||
uint32 cfgval;
|
||||
if (bridge->bus == bus) {
|
||||
/*
|
||||
* No slots less than 11 on the primary bus
|
||||
*/
|
||||
if (slot < 11)
|
||||
return (0);
|
||||
|
||||
cfgval = (1 << slot) | (function << 8) | (offset & 0xfc);
|
||||
} else {
|
||||
cfgval = (bus << 16) | (slot << 11) | (function << 8) |
|
||||
(offset & 0xfc) | 1;
|
||||
}
|
||||
|
||||
do {
|
||||
out32rb(bridge->address_registers, cfgval);
|
||||
} while (in32rb(bridge->address_registers) != cfgval);
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
||||
|
||||
// #pragma mark -
|
||||
|
||||
status_t
|
||||
ppc_openfirmware_probe_uninorth(int deviceNode,
|
||||
const StringArrayPropertyValue &compatibleValue)
|
||||
{
|
||||
if (!compatibleValue.ContainsElement("uni-north"))
|
||||
return B_ERROR;
|
||||
|
||||
uint32 reg[2];
|
||||
if (of_getprop(deviceNode, "reg", reg, sizeof(reg)) < 8)
|
||||
return B_ERROR;
|
||||
|
||||
uint32 busrange[2];
|
||||
if (of_getprop(deviceNode, "bus-range", busrange, sizeof(busrange)) != 8)
|
||||
return B_ERROR;
|
||||
|
||||
uninorth_host_bridge *bridge
|
||||
= (uninorth_host_bridge*)malloc(sizeof(uninorth_host_bridge));
|
||||
if (!bridge)
|
||||
return B_NO_MEMORY;
|
||||
|
||||
bridge->device_node = deviceNode;
|
||||
bridge->address_registers = reg[0] + 0x800000;
|
||||
bridge->data_registers = reg[0] + 0xc00000;
|
||||
bridge->bus = busrange[0];
|
||||
// TODO: Check whether address and data registers have already been mapped by
|
||||
// the Open Firmware. If not, map them ourselves.
|
||||
|
||||
memset(bridge->ranges, 0, sizeof(bridge->ranges));
|
||||
int bytesRead = of_getprop(deviceNode, "ranges", bridge->ranges,
|
||||
sizeof(bridge->ranges));
|
||||
|
||||
if (bytesRead < 0) {
|
||||
dprintf("ppc_openfirmware_probe_uninorth: Could not get ranges.\n");
|
||||
return B_ERROR;
|
||||
}
|
||||
bridge->range_count = bytesRead / sizeof(uninorth_range);
|
||||
|
||||
uninorth_range *ioRange = NULL;
|
||||
uninorth_range *memoryRanges[2];
|
||||
int memoryRangeCount = 0;
|
||||
|
||||
for (int i = 0; i < bridge->range_count; i++) {
|
||||
uninorth_range *range = bridge->ranges + i;
|
||||
switch (range->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
|
||||
case OFW_PCI_PHYS_HI_SPACE_CONFIG:
|
||||
break;
|
||||
case OFW_PCI_PHYS_HI_SPACE_IO:
|
||||
ioRange = range;
|
||||
break;
|
||||
case OFW_PCI_PHYS_HI_SPACE_MEM32:
|
||||
memoryRanges[memoryRangeCount++] = range;
|
||||
break;
|
||||
case OFW_PCI_PHYS_HI_SPACE_MEM64:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (ioRange == NULL) {
|
||||
dprintf("ppc_openfirmware_probe_uninorth: Can't find io range.\n");
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
if (memoryRangeCount == 0) {
|
||||
dprintf("ppc_openfirmware_probe_uninorth: Can't find mem ranges.\n");
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
status_t error = pci_controller_add(&sUniNorthPCIController, bridge);
|
||||
if (error != B_OK)
|
||||
free(bridge);
|
||||
return error;
|
||||
}
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
#include "pci_controller.h"
|
||||
|
||||
#include <arch_platform.h>
|
||||
|
||||
#include "pci_priv.h"
|
||||
|
||||
/*
|
||||
* As we don't have any real PCI bus in any of the supported m68k platforms,
|
||||
* we fake one, with hardcoded devices.
|
||||
*/
|
||||
|
||||
#include "amiga/pci_amiga.h"
|
||||
#include "apple/pci_apple.h"
|
||||
#include "atari/pci_atari.h"
|
||||
|
||||
|
||||
status_t
|
||||
pci_controller_init(void)
|
||||
{
|
||||
switch (PPCPlatform::Default()->PlatformType()) {
|
||||
/* case M68K_PLATFORM_AMIGA:
|
||||
return m68k_amiga_pci_controller_init();
|
||||
break;
|
||||
case M68K_PLATFORM_APPLE:
|
||||
return m68k_apple_pci_controller_init();
|
||||
break;*/
|
||||
case M68K_PLATFORM_ATARI:
|
||||
return m68k_atari_pci_controller_init();
|
||||
break;
|
||||
default:
|
||||
return EINVAL;
|
||||
}
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
void *
|
||||
pci_ram_address(const void *physical_address_in_system_memory)
|
||||
{
|
||||
return (void *)physical_address_in_system_memory;
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
#include "pci_io.h"
|
||||
#include "pci_priv.h"
|
||||
|
||||
status_t
|
||||
pci_io_init()
|
||||
{
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
uint8
|
||||
pci_read_io_8(int mapped_io_addr)
|
||||
{
|
||||
return m68k_in8((vuint8*)mapped_io_addr);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_write_io_8(int mapped_io_addr, uint8 value)
|
||||
{
|
||||
m68k_out8((vuint8*)mapped_io_addr, value);
|
||||
}
|
||||
|
||||
|
||||
uint16
|
||||
pci_read_io_16(int mapped_io_addr)
|
||||
{
|
||||
return m68k_in16((vuint16*)mapped_io_addr);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_write_io_16(int mapped_io_addr, uint16 value)
|
||||
{
|
||||
m68k_out16((vuint16*)mapped_io_addr, value);
|
||||
}
|
||||
|
||||
|
||||
uint32
|
||||
pci_read_io_32(int mapped_io_addr)
|
||||
{
|
||||
return m68k_in32((vuint32*)mapped_io_addr);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
pci_write_io_32(int mapped_io_addr, uint32 value)
|
||||
{
|
||||
m68k_out32((vuint32*)mapped_io_addr, value);
|
||||
}
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright 2006, Ingo Weinhold <bonefish@cs.tu-berlin.de>.
|
||||
* All rights reserved. Distributed under the terms of the MIT License.
|
||||
*/
|
||||
|
||||
#ifndef PCI_BUS_MANAGER_M68K_IO_H
|
||||
#define PCI_BUS_MANAGER_M68K_IO_H
|
||||
|
||||
#include <SupportDefs.h>
|
||||
|
||||
#define IOBARRIER() asm volatile("nop") /* nop flushes the instruction pipeline */
|
||||
/*XXX: sync cache/pmmu?*/
|
||||
|
||||
static inline void
|
||||
m68k_out8(vuint8 *address, uint8 value)
|
||||
{
|
||||
*address = value;
|
||||
IOBARRIER();
|
||||
}
|
||||
|
||||
|
||||
static inline void
|
||||
m68k_out16(vuint16 *address, uint16 value)
|
||||
{
|
||||
*address = value;
|
||||
IOBARRIER();
|
||||
}
|
||||
|
||||
#if _XXX_HAS_REVERSE_IO
|
||||
static inline void
|
||||
m68k_out16_reverse(vuint16 *address, uint16 value)
|
||||
{
|
||||
asm volatile("sthbrx %1, 0, %0" : : "r"(address), "r"(value));
|
||||
IOBARRIER();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static inline void
|
||||
m68k_out32(vuint32 *address, uint32 value)
|
||||
{
|
||||
*address = value;
|
||||
IOBARRIER();
|
||||
}
|
||||
|
||||
|
||||
#if _XXX_HAS_REVERSE_IO
|
||||
static inline void
|
||||
m68k_out32_reverse(vuint32 *address, uint32 value)
|
||||
{
|
||||
asm volatile("stwbrx %1, 0, %0" : : "r"(address), "r"(value));
|
||||
IOBARRIER();
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline uint8
|
||||
m68k_in8(const vuint8 *address)
|
||||
{
|
||||
uint8 value = *address;
|
||||
IOBARRIER();
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
static inline uint16
|
||||
m68k_in16(const vuint16 *address)
|
||||
{
|
||||
uint16 value = *address;
|
||||
IOBARRIER();
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
#if _XXX_HAS_REVERSE_IO
|
||||
static inline uint16
|
||||
m68k_in16_reverse(const vuint16 *address)
|
||||
{
|
||||
uint16 value;
|
||||
asm volatile("lhbrx %0, 0, %1" : "=r"(value) : "r"(address));
|
||||
IOBARRIER();
|
||||
return value;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static inline uint32
|
||||
m68k_in32(const vuint32 *address)
|
||||
{
|
||||
uint32 value = *address;
|
||||
IOBARRIER();
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
#if _XXX_HAS_REVERSE_IO
|
||||
static inline uint32
|
||||
m68k_in32_reverse(const vuint32 *address)
|
||||
{
|
||||
uint32 value;
|
||||
asm volatile("lwbrx %0, 0, %1" : "=r"(value) : "r"(address));
|
||||
IOBARRIER();
|
||||
return value;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // PCI_BUS_MANAGER_M68K_IO_H
|
||||
Loading…
Reference in New Issue