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on pre-NV40 I have activated the main mem DMA command buffer at size = 1Mb. It's working OK and is way faster on TNT1 (using the local-DMA-via-mainmem workaround) - of course. For all other cards however (so which have working local DMA command buffers) the mainmem implementation is actually a bit slower, and places a higher burder on the bus slowing down 2D a lot when 3D maxes out. All in all, I am not sure this is the way to go. It might be best to make this all a switch for nv.settings, disabled by default. Still testing... (Curious how AGP transfers will do - if possible, currently using PCI transfers)

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12843 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-05-26 14:08:36 +00:00
parent 0c7e8ef8f4
commit 5b5ef87b84
1 changed files with 22 additions and 9 deletions
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27
src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
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@ -383,20 +383,24 @@ status_t nv_acc_init_dma()
* DMA class is $002 (b0-11); * DMA class is $002 (b0-11);
* DMA target node is NVM (non-volatile memory?) * DMA target node is NVM (non-volatile memory?)
* (instead of doing PCI or AGP transfers) */ * (instead of doing PCI or AGP transfers) */
ACCW(PR_CTX1_A, 0x00007fff); /* DMA limit: tablesize is 32k bytes */ //main mem DMA buf test on pre-NV40:
// ACCW(PR_CTX1_A, 0x00007fff); /* DMA limit: tablesize is 32k bytes */
ACCW(PR_CTX1_A, 0x000fffff); /* DMA limit: tablesize is 1M bytes */
ACCW(PR_CTX2_A, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002)); ACCW(PR_CTX2_A, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002));
/* DMA access type is READ_AND_WRITE; /* DMA access type is READ_AND_WRITE;
* table is located at end of cardRAM (b12-31): * table is located at end of cardRAM (b12-31):
* It's adress needs to be at a 4kb boundary! */ * It's adress needs to be at a 4kb boundary! */
/* NVM DMA is broken on TNT1, so we use PCI-transfers back to the gfxRAM here */ /* NVM DMA is broken on TNT1, so we use PCI-transfers back to the gfxRAM here */
if (si->ps.card_type == NV04) //main mem DMA buf test on pre-NV40
if (1)//si->ps.card_type == NV04)
{ {
/* DMA target node is PCI */ /* DMA target node is PCI */
ACCW(PR_CTX0_A, 0x00023002); ACCW(PR_CTX0_A, 0x00023002);
/* point at the DMA buffer via main system memory */ /* point at the DMA buffer via main system memory */
ACCW(PR_CTX2_A, (ACCR(PR_CTX2_A) + // ACCW(PR_CTX2_A, (ACCR(PR_CTX2_A) +
(((uint32)((uint8 *)(si->framebuffer_pci))) & 0xfffff000))); // (((uint32)((uint8 *)(si->framebuffer_pci))) & 0xfffff000)));
ACCW(PR_CTX2_A, ((uint32)((uint8 *)(si->dma_buffer_pci))));
} }
//3D stuff: //3D stuff:
@ -864,8 +868,11 @@ status_t nv_acc_init_dma()
} }
/*** init DMA command buffer info ***/ /*** init DMA command buffer info ***/
if (si->ps.card_arch >= NV40A) //main mem DMA buf test on pre-NV40
{
si->dma_buffer = (void *)((char *)si->framebuffer + si->dma_buffer = (void *)((char *)si->framebuffer +
((si->ps.memory_size - 1) & 0xffff8000)); ((si->ps.memory_size - 1) & 0xffff8000));
}
LOG(4,("ACC_DMA: command buffer is at adress $%08x\n", LOG(4,("ACC_DMA: command buffer is at adress $%08x\n",
((uint32)(si->dma_buffer)))); ((uint32)(si->dma_buffer))));
/* we have issued no DMA cmd's to the engine yet */ /* we have issued no DMA cmd's to the engine yet */
@ -877,7 +884,9 @@ status_t nv_acc_init_dma()
* one word is reserved at the end of the DMA buffer to be able to instruct the * one word is reserved at the end of the DMA buffer to be able to instruct the
* engine to do a buffer wrap-around! * engine to do a buffer wrap-around!
* (DMA opcode 'noninc method': issue word $20000000.) */ * (DMA opcode 'noninc method': issue word $20000000.) */
si->engine.dma.max = 8192 - 1; //main mem DMA buf test on pre-NV40
// si->engine.dma.max = 8192 - 1;
si->engine.dma.max = ((1 * 1024 * 1024) >> 2) - 1;
/* note the current free space we have left in the DMA buffer */ /* note the current free space we have left in the DMA buffer */
si->engine.dma.free = si->engine.dma.max - si->engine.dma.current; si->engine.dma.free = si->engine.dma.max - si->engine.dma.current;
@ -1224,14 +1233,18 @@ static void nv_init_for_3D_dma(void)
static void nv_start_dma(void) static void nv_start_dma(void)
{ {
uint8 dummy; uint32 dummy;
if (si->engine.dma.current != si->engine.dma.put) if (si->engine.dma.current != si->engine.dma.put)
{ {
si->engine.dma.put = si->engine.dma.current; si->engine.dma.put = si->engine.dma.current;
/* dummy read the first adress of the framebuffer: flushes MTRR-WC buffers so /* dummy read the first adress of the framebuffer: flushes MTRR-WC buffers so
* we know for sure the DMA command buffer received all data. */ * we know for sure the DMA command buffer received all data. */
dummy = *((char *)(si->framebuffer)); //main mem DMA buf test on pre-NV40
// dummy = *((uint32 *)(si->framebuffer));
__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory"); //thomas
dummy = ACCR(STATUS);
/* actually start DMA to execute all commands now in buffer */ /* actually start DMA to execute all commands now in buffer */
/* note: /* note:
* it doesn't matter which FIFO channel's DMA registers we access, they are in * it doesn't matter which FIFO channel's DMA registers we access, they are in