tuned new PLL routine to adhere to cardspecs (should be much more precise than the old setup :)
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9179 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -387,30 +387,56 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find(
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status_t nv_dac_sys_pll_find(
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float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, uint8* p_result, uint8 test)
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{
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int m = 0, n = 0, p = 0/*, m_max*/;
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int m = 0, n = 0, p = 0;
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float error, error_best = 999999999;
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int best[3];
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float f_vco;
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int best[3];
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float f_vco, discr_low, discr_high;
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/* determine the max. reference-frequency postscaler setting for the
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* current card (see G100, G200 and G400 specs). */
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/* switch(si->ps.card_type)
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* current requested clock */
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switch (si->ps.card_arch)
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{
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case G100:
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LOG(4,("DAC: G100 restrictions apply\n"));
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m_max = 7;
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break;
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case G200:
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LOG(4,("DAC: G200 restrictions apply\n"));
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m_max = 7;
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case NV04A:
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LOG(4,("DAC: NV04 restrictions apply\n"));
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/* set phase-discriminator frequency range (Mhz) */
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/* (verified) */
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discr_low = 1.0;
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discr_high = 2.0;
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break;
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default:
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LOG(4,("DAC: G400/G400MAX restrictions apply\n"));
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m_max = 32;
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LOG(4,("DAC: NV10/NV20/NV30 restrictions apply\n"));
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/* apparantly we would get distortions on high PLL output frequencies if
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* we use the phase-discriminator at low frequencies */
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/* (low discriminator specs are verified) */
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if (req_sclk > 340.0)
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{
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/* Fpll > 340Mhz */
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discr_low = 6.74;
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}
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else
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{
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if (req_sclk > 250.0)
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{
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/* 250Mhz < Fpll <= 340Mhz */
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discr_low = 2.24;
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}
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else
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{
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/* Fpll < 250Mhz */
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discr_low = 1.0;
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}
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}
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/* (additional verified restriction on NV36) */
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if (si->ps.card_type == NV36)
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{
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if (discr_low < 3.2) discr_low = 3.2;
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}
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/* (high discriminator spec is failsafe) */
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discr_high = 14.0;
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break;
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}
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*/
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LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n"));
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LOG(4,("DAC: PLL discriminator input frequency range is %2.2fMhz - %2.2fMhz\n",
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discr_low, discr_high));
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/* Make sure the requested clock is within the PLL's operational limits */
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/* lower limit is min_system_vco divided by highest postscaler-factor */
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@ -441,24 +467,17 @@ status_t nv_dac_sys_pll_find(
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if (si->ps.ext_pll) f_vco /= 4;
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/* iterate trough all valid reference-frequency postscaler settings */
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for (m = 7; m <= 14; m++)
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for (m = 1; m <= 14; m++)
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{
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/* check if phase-discriminator will be within operational limits */
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//fixme: PLL calcs will be resetup/splitup/updated...
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if (si->ps.card_type == NV36)
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{
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if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;
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}
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else
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{
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if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;
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}
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if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high))
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continue;
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/* calculate VCO postscaler setting for current setup.. */
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n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
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/* ..and check for validity */
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if ((n < 1) || (n > 255)) continue;
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if ((n < 1) || (n > 255)) continue;
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/* find error in frequency this setting gives */
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if (si->ps.ext_pll)
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